NVMainMemory::NVMainMemory(std::string& nvmainTechIni, std::string& outputFile, std::string& traceName, uint32_t capacityMB, uint64_t _minLatency, uint32_t _domain, const g_string& _name , std::string fetcher_name) { nvmainConfig = new NVM::Config(); mm = NULL; nvmainConfig->Read(nvmainTechIni); info("NVMainControl: Reading NVMain config file: %s", nvmainTechIni.c_str()); std::string mem_type = "NVMain"; if( nvmainConfig->KeyExists("CMemType")) mem_type = nvmainConfig->GetString("CMemType"); nvmainPtr = NVM::NVMainFactory::CreateNewNVMain(mem_type); nvmainStatsPtr = new NVM::Stats(); nvmainSimInterface = new NVM::NullInterface(); nvmainEventQueue = new NVM::EventQueue(); nvmainGlobalEventQueue = new NVM::GlobalEventQueue(); nvmainTagGenerator = new NVM::TagGenerator(1000); nvmainConfig->SetSimInterface(nvmainSimInterface); SetEventQueue(nvmainEventQueue); SetStats(nvmainStatsPtr); SetTagGenerator(nvmainTagGenerator); nvmainGlobalEventQueue->SetFrequency(nvmainConfig->GetEnergy("CPUFreq") * 1000000.0); SetGlobalEventQueue(nvmainGlobalEventQueue); /* Add any specified hooks */ std::vector<std::string>& hookList = nvmainConfig->GetHooks(); previous_caching = 0; bool migrator_setted = false; for(size_t i = 0; i < hookList.size(); i++) { NVMObject *hook = NVM::HookFactory::CreateHook(hookList[i]); if( hook != NULL ) { AddHook(hook); hook->SetParent( this ); std::cout<<"this:"<<this<<std::endl; std::cout<<"nvmainPtr:"<<nvmainPtr<<std::endl; hook->Init( nvmainConfig ); } else { warn("Could not create a hook"); } if( mem_type == "RBLANVMain" && !migrator_setted && hookList[i].find("Migrator")!=std::string::npos) { nvmainPtr->SetMigrator(hook); migrator_setted = true; //add migrator to nvmain } } //Setup child and parent modules AddChild(nvmainPtr); nvmainPtr->SetParent(this); nvmainGlobalEventQueue->AddSystem(nvmainPtr, nvmainConfig); nvmainPtr->SetConfig(nvmainConfig); if( mem_type == "FineNVMain" ) { mm = dynamic_cast<NVM::FineNVMain*>(nvmainPtr); //DRAM buffer fetcher related if( (mm->reserved_channels) > 0 ) { fetcher = NVM::FetcherFactory::CreateFetcher(fetcher_name); debug_printf("set fetcher parent"); fetcher->SetParent( nvmainPtr ); nvmainPtr->AddChild(fetcher); fetcher->Init( nvmainConfig); mm->SetBlockFetcher(fetcher); //basic information about dram buffer and main memory zinfo->buffer_size = nvmainPtr->GetBufferSize(); unsigned mem_width = nvmainPtr->GetMemoryWidth(); zinfo->high_addr = (Address)1<<mem_width; //get delta time information for dynamically threshold adjustment mm->GetDeltaCycles( delta_hit_t, delta_clean_miss_t , delta_dirty_miss_t); debug_printf("nvmain_buffer size is : %llx",zinfo->buffer_size); debug_printf("base addr of nvmain dram buffer: %llx",zinfo->high_addr); debug_printf("width of main memory: %d",nvmainPtr->GetMemoryWidth()); } } else { fetcher=NULL; zinfo->buffer_size = 0; zinfo->high_addr = 0; delta_hit_t = delta_clean_miss_t = delta_dirty_miss_t = 0; } /***-----get memory size------***/ zinfo->memory_size = nvmainPtr->GetMemorySize(); curCycle = 0; updateCycle = 0; nvmain_access_count = 0; nvmain_read_access_count = 0; nvmain_write_access_count = 0; prefetch_time = 0; last_memory_access = 0; last_memory_access_cycle=0; double cpuFreq = static_cast<double>(nvmainConfig->GetEnergy("CPUFreq")); double busFreq = static_cast<double>(nvmainConfig->GetEnergy("CLK")); eventDriven = static_cast<bool>(nvmainConfig->GetBool("EventDriven")); info("NVMain: with %f cpuFreq, %f busFreq", cpuFreq, busFreq); minLatency = _minLatency; domain = _domain; // No longer necessary, now we do not tick every cycle, we use SchedEvent name = _name; // Data if( nvmainConfig->KeyExists( "IgnoreData" ) && nvmainConfig->GetString( "IgnoreData" ) == "true" ) { ignoreData = true; } else { ignoreData = false; } // NVMain stats output file std::string path = zinfo->outputDir; path += "/"; nvmainStatsFile = gm_strdup((path + name.c_str() + "-" + outputFile).c_str()); std::ofstream out(nvmainStatsFile, std::ios_base::out); out << "# nvmain stats for " << name << std::endl; out << "===" << std::endl; // Wave phase handling nextSchedRequest = NULL; nextSchedEvent = NULL; eventFreelist = NULL; e = 2.718; T = 2000; N = 999; srand((unsigned)time(NULL)); lastCycle = 0; previous_action = InitZero; previous_benefit = 0; if( zinfo->proc_fairness == false) { period_touch_vec.resize(1); period_nvm_touch.resize(1); period_access_vec.resize(1,0); period_nvm_access.resize(1,0); last_period_hotness.resize(1,0.0); last_action.resize(1,-1); } else { period_touch_vec.resize(zinfo->numProcs); period_nvm_touch.resize(zinfo->numProcs); period_access_vec.resize(zinfo->numProcs,0); period_nvm_access.resize(zinfo->numProcs,0); last_period_hotness.resize(zinfo->numProcs,0.0); last_action.resize(zinfo->numProcs,-1); } for( unsigned i=0; i< period_touch_vec.size(); i++ ) { g_map<Address, Address> tmp; g_map<Address, Address> tmp2; period_touch_vec[i] = tmp; period_nvm_touch[i] = tmp2; } fdrc.open("dram.log"); fnvm.open("nvm.log"); futex_init(&access_lock); }
int TraceMain::RunTrace( int argc, char *argv[] ) { Stats *stats = new Stats( ); Config *config = new Config( ); GenericTraceReader *trace = NULL; TraceLine *tl = new TraceLine( ); SimInterface *simInterface = new NullInterface( ); NVMain *nvmain = new NVMain( ); EventQueue *mainEventQueue = new EventQueue( ); GlobalEventQueue *globalEventQueue = new GlobalEventQueue( ); TagGenerator *tagGenerator = new TagGenerator( 1000 ); bool IgnoreData = false; bool EventDriven = false; uint64_t simulateCycles; uint64_t currentCycle; if( argc < 4 ) { std::cout << "Usage: nvmain CONFIG_FILE TRACE_FILE CYCLES [PARAM=value ...]" << std::endl; return 1; } /* Print out the command line that was provided. */ std::cout << "NVMain command line is:" << std::endl; for( int curArg = 0; curArg < argc; ++curArg ) { std::cout << argv[curArg] << " "; } std::cout << std::endl << std::endl; config->Read( argv[1] ); config->SetSimInterface( simInterface ); SetEventQueue( mainEventQueue ); SetGlobalEventQueue( globalEventQueue ); SetStats( stats ); SetTagGenerator( tagGenerator ); std::ofstream statStream; /* Allow for overriding config parameter values for trace simulations from command line. */ if( argc > 4 ) { for( int curArg = 4; curArg < argc; ++curArg ) { std::string clParam, clValue, clPair; clPair = argv[curArg]; clParam = clPair.substr( 0, clPair.find_first_of("=")); clValue = clPair.substr( clPair.find_first_of("=") + 1, std::string::npos ); std::cout << "Overriding " << clParam << " with '" << clValue << "'" << std::endl; config->SetValue( clParam, clValue ); } } if( config->KeyExists( "StatsFile" ) ) { statStream.open( config->GetString( "StatsFile" ).c_str(), std::ofstream::out | std::ofstream::app ); } if( config->KeyExists( "IgnoreData" ) && config->GetString( "IgnoreData" ) == "true" ) { IgnoreData = true; } config->GetBool( "EventDriven", EventDriven ); /* Add any specified hooks */ std::vector<std::string>& hookList = config->GetHooks( ); for( size_t i = 0; i < hookList.size( ); i++ ) { std::cout << "Creating hook " << hookList[i] << std::endl; NVMObject *hook = HookFactory::CreateHook( hookList[i] ); if( hook != NULL ) { AddHook( hook ); hook->SetParent( this ); hook->Init( config ); } else { std::cout << "Warning: Could not create a hook named `" << hookList[i] << "'." << std::endl; } } AddChild( nvmain ); nvmain->SetParent( this ); globalEventQueue->SetFrequency( config->GetEnergy( "CPUFreq" ) * 1000000.0 ); globalEventQueue->AddSystem( nvmain, config ); simInterface->SetConfig( config, true ); nvmain->SetConfig( config, "defaultMemory", true ); std::cout << "traceMain (" << (void*)(this) << ")" << std::endl; nvmain->PrintHierarchy( ); if( config->KeyExists( "TraceReader" ) ) trace = TraceReaderFactory::CreateNewTraceReader( config->GetString( "TraceReader" ) ); else trace = TraceReaderFactory::CreateNewTraceReader( "NVMainTrace" ); trace->SetTraceFile( argv[2] ); if( argc == 3 ) simulateCycles = 0; else simulateCycles = atoi( argv[3] ); std::cout << "*** Simulating " << simulateCycles << " input cycles. ("; /* * The trace cycle is assumed to be the rate that the CPU/LLC is issuing. * Scale the simulation cycles to be the number of *memory cycles* to run. */ simulateCycles = (uint64_t)ceil( ((double)(config->GetValue( "CPUFreq" )) / (double)(config->GetValue( "CLK" ))) * simulateCycles ); std::cout << simulateCycles << " memory cycles) ***" << std::endl; currentCycle = 0; while( currentCycle <= simulateCycles || simulateCycles == 0 ) { if( !trace->GetNextAccess( tl ) ) { /* Force all modules to drain requests. */ bool draining = Drain( ); std::cout << "Could not read next line from trace file!" << std::endl; /* Wait for requests to drain. */ while( outstandingRequests > 0 ) { if( EventDriven ) globalEventQueue->Cycle( 1 ); else GetChild( )->Cycle( 1 ); currentCycle++; /* Retry drain each cycle if it failed. */ if( !draining ) draining = Drain( ); } break; } NVMainRequest *request = new NVMainRequest( ); request->address = tl->GetAddress( ); request->type = tl->GetOperation( ); request->bulkCmd = CMD_NOP; request->threadId = tl->GetThreadId( ); if( !IgnoreData ) request->data = tl->GetData( ); if( !IgnoreData ) request->oldData = tl->GetOldData( ); request->status = MEM_REQUEST_INCOMPLETE; request->owner = (NVMObject *)this; /* * If you want to ignore the cycles used in the trace file, just set * the cycle to 0. */ if( config->KeyExists( "IgnoreTraceCycle" ) && config->GetString( "IgnoreTraceCycle" ) == "true" ) tl->SetLine( tl->GetAddress( ), tl->GetOperation( ), 0, tl->GetData( ), tl->GetOldData( ), tl->GetThreadId( ) ); if( request->type != READ && request->type != WRITE ) std::cout << "traceMain: Unknown Operation: " << request->type << std::endl; /* * If the next operation occurs after the requested number of cycles, * we can quit. */ if( tl->GetCycle( ) > simulateCycles && simulateCycles != 0 ) { if( EventDriven ) { globalEventQueue->Cycle( simulateCycles - currentCycle ); currentCycle += simulateCycles - currentCycle; break; } /* Just ride it out 'til the end. */ while( currentCycle < simulateCycles ) { GetChild( )->Cycle( 1 ); currentCycle++; } break; } else { /* * If the command is in the past, it can be issued. This would * occur since the trace was probably generated with an inaccurate * memory * simulator, so the cycles may not match up. Otherwise, * we need to wait. */ if( tl->GetCycle( ) > currentCycle ) { if( EventDriven ) { globalEventQueue->Cycle( tl->GetCycle() - currentCycle ); currentCycle = globalEventQueue->GetCurrentCycle( ); } else { /* Wait until currentCycle is the trace operation's cycle. */ while( currentCycle < tl->GetCycle( ) ) { if( currentCycle >= simulateCycles && simulateCycles != 0 ) break; GetChild( )->Cycle( 1 ); currentCycle++; } } if( currentCycle >= simulateCycles && simulateCycles != 0 ) break; } /* * Wait for the memory controller to accept the next command.. * the trace reader is "stalling" until then. */ while( !GetChild( )->IsIssuable( request ) ) { if( currentCycle >= simulateCycles && simulateCycles != 0 ) break; if( EventDriven ) { globalEventQueue->Cycle( 1 ); currentCycle = globalEventQueue->GetCurrentCycle( ); } else { GetChild( )->Cycle( 1 ); currentCycle++; } } outstandingRequests++; GetChild( )->IssueCommand( request ); if( currentCycle >= simulateCycles && simulateCycles != 0 ) break; } } GetChild( )->CalculateStats( ); std::ostream& refStream = (statStream.is_open()) ? statStream : std::cout; stats->PrintAll( refStream ); std::cout << "Exiting at cycle " << currentCycle << " because simCycles " << simulateCycles << " reached." << std::endl; if( outstandingRequests > 0 ) std::cout << "Note: " << outstandingRequests << " requests still in-flight." << std::endl; delete config; delete stats; return 0; }