void PCB_DRAW_PANEL_GAL::DisplayBoard( const BOARD* aBoard )
{
m_view->Clear();
// Load zones
for( int i = 0; i < aBoard->GetAreaCount(); ++i )
m_view->Add( (KIGFX::VIEW_ITEM*) ( aBoard->GetArea( i ) ) );
// Load drawings
for( BOARD_ITEM* drawing = aBoard->m_Drawings; drawing; drawing = drawing->Next() )
m_view->Add( drawing );
// Load tracks
for( TRACK* track = aBoard->m_Track; track; track = track->Next() )
m_view->Add( track );
// Load modules and its additional elements
for( MODULE* module = aBoard->m_Modules; module; module = module->Next() )
{
module->RunOnChildren( boost::bind( &KIGFX::VIEW::Add, m_view, _1 ) );
m_view->Add( module );
}
// Segzones (equivalent of ZONE_CONTAINER for legacy boards)
for( SEGZONE* zone = aBoard->m_Zone; zone; zone = zone->Next() )
m_view->Add( zone );
// Ratsnest
if( m_ratsnest )
{
m_view->Remove( m_ratsnest );
delete m_ratsnest;
}
m_ratsnest = new KIGFX::RATSNEST_VIEWITEM( aBoard->GetRatsnest() );
m_view->Add( m_ratsnest );
// Display settings
UseColorScheme( aBoard->GetColorsSettings() );
PCB_BASE_FRAME* frame = dynamic_cast<PCB_BASE_FRAME*>( GetParent() );
if( frame )
{
SetTopLayer( frame->GetActiveLayer() );
DISPLAY_OPTIONS* displ_opts = (DISPLAY_OPTIONS*) frame->GetDisplayOptions();
static_cast<KIGFX::PCB_RENDER_SETTINGS*>(
m_view->GetPainter()->GetSettings() )->LoadDisplayOptions( displ_opts );
}
m_view->RecacheAllItems( true );
}
void D_PAD::Draw( EDA_DRAW_PANEL* aPanel, wxDC* aDC, GR_DRAWMODE aDraw_mode,
const wxPoint& aOffset )
{
wxSize mask_margin; // margin (clearance) used for some non copper layers
#ifdef SHOW_PADMASK_REAL_SIZE_AND_COLOR
int showActualMaskSize = 0; /* Layer number if the actual pad size on mask layer can
* be displayed i.e. if only one layer is shown for this pad
* and this layer is a mask (solder mask or solder paste
*/
#endif
if( m_Flags & DO_NOT_DRAW )
return;
PAD_DRAWINFO drawInfo;
drawInfo.m_Offset = aOffset;
/* We can show/hide pads from the layer manager.
* options are show/hide pads on front and/or back side of the board
* For through pads, we hide them only if both sides are hidden.
* smd pads on back are hidden for all layers (copper and technical layers)
* on back side of the board
* smd pads on front are hidden for all layers (copper and technical layers)
* on front side of the board
* ECO, edge and Draw layers and not considered
*/
BOARD* brd = GetBoard();
bool frontVisible = brd->IsElementVisible( PCB_VISIBLE( PAD_FR_VISIBLE ) );
bool backVisible = brd->IsElementVisible( PCB_VISIBLE( PAD_BK_VISIBLE ) );
if( !frontVisible && !backVisible )
return;
// If pad is only on front side (no layer on back side)
// and if hide front side pads is enabled, do not draw
if( !frontVisible && !( m_layerMask & LSET::BackMask() ).any() )
return;
// If pad is only on back side (no layer on front side)
// and if hide back side pads is enabled, do not draw
if( !backVisible && !( m_layerMask & LSET::FrontMask() ).any() )
return;
PCB_BASE_FRAME* frame = (PCB_BASE_FRAME*) aPanel->GetParent();
wxCHECK_RET( frame != NULL, wxT( "Panel has no parent frame window." ) );
DISPLAY_OPTIONS* displ_opts = (DISPLAY_OPTIONS*)frame->GetDisplayOptions();
PCB_SCREEN* screen = frame->GetScreen();
if( displ_opts && displ_opts->m_DisplayPadFill == SKETCH )
drawInfo.m_ShowPadFilled = false;
else
drawInfo.m_ShowPadFilled = true;
EDA_COLOR_T color = BLACK;
if( m_layerMask[F_Cu] )
{
color = brd->GetVisibleElementColor( PAD_FR_VISIBLE );
}
if( m_layerMask[B_Cu] )
{
color = ColorMix( color, brd->GetVisibleElementColor( PAD_BK_VISIBLE ) );
}
if( color == BLACK ) // Not on a visible copper layer (i.e. still nothing to show)
{
// If the pad is on only one tech layer, use the layer color else use DARKGRAY
LSET mask_non_copper_layers = m_layerMask & ~LSET::AllCuMask();
#ifdef SHOW_PADMASK_REAL_SIZE_AND_COLOR
mask_non_copper_layers &= brd->GetVisibleLayers();
#endif
LAYER_ID pad_layer = mask_non_copper_layers.ExtractLayer();
switch( (int) pad_layer )
{
case UNDEFINED_LAYER: // More than one layer
color = DARKGRAY;
break;
case UNSELECTED_LAYER: // Shouldn't really happen...
break;
default:
color = brd->GetLayerColor( pad_layer );
#ifdef SHOW_PADMASK_REAL_SIZE_AND_COLOR
showActualMaskSize = pad_layer;
#endif
}
}
// if SMD or connector pad and high contrast mode
if( ( aDraw_mode & GR_ALLOW_HIGHCONTRAST ) &&
( GetAttribute() == PAD_SMD || GetAttribute() == PAD_CONN ) &&
displ_opts && displ_opts->m_ContrastModeDisplay )
{
// when routing tracks
if( frame->GetToolId() == ID_TRACK_BUTT )
{
LAYER_ID routeTop = screen->m_Route_Layer_TOP;
LAYER_ID routeBot = screen->m_Route_Layer_BOTTOM;
// if routing between copper and component layers,
// or the current layer is one of said 2 external copper layers,
// then highlight only the current layer.
if( ( screen->m_Active_Layer == F_Cu || screen->m_Active_Layer == B_Cu ) ||
( routeTop==F_Cu && routeBot==B_Cu ) ||
( routeTop==B_Cu && routeBot==F_Cu )
)
{
if( !IsOnLayer( screen->m_Active_Layer ) )
ColorTurnToDarkDarkGray( &color );
}
// else routing between an internal signal layer and some other
// layer. Grey out all PAD_SMD pads not on current or the single
// selected external layer.
else if( !IsOnLayer( screen->m_Active_Layer )
&& !IsOnLayer( routeTop )
&& !IsOnLayer( routeBot ) )
{
ColorTurnToDarkDarkGray( &color );
}
}
// when not edting tracks, show PAD_SMD components not on active layer
// as greyed out
else
{
if( !IsOnLayer( screen->m_Active_Layer ) )
ColorTurnToDarkDarkGray( &color );
}
}
#ifdef SHOW_PADMASK_REAL_SIZE_AND_COLOR
if( showActualMaskSize )
{
switch( showActualMaskSize )
{
case B_Mask:
case F_Mask:
mask_margin.x = mask_margin.y = GetSolderMaskMargin();
break;
case B_Paste:
case F_Paste:
mask_margin = GetSolderPasteMargin();
break;
default:
// Another layer which has no margin to handle
break;
}
}
#endif
// if Contrast mode is ON and a technical layer active, show pads on this
// layer so we can see pads on paste or solder layer and the size of the
// mask
if( ( aDraw_mode & GR_ALLOW_HIGHCONTRAST ) &&
displ_opts && displ_opts->m_ContrastModeDisplay && !IsCopperLayer( screen->m_Active_Layer ) )
{
if( IsOnLayer( screen->m_Active_Layer ) )
{
color = brd->GetLayerColor( screen->m_Active_Layer );
// In high contrast mode, and if the active layer is the mask
// layer shows the pad size with the mask clearance
switch( screen->m_Active_Layer )
{
case B_Mask:
case F_Mask:
mask_margin.x = mask_margin.y = GetSolderMaskMargin();
break;
case B_Paste:
case F_Paste:
mask_margin = GetSolderPasteMargin();
break;
default:
break;
}
}
else
color = DARKDARKGRAY;
}
if( aDraw_mode & GR_HIGHLIGHT )
ColorChangeHighlightFlag( &color, !(aDraw_mode & GR_AND) );
ColorApplyHighlightFlag( &color );
bool DisplayIsol = displ_opts && displ_opts->m_DisplayPadIsol;
if( !( m_layerMask & LSET::AllCuMask() ).any() )
DisplayIsol = false;
if( ( GetAttribute() == PAD_HOLE_NOT_PLATED ) &&
brd->IsElementVisible( NON_PLATED_VISIBLE ) )
{
drawInfo.m_ShowNotPlatedHole = true;
drawInfo.m_NPHoleColor = brd->GetVisibleElementColor( NON_PLATED_VISIBLE );
}
drawInfo.m_DrawMode = aDraw_mode;
drawInfo.m_Color = color;
drawInfo.m_DrawPanel = aPanel;
drawInfo.m_Mask_margin = mask_margin;
drawInfo.m_ShowNCMark = brd->IsElementVisible( PCB_VISIBLE( NO_CONNECTS_VISIBLE ) );
drawInfo.m_IsPrinting = screen->m_IsPrinting;
SetAlpha( &color, 170 );
/* Get the pad clearance. This has a meaning only for Pcbnew.
* for CvPcb GetClearance() creates debug errors because
* there is no net classes so a call to GetClearance() is made only when
* needed (never needed in CvPcb)
*/
drawInfo.m_PadClearance = DisplayIsol ? GetClearance() : 0;
// Draw the pad number
if( displ_opts && !displ_opts->m_DisplayPadNum )
drawInfo.m_Display_padnum = false;
if( displ_opts &&
(( displ_opts ->m_DisplayNetNamesMode == 0 ) || ( displ_opts->m_DisplayNetNamesMode == 2 )) )
drawInfo.m_Display_netname = false;
// Display net names is restricted to pads that are on the active layer
// in high contrast mode display
if( ( aDraw_mode & GR_ALLOW_HIGHCONTRAST ) &&
!IsOnLayer( screen->m_Active_Layer ) && displ_opts && displ_opts->m_ContrastModeDisplay )
drawInfo.m_Display_netname = false;
DrawShape( aPanel->GetClipBox(), aDC, drawInfo );
}
void VIA::Draw( EDA_DRAW_PANEL* panel, wxDC* aDC, GR_DRAWMODE aDrawMode, const wxPoint& aOffset )
{
wxCHECK_RET( panel != NULL, wxT( "VIA::Draw panel cannot be NULL." ) );
int radius;
PCB_LAYER_ID curr_layer = ( (PCB_SCREEN*) panel->GetScreen() )->m_Active_Layer;
int fillvia = 0;
PCB_BASE_FRAME* frame = (PCB_BASE_FRAME*) panel->GetParent();
PCB_SCREEN* screen = frame->GetScreen();
auto displ_opts = (PCB_DISPLAY_OPTIONS*)( frame->GetDisplayOptions() );
if( displ_opts->m_DisplayViaFill == FILLED )
fillvia = 1;
GRSetDrawMode( aDC, aDrawMode );
BOARD * brd = GetBoard();
COLOR4D color = frame->Settings().Colors().GetItemColor( LAYER_VIAS + GetViaType() );
if( brd->IsElementVisible( LAYER_VIAS + GetViaType() ) == false
&& !( aDrawMode & GR_HIGHLIGHT ) )
return;
// Only draw the via if at least one of the layers it crosses is being displayed
if( !( brd->GetVisibleLayers() & GetLayerSet() ).any() )
return;
if( displ_opts->m_ContrastModeDisplay )
{
if( !IsOnLayer( curr_layer ) )
color = COLOR4D( DARKDARKGRAY );
}
if( ( aDrawMode & GR_HIGHLIGHT ) && !( aDrawMode & GR_AND ) )
color.SetToLegacyHighlightColor();
color.a = 0.588;
radius = m_Width >> 1;
// for small via size on screen (radius < 4 pixels) draw a simplified shape
int radius_in_pixels = aDC->LogicalToDeviceXRel( radius );
bool fast_draw = false;
// Vias are drawn as a filled circle or a double circle. The hole will be drawn later
int drill_radius = GetDrillValue() / 2;
int inner_radius = radius - aDC->DeviceToLogicalXRel( 2 );
if( radius_in_pixels < MIN_VIA_DRAW_SIZE )
{
fast_draw = true;
fillvia = false;
}
if( fillvia )
{
GRFilledCircle( panel->GetClipBox(), aDC, m_Start + aOffset, radius, color );
}
else
{
GRCircle( panel->GetClipBox(), aDC, m_Start + aOffset, radius, 0, color );
if ( fast_draw )
return;
GRCircle( panel->GetClipBox(), aDC, m_Start + aOffset, inner_radius, 0, color );
}
if( fillvia )
{
bool blackpenstate = false;
if( screen->m_IsPrinting )
{
blackpenstate = GetGRForceBlackPenState();
GRForceBlackPen( false );
color = WHITE;
}
else
{
color = BLACK; // or DARKGRAY;
}
if( (aDrawMode & GR_XOR) == 0)
GRSetDrawMode( aDC, GR_COPY );
// Draw hole if the radius is > 1pixel.
if( aDC->LogicalToDeviceXRel( drill_radius ) > 1 )
GRFilledCircle( panel->GetClipBox(), aDC, m_Start.x + aOffset.x,
m_Start.y + aOffset.y, drill_radius, 0, color, color );
if( screen->m_IsPrinting )
GRForceBlackPen( blackpenstate );
}
else
{
if( drill_radius < inner_radius ) // We can show the via hole
GRCircle( panel->GetClipBox(), aDC, m_Start + aOffset, drill_radius, 0, color );
}
if( ShowClearance( displ_opts, this ) )
{
GRCircle( panel->GetClipBox(), aDC, m_Start + aOffset, radius + GetClearance(), 0, color );
}
// for Micro Vias, draw a partial cross : X on component layer, or + on copper layer
// (so we can see 2 superimposed microvias ):
if( GetViaType() == VIA_MICROVIA )
{
int ax, ay, bx, by;
if( IsOnLayer( B_Cu ) )
{
ax = radius; ay = 0;
bx = drill_radius; by = 0;
}
else
{
ax = ay = (radius * 707) / 1000;
bx = by = (drill_radius * 707) / 1000;
}
// lines '|' or '\'
GRLine( panel->GetClipBox(), aDC, m_Start.x + aOffset.x - ax,
m_Start.y + aOffset.y - ay,
m_Start.x + aOffset.x - bx,
m_Start.y + aOffset.y - by, 0, color );
GRLine( panel->GetClipBox(), aDC, m_Start.x + aOffset.x + bx,
m_Start.y + aOffset.y + by,
m_Start.x + aOffset.x + ax,
m_Start.y + aOffset.y + ay, 0, color );
// lines - or '/'
GRLine( panel->GetClipBox(), aDC, m_Start.x + aOffset.x + ay,
m_Start.y + aOffset.y - ax,
m_Start.x + aOffset.x + by,
m_Start.y + aOffset.y - bx, 0, color );
GRLine( panel->GetClipBox(), aDC, m_Start.x + aOffset.x - by,
m_Start.y + aOffset.y + bx,
m_Start.x + aOffset.x - ay,
m_Start.y + aOffset.y + ax, 0, color );
}
// for Buried Vias, draw a partial line : orient depending on layer pair
// (so we can see superimposed buried vias ):
if( GetViaType() == VIA_BLIND_BURIED )
{
int ax = 0, ay = radius, bx = 0, by = drill_radius;
PCB_LAYER_ID layer_top, layer_bottom;
LayerPair( &layer_top, &layer_bottom );
// lines for the top layer
RotatePoint( &ax, &ay, layer_top * 3600.0 / brd->GetCopperLayerCount( ) );
RotatePoint( &bx, &by, layer_top * 3600.0 / brd->GetCopperLayerCount( ) );
GRLine( panel->GetClipBox(), aDC, m_Start.x + aOffset.x - ax,
m_Start.y + aOffset.y - ay,
m_Start.x + aOffset.x - bx,
m_Start.y + aOffset.y - by, 0, color );
// lines for the bottom layer
ax = 0; ay = radius; bx = 0; by = drill_radius;
RotatePoint( &ax, &ay, layer_bottom * 3600.0 / brd->GetCopperLayerCount( ) );
RotatePoint( &bx, &by, layer_bottom * 3600.0 / brd->GetCopperLayerCount( ) );
GRLine( panel->GetClipBox(), aDC, m_Start.x + aOffset.x - ax,
m_Start.y + aOffset.y - ay,
m_Start.x + aOffset.x - bx,
m_Start.y + aOffset.y - by, 0, color );
}
// Display the short netname:
if( GetNetCode() == NETINFO_LIST::UNCONNECTED )
return;
if( displ_opts->m_DisplayNetNamesMode == 0 || displ_opts->m_DisplayNetNamesMode == 1 )
return;
NETINFO_ITEM* net = GetNet();
if( net == NULL )
return;
int len = net->GetShortNetname().Len();
if( len > 0 )
{
// calculate a good size for the text
int tsize = m_Width / len;
if( aDC->LogicalToDeviceXRel( tsize ) >= MIN_TEXT_SIZE )
{
tsize = (tsize * 7) / 10; // small reduction to give a better look, inside via
if( (aDrawMode & GR_XOR) == 0 )
GRSetDrawMode( aDC, GR_COPY );
EDA_RECT* clipbox = panel->GetClipBox();
DrawGraphicHaloText( clipbox, aDC, m_Start,
color, WHITE, BLACK, net->GetShortNetname(), 0,
wxSize( tsize, tsize ),
GR_TEXT_HJUSTIFY_CENTER, GR_TEXT_VJUSTIFY_CENTER,
tsize / 7, false, false );
}
}
}