string Operator::use(string name) throw(std::string) {
ostringstream e;
e << "ERROR in use(), "; // just in case
if(isSequential()) {
Signal *s;
try {
s=getSignalByName(name);
}
catch (string e2) {
e << endl << tab << e2;
throw e.str();
}
if(s->getCycle() < 0) {
e << "signal " << name<< " doesn't have (yet?) a valid cycle";
throw e.str();
}
if(s->getCycle() > currentCycle_) {
ostringstream e;
e << "active cycle of signal " << name<< " is later than current cycle, cannot delay it";
throw e.str();
}
// update the lifeSpan of s
s->updateLifeSpan( currentCycle_ - s->getCycle() );
return s->delayedName( currentCycle_ - s->getCycle() );
}
else
return name;
}
void Operator::syncCycleFromSignal(string name, bool report) throw(std::string) {
ostringstream e;
e << "ERROR in syncCycleFromSignal, "; // just in case
if(isSequential()) {
Signal* s;
try {
s=getSignalByName(name);
}
catch (string e2) {
e << endl << tab << e2;
throw e.str();
}
if( s->getCycle() < 0 ) {
ostringstream o;
o << "signal " << name << " doesn't have (yet?) a valid cycle";
throw o.str();
}
// advance cycle if needed
if (s->getCycle()>currentCycle_)
currentCycle_ = s->getCycle();
if(report)
vhdl << tab << "----------------Synchro barrier, entering cycle " << currentCycle_ << "----------------" << endl ;
// automatically update pipeline depth of the operator
if (currentCycle_ > pipelineDepth_)
pipelineDepth_ = currentCycle_;
}
}
void Operator::inPortMap(Operator* op, string componentPortName, string actualSignalName) throw(std::string) {
Signal* formal;
ostringstream e;
string name;
e << "ERROR in inPortMap(), "; // just in case
if(isSequential()) {
Signal *s;
try {
s=getSignalByName(actualSignalName);
}
catch (string e2) {
e << endl << tab << e2;
throw e.str();
}
if(s->getCycle() < 0) {
ostringstream e;
e << "signal " << actualSignalName<< " doesn't have (yet?) a valid cycle";
throw e.str();
}
if(s->getCycle() > currentCycle_) {
ostringstream e;
e << "active cycle of signal " << actualSignalName<< " is later than current cycle, cannot delay it";
throw e.str();
}
// update the lifeSpan of s
s->updateLifeSpan( currentCycle_ - s->getCycle() );
name = s->delayedName( currentCycle_ - s->getCycle() );
}
else
name = actualSignalName;
try {
formal=op->getSignalByName(componentPortName);
}
catch (string e2) {
e << endl << tab << e2;
throw e.str();
}
if (formal->type()!=Signal::in){
e << "signal " << componentPortName << " of component " << op->getName()
<< " doesn't seem to be an input port";
throw e.str();
}
// add the mapping to the mapping list of Op
op->portMap_[componentPortName] = name;
}