template<> bool
device<UserFDK>::acquire( task& task )
{
//Start the acquisition
try { task.spAgDrvr()->Acquisition->UserControl->StartSegmentation(); } catch ( _com_error& e ) { TERR(e, "StartSegmentation"); }
try { task.spAgDrvr()->Acquisition->UserControl->StartProcessing(AgMD2UserControlProcessingType1); } catch ( _com_error& e ) {
TERR( e, "StartProcessing" ); }
return true;
}
template<> bool
device<UserFDK>::readData( task& task, waveform& data )
{
static std::chrono::high_resolution_clock::time_point __uptime = std::chrono::high_resolution_clock::now();
IAgMD2LogicDevicePtr spDpuA = task.spAgDrvr()->LogicDevices->Item[L"DpuA"];
long words_32bits = task.method().nbr_of_s_to_acquire;
data.method_ = task.method();
try {
SAFEARRAY * psaWfmDataRaw(0);
spDpuA->ReadIndirectInt32(0x11, 0, words_32bits, &psaWfmDataRaw, &data.actualElements_, &data.firstValidElement_);
// workaround
data.timestamp_ = std::chrono::duration< uint64_t, std::pico >( std::chrono::high_resolution_clock::now() - __uptime ).count();
safearray_t<int32_t> sa( psaWfmDataRaw );
data.d_.resize( words_32bits );
std::copy( sa.data() + data.firstValidElement_, sa.data() + words_32bits, data.d_.begin() );
} catch ( _com_error& e ) {
TERR(e,"readData::ReadIndirectInt32");
}
return true;
}
template<> bool
device<Simulate>::initial_setup( task& task, const method& m )
{
IAgMD2LogicDevicePtr spDpuA = task.spAgDrvr()->LogicDevices->Item[L"DpuA"];
IAgMD2LogicDeviceMemoryBankPtr spDDR3A = spDpuA->MemoryBanks->Item[L"DDR3A"];
IAgMD2LogicDeviceMemoryBankPtr spDDR3B = spDpuA->MemoryBanks->Item[L"DDR3B"];
// Create smart pointers to Channels and TriggerSource interfaces
IAgMD2ChannelPtr spCh1 = task.spAgDrvr()->Channels->Item[L"Channel1"];
IAgMD2TriggerSourcePtr spTrigSrc = task.spAgDrvr()->Trigger->Sources->Item[L"External1"];
try { spCh1->TimeInterleavedChannelList = "Channel2"; } catch ( _com_error& e ) { TERR(e, "TimeInterleavedChannelList"); }
try { spCh1->PutRange(m.front_end_range); } catch ( _com_error& e ) { TERR(e, "Range"); }
try { spCh1->PutOffset(m.front_end_offset); } catch ( _com_error& e ) { TERR(e, "Offset"); }
// Setup triggering
try { task.spAgDrvr()->Trigger->ActiveSource = "External1"; } catch ( _com_error& e ) { TERR(e, "Trigger::ActiveSource"); }
try { spTrigSrc->PutLevel(m.ext_trigger_level); } catch ( _com_error& e ) { TERR(e, "TriggerSource::Level"); }
// Calibrate
ADTRACE() << "Calibrating...";
try { task.spAgDrvr()->Calibration->SelfCalibrate(); } catch ( _com_error& e ) { TERR(e, "Calibration::SelfCalibrate"); }
// Set the sample rate and nbr of samples to acquire
double sample_rate = 3.2E9;
try { task.spAgDrvr()->Acquisition->PutSampleRate(sample_rate); } catch (_com_error& e) { TERR(e,"SampleRate"); }
try { spCh1->Filter->Bypass = 1; } catch ( _com_error& e ) { TERR( e, "Bandwidth" ); } // invalid value
ADTRACE() << "Apply setup...";
try { task.spAgDrvr()->Acquisition->ApplySetup(); } catch ( _com_error& e ) { TERR( e, "ApplySetup" ); }
std::this_thread::sleep_for( std::chrono::milliseconds( 1000 ) );
return true;
}
template<> bool
device<UserFDK>::waitForEndOfAcquisition( task& task, int timeout )
{
(void)timeout;
//Wait for the end of the acquisition
long wait_for_end = 0x80000000;
IAgMD2LogicDevicePtr spDpuA = task.spAgDrvr()->LogicDevices->Item[L"DpuA"];
int count = 0;
while ( wait_for_end >= 0x80000000 ) {
std::this_thread::sleep_for( std::chrono::milliseconds( 200 ) );
try { spDpuA->ReadRegisterInt32( 0x3308, &wait_for_end ); } catch ( _com_error& e ) { TERR(e, "ReadRegisterInt32"); }
if ( ++count > 15 ) {
ADTRACE() << "U5303A::waitForEndOfAcqisition timed out";
return false;
}
}
return true;
}
template<> bool
device<UserFDK>::initial_setup( task& task, const method& m )
{
IAgMD2LogicDevicePtr spDpuA = task.spAgDrvr()->LogicDevices->Item[L"DpuA"];
IAgMD2LogicDeviceMemoryBankPtr spDDR3A = spDpuA->MemoryBanks->Item[L"DDR3A"];
IAgMD2LogicDeviceMemoryBankPtr spDDR3B = spDpuA->MemoryBanks->Item[L"DDR3B"];
// Create smart pointers to Channels and TriggerSource interfaces
IAgMD2ChannelPtr spCh1 = task.spAgDrvr()->Channels->Item[L"Channel1"];
IAgMD2TriggerSourcePtr spTrigSrc = task.spAgDrvr()->Trigger->Sources->Item[L"External1"];
try { spCh1->TimeInterleavedChannelList = "Channel2"; } catch ( _com_error& e ) { TERR(e, "TimeInterleavedChannelList"); }
try { spCh1->PutRange(m.front_end_range); } catch ( _com_error& e ) { TERR(e, "Range"); }
try { spCh1->PutOffset(m.front_end_offset); } catch ( _com_error& e ) { TERR(e, "Offset"); }
// Setup triggering
try { task.spAgDrvr()->Trigger->ActiveSource = "External1"; } catch ( _com_error& e ) { TERR(e, "Trigger::ActiveSource"); }
try { spTrigSrc->PutLevel(m.ext_trigger_level); } catch ( _com_error& e ) { TERR(e, "TriggerSource::Level"); }
// Calibrate
ADTRACE() << "Calibrating...";
try { task.spAgDrvr()->Calibration->SelfCalibrate(); } catch ( _com_error& e ) { TERR(e, "Calibration::SelfCalibrate"); }
ADTRACE() << "Set the Mode FDK...";
try { task.spAgDrvr()->Acquisition->Mode = AgMD2AcquisitionModeUserFDK; } catch (_com_error& e) { TERR(e,"Acquisition::Mode"); }
// Set the sample rate and nbr of samples to acquire
const double sample_rate = 3.2E9;
try { task.spAgDrvr()->Acquisition->PutSampleRate(sample_rate); } catch (_com_error& e) { TERR(e,"SampleRate"); }
try { task.spAgDrvr()->Acquisition->UserControl->PostTrigger = (m.nbr_of_s_to_acquire/32) + 2; } catch ( _com_error& e ) { TERR(e,"PostTrigger"); }
try { task.spAgDrvr()->Acquisition->UserControl->PreTrigger = 0; } catch ( _com_error& e ) { TERR(e,"PreTrigger"); }
// Start on trigger
try { task.spAgDrvr()->Acquisition->UserControl->StartOnTriggerEnabled = 1; } catch ( _com_error& e ) { TERR( e,"StartOnTrigger" ); }
// Full bandwidth
try { spCh1->Filter->Bypass = 1; } catch ( _com_error& e ) { TERR( e, "Bandwidth" ); }
ADTRACE() << "Apply setup...";
try { task.spAgDrvr()->Acquisition->ApplySetup(); } catch ( _com_error& e ) { TERR( e, "ApplySetup" ); }
long seg_depth = (m.nbr_of_s_to_acquire >> 5) + 5;
long seg_ctrl = 0x80000; // Averager mode, Analog trigger
if (m.invert_signal == 1) {
seg_ctrl = seg_ctrl + 0x400000;
}
long delay_next_acq = 2;
try { spDpuA->WriteRegisterInt32(0x3300, seg_depth); } catch ( _com_error& e ) { TERR(e, "WriteRegisterInt32,0x3300"); }
try { spDpuA->WriteRegisterInt32(0x3304, m.nbr_of_averages); } catch ( _com_error& e ) { TERR(e, "WriteRegisterInt32,0x3304"); }
try { spDpuA->WriteRegisterInt32(0x3308, seg_ctrl); } catch ( _com_error& e ) { TERR(e, "WriteRegisterInt32,0x3308"); }
try { spDpuA->WriteRegisterInt32(0x3318, m.nbr_of_averages); } catch ( _com_error& e ) { TERR(e, "WriteRegisterInt32,0x3318"); }
try { spDpuA->WriteRegisterInt32(0x331c, m.nsa); } catch ( _com_error& e ) { TERR(e, "WriteRegisterInt32,0x331c"); }
try { spDpuA->WriteRegisterInt32(0x3320, m.delay_to_first_s);} catch ( _com_error& e ) { TERR(e, "WriteRegisterInt32,0x3320"); }
try { spDpuA->WriteRegisterInt32(0x3324, delay_next_acq); } catch ( _com_error& e ) { TERR(e, "WriteRegisterInt32,0x3324"); }
std::this_thread::sleep_for( std::chrono::milliseconds( 1000 ) );
// Memory settings
try { spDDR3A->PutAccessControl(AgMD2LogicDeviceMemoryBankAccessControlUserFirmware); } catch (_com_error& e){TERR(e,"DDR3A::AccessControl");}
try { spDDR3B->PutAccessControl(AgMD2LogicDeviceMemoryBankAccessControlUserFirmware); } catch (_com_error& e){TERR(e,"DDR3B::AccessControl");}
std::this_thread::sleep_for( std::chrono::milliseconds( 1000 ) );
return true;
}
