// Tagged non-blocking transport forward method
virtual tlm::tlm_sync_enum nb_transport_fw(int id,
tlm::tlm_generic_payload& trans, tlm::tlm_phase& phase, sc_time& delay)
{
assert (id < targ_socket.size());
// Forward path
m_id_map[ &trans ] = id;
sc_dt::uint64 address = trans.get_address();
sc_dt::uint64 masked_address;
unsigned int target_nr = decode_address( address, masked_address);
if (target_nr < init_socket.size())
{
// Modify address within transaction
trans.set_address( masked_address );
// Forward transaction to appropriate target
tlm::tlm_sync_enum status = init_socket[target_nr]->nb_transport_fw(trans, phase, delay);
if (status == tlm::TLM_COMPLETED)
// Put back original address
trans.set_address( address );
return status;
}
else
return tlm::TLM_COMPLETED;
}
// Tagged debug transaction method
virtual unsigned int transport_dbg(int id, tlm::tlm_generic_payload& trans)
{
sc_dt::uint64 masked_address;
unsigned int target_nr = decode_address( trans.get_address(), masked_address );
if (target_nr >= init_socket.size())
return 0;
trans.set_address( masked_address );
// Forward debug transaction to appropriate target
return init_socket[target_nr]->transport_dbg( trans );
}
// Tagged TLM-2 blocking transport method
virtual void b_transport( int id, tlm::tlm_generic_payload& trans, sc_time& delay )
{
assert (id < targ_socket.size());
// Forward path
sc_dt::uint64 address = trans.get_address();
sc_dt::uint64 masked_address;
unsigned int target_nr = decode_address( address, masked_address);
if (target_nr < init_socket.size())
{
// Modify address within transaction
trans.set_address( masked_address );
// Forward transaction to appropriate target
init_socket[target_nr]->b_transport(trans, delay);
// Replace original address
trans.set_address( address );
}
}
// Tagged non-blocking transport backward method
virtual tlm::tlm_sync_enum nb_transport_bw(int id,
tlm::tlm_generic_payload& trans, tlm::tlm_phase& phase, sc_time& delay)
{
assert (id < init_socket.size());
// Backward path
// Replace original address
sc_dt::uint64 address = trans.get_address();
trans.set_address( compose_address( id, address ) );
return targ_socket[ m_id_map[ &trans ] ]->nb_transport_bw(trans, phase, delay);
}
void FastBus::b_transport(tlm::tlm_generic_payload &trans,
sc_core::sc_time &t) {
ensitlm::addr_t a = trans.get_address();
addr_map_t::iterator it = addr_map.find(addr_range(a, a));
if (it == addr_map.end()) {
std::cerr << name() << ": no target at address "
<< std::showbase << std::hex << a << std::endl;
trans.set_response_status(tlm::TLM_ADDRESS_ERROR_RESPONSE);
return;
}
trans.set_address(a - (*it).first.begin);
initiator[(*it).second]->b_transport(trans, t);
}
// Tagged TLM-2 forward DMI method
virtual bool get_direct_mem_ptr(int id,
tlm::tlm_generic_payload& trans,
tlm::tlm_dmi& dmi_data)
{
sc_dt::uint64 masked_address;
unsigned int target_nr = decode_address( trans.get_address(), masked_address );
if (target_nr >= init_socket.size())
return false;
trans.set_address( masked_address );
bool status = init_socket[target_nr]->get_direct_mem_ptr( trans, dmi_data );
// Calculate DMI address of target in system address space
dmi_data.set_start_address( compose_address( target_nr, dmi_data.get_start_address() ));
dmi_data.set_end_address ( compose_address( target_nr, dmi_data.get_end_address() ));
return status;
}
virtual void b_transport( int id, tlm::tlm_generic_payload& trans, sc_time& delay )
{
int target_nr = 0;
sc_dt::uint64 address = trans.get_address();
sc_dt::uint64 read_address = 0;
sc_dt::uint64 write_address = 0 ;
decode_address( address, read_address, write_address, id, startAdr[id]);
if(id == 0){//Writer
writeAllowed = true;
trans.set_address(write_address);
(*init_socket[target_nr])->b_transport(trans, delay);
cout << "\tID is: " << id << " - After calling b_transport in Switch: " << endl;
if(trans.is_response_ok() && writerCounter < startAdr[id + 1])
writerCounter = writerCounter + 8; // Change since now 8-bit words.
if(trans.is_response_ok() && writerCounter >= startAdr[id + 1]){
writeAllowed = false;
mtfAllowed = true;
}
}
else if(id == 1){//mtf
if(mtfAllowed == true){
if(trans.get_command() == tlm::TLM_WRITE_COMMAND)
trans.set_address( write_address );
if(trans.get_command() == tlm::TLM_READ_COMMAND)
trans.set_address(read_address);
(*init_socket[target_nr])->b_transport(trans, delay);
cout << "\tID is: " << id << " - After calling b_transport in Switch: " << endl;
if(trans.is_response_ok() && MTFCounter < startAdr[id + 1])
MTFCounter = MTFCounter + 8; // Change since now 8-bit words.
if(trans.is_response_ok() && MTFCounter >= startAdr[id + 1]){
runAllowed.write(true);
}
}
}
else if(id == 2){//runL
if(runAllowed == true){
if(trans.get_command() == tlm::TLM_WRITE_COMMAND)
trans.set_address( write_address );
if(trans.get_command() == tlm::TLM_READ_COMMAND)
trans.set_address(read_address);
(*init_socket[target_nr])->b_transport(trans, delay);
//cout << "\tID is: " << id << " - After calling b_transport in Switch: " << endl;
if(trans.is_response_ok() && runCounter < startAdr[id + 1])
runCounter = runCounter + 8; // Change since now 8-bit words.
if(trans.is_response_ok() && runCounter >= startAdr[id + 1]- startAdr[id]){
readAllowed.write(true);
}
}
}
else if(id == 3){//Reader
if(readAllowed == true){
if(trans.get_command() == tlm::TLM_READ_COMMAND)
trans.set_address(read_address );
(*init_socket[target_nr])->b_transport(trans, delay);
//cout << "\tID is: " << id << " - After calling b_transport in Switch: " << endl;
if(readCounter <= startAdr[id]- startAdr[id - 1]){
readCounter = readCounter + 8; // Change since now 8-bit words.
trans.set_response_status(tlm::TLM_INCOMPLETE_RESPONSE);
}
else if(readCounter > startAdr[id]- startAdr[id - 1]){
trans.set_response_status(tlm::TLM_OK_RESPONSE);
}
}
else
trans.set_response_status(tlm::TLM_INCOMPLETE_RESPONSE);
}
}