Beispiel #1
0
static void exynos5420_pmu_init(void)
{
	unsigned int value;
	int i;

	/*
	 * Set the CMU_RESET, CMU_SYSCLK and CMU_CLKSTOP registers
	 * for local power blocks to Low initially as per Table 8-4:
	 * "System-Level Power-Down Configuration Registers".
	 */
	for (i = 0; i < ARRAY_SIZE(exynos5420_list_disable_pmu_reg); i++)
		pmu_raw_writel(0, exynos5420_list_disable_pmu_reg[i]);

	/* Enable USE_STANDBY_WFI for all CORE */
	pmu_raw_writel(EXYNOS5420_USE_STANDBY_WFI_ALL, S5P_CENTRAL_SEQ_OPTION);

	value  = pmu_raw_readl(EXYNOS_L2_OPTION(0));
	value &= ~EXYNOS5_USE_RETENTION;
	pmu_raw_writel(value, EXYNOS_L2_OPTION(0));

	value = pmu_raw_readl(EXYNOS_L2_OPTION(1));
	value &= ~EXYNOS5_USE_RETENTION;
	pmu_raw_writel(value, EXYNOS_L2_OPTION(1));

	/*
	 * If L2_COMMON is turned off, clocks related to ATB async
	 * bridge are gated. Thus, when ISP power is gated, LPI
	 * may get stuck.
	 */
	value = pmu_raw_readl(EXYNOS5420_LPI_MASK);
	value |= EXYNOS5420_ATB_ISP_ARM;
	pmu_raw_writel(value, EXYNOS5420_LPI_MASK);

	value  = pmu_raw_readl(EXYNOS5420_LPI_MASK1);
	value |= EXYNOS5420_ATB_KFC;
	pmu_raw_writel(value, EXYNOS5420_LPI_MASK1);

	/* Prevent issue of new bus request from L2 memory */
	value = pmu_raw_readl(EXYNOS5420_ARM_COMMON_OPTION);
	value |= EXYNOS5_SKIP_DEACTIVATE_ACEACP_IN_PWDN;
	pmu_raw_writel(value, EXYNOS5420_ARM_COMMON_OPTION);

	value = pmu_raw_readl(EXYNOS5420_KFC_COMMON_OPTION);
	value |= EXYNOS5_SKIP_DEACTIVATE_ACEACP_IN_PWDN;
	pmu_raw_writel(value, EXYNOS5420_KFC_COMMON_OPTION);

	/* This setting is to reduce suspend/resume time */
	pmu_raw_writel(DUR_WAIT_RESET, EXYNOS5420_LOGIC_RESET_DURATION3);

	/* Serialized CPU wakeup of Eagle */
	pmu_raw_writel(SPREAD_ENABLE, EXYNOS5420_ARM_INTR_SPREAD_ENABLE);

	pmu_raw_writel(SPREAD_USE_STANDWFI,
			EXYNOS5420_ARM_INTR_SPREAD_USE_STANDBYWFI);

	pmu_raw_writel(0x1, EXYNOS5420_UP_SCHEDULER);

	pm_power_off = exynos5_power_off;
	pr_info("EXYNOS5420 PMU initialized\n");
}
Beispiel #2
0
int __init exynos7420_pmu_init(void)
{
	unsigned int tmp, i;

	/* Enable USE_STANDBY_WFI for all CORE */
	__raw_writel(EXYNOS5_USE_STANDBY_WFI_ALL |
		EXYNOS_USE_PROLOGNED_LOGIC_RESET, EXYNOS_CENTRAL_SEQ_OPTION);

	/* L2 use retention disable */
	tmp = __raw_readl(EXYNOS_L2_OPTION(0));
	tmp &= ~(USE_RETENTION | USE_STANDBYWFIL2);
	tmp |= USE_DEACTIVATE_ACP | USE_DEACTIVATE_ACE;
	__raw_writel(tmp, EXYNOS_L2_OPTION(0));

	/* Use SC_FEEDBACK */
	exynos_use_feedback();

	/* Initialize setting for core */
	exynos_core_option();

	/* Initialize L2 cache */
	for (i = 0; i < CLUSTER_NUM; i++) {
		tmp = __raw_readl(EXYNOS_L2_OPTION(i));
		tmp &= ~(USE_RETENTION | USE_AUTOMATIC_L2FLUSHREQ);
		if (i == 0)
			tmp |= (USE_STANDBYWFIL2 | USE_DEACTIVATE_ACP | USE_DEACTIVATE_ACE);
		__raw_writel(tmp, EXYNOS_L2_OPTION(i));
	}

	/* Ignore LPI for ASATB at ATLAS  */
	exynos_atlas_asyncbridge_ignore_lpi();

	/* UP Scheduler Enable */
	tmp = __raw_readl(EXYNOS7420_UP_SCHEDULER);
	tmp |= ENABLE_EAGLE_CPU;
	__raw_writel(tmp, EXYNOS7420_UP_SCHEDULER);

	/* Set PSHOLD port for output high and enable signal */
	tmp = __raw_readl(EXYNOS7420_PS_HOLD_CONTROL);
	tmp |= (EXYNOS_PS_HOLD_OUTPUT_HIGH | EXYNOS_PS_HOLD_EN);
	__raw_writel(tmp, EXYNOS7420_PS_HOLD_CONTROL);

	/* Skip block power down for ATLAS during automatic power down sequence */
	tmp = __raw_readl(EXYNOS7420_ATLAS_CPUSEQUENCER_OPTION);
	tmp |= SKIP_BLK_PWR_DOWN;
	__raw_writel(tmp, EXYNOS7420_ATLAS_CPUSEQUENCER_OPTION);

	/* Set clock freeze cycle before and after ARM clamp to 0 */
	__raw_writel(0x0, EXYNOS7420_ATLAS_ARMCLK_STOPCTRL);
	__raw_writel(0x0, EXYNOS7420_APOLLO_ARMCLK_STOPCTRL);

	exynos_cpu.power_up = exynos7420_secondary_up;
	exynos_cpu.power_down = exynos7420_cpu_down;
	exynos_cpu.power_state = exynos7420_cpu_state;

	pmu_cal_sys_init();

	return 0;
}
Beispiel #3
0
static const struct exynos_pmu_conf exynos5250_pmu_config[] = {
	/* { .offset = offset, .val = { AFTR, LPA, SLEEP } */
	{ EXYNOS5_ARM_CORE0_SYS_PWR_REG,		{ 0x0, 0x0, 0x2} },
	{ EXYNOS5_DIS_IRQ_ARM_CORE0_LOCAL_SYS_PWR_REG,	{ 0x0, 0x0, 0x0} },
	{ EXYNOS5_DIS_IRQ_ARM_CORE0_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
	{ EXYNOS5_ARM_CORE1_SYS_PWR_REG,		{ 0x0, 0x0, 0x2} },
	{ EXYNOS5_DIS_IRQ_ARM_CORE1_LOCAL_SYS_PWR_REG,	{ 0x0, 0x0, 0x0} },
	{ EXYNOS5_DIS_IRQ_ARM_CORE1_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
	{ EXYNOS5_FSYS_ARM_SYS_PWR_REG,			{ 0x1, 0x0, 0x0} },
	{ EXYNOS5_DIS_IRQ_FSYS_ARM_CENTRAL_SYS_PWR_REG,	{ 0x1, 0x1, 0x1} },
	{ EXYNOS5_ISP_ARM_SYS_PWR_REG,			{ 0x1, 0x0, 0x0} },
	{ EXYNOS5_DIS_IRQ_ISP_ARM_LOCAL_SYS_PWR_REG,	{ 0x0, 0x0, 0x0} },
	{ EXYNOS5_DIS_IRQ_ISP_ARM_CENTRAL_SYS_PWR_REG,	{ 0x0, 0x0, 0x0} },
	{ EXYNOS5_ARM_COMMON_SYS_PWR_REG,		{ 0x0, 0x0, 0x2} },
	{ EXYNOS5_ARM_L2_SYS_PWR_REG,			{ 0x3, 0x3, 0x3} },
	{ EXYNOS_L2_OPTION(0),				{ 0x10, 0x10, 0x0 } },
	{ EXYNOS5_CMU_ACLKSTOP_SYS_PWR_REG,		{ 0x1, 0x0, 0x1} },
	{ EXYNOS5_CMU_SCLKSTOP_SYS_PWR_REG,		{ 0x1, 0x0, 0x1} },
	{ EXYNOS5_CMU_RESET_SYS_PWR_REG,		{ 0x1, 0x1, 0x0} },
	{ EXYNOS5_CMU_ACLKSTOP_SYSMEM_SYS_PWR_REG,	{ 0x1, 0x0, 0x1} },
	{ EXYNOS5_CMU_SCLKSTOP_SYSMEM_SYS_PWR_REG,	{ 0x1, 0x0, 0x1} },
	{ EXYNOS5_CMU_RESET_SYSMEM_SYS_PWR_REG,		{ 0x1, 0x1, 0x0} },
	{ EXYNOS5_DRAM_FREQ_DOWN_SYS_PWR_REG,		{ 0x1, 0x1, 0x1} },
	{ EXYNOS5_DDRPHY_DLLOFF_SYS_PWR_REG,		{ 0x1, 0x1, 0x1} },
	{ EXYNOS5_DDRPHY_DLLLOCK_SYS_PWR_REG,		{ 0x1, 0x1, 0x1} },
	{ EXYNOS5_APLL_SYSCLK_SYS_PWR_REG,		{ 0x1, 0x0, 0x0} },
	{ EXYNOS5_MPLL_SYSCLK_SYS_PWR_REG,		{ 0x1, 0x0, 0x0} },
	{ EXYNOS5_VPLL_SYSCLK_SYS_PWR_REG,		{ 0x1, 0x0, 0x0} },
	{ EXYNOS5_EPLL_SYSCLK_SYS_PWR_REG,		{ 0x1, 0x1, 0x0} },
	{ EXYNOS5_BPLL_SYSCLK_SYS_PWR_REG,		{ 0x1, 0x0, 0x0} },
	{ EXYNOS5_CPLL_SYSCLK_SYS_PWR_REG,		{ 0x1, 0x0, 0x0} },
static int __init exynos_pmu_init(void)
{
	unsigned int value;

	exynos_pmu_config = exynos4210_pmu_config;

	if (soc_is_exynos4210()) {
		exynos_pmu_config = exynos4210_pmu_config;
		pr_info("EXYNOS4210 PMU Initialize\n");
	} else if (soc_is_exynos4212() || soc_is_exynos4412()) {
		exynos_pmu_config = exynos4x12_pmu_config;
		pr_info("EXYNOS4x12 PMU Initialize\n");
	} else if (soc_is_exynos5250()) {
		exynos5250_disable_isp();

		exynos_pmu_config = exynos5250_pmu_config;
		pm_power_off = exynos5_power_off;
		pr_info("EXYNOS5250 PMU Initialize\n");
	} else if (soc_is_exynos5420()) {
		__raw_writel(0xfffff, EXYNOS5_XXTI_DURATION3);

		/* Enable USE_STANDBY_WFI for all CORE */
		__raw_writel(EXYNOS5420_USE_STANDBY_WFI_ALL,
				S5P_CENTRAL_SEQ_OPTION);

		value = __raw_readl(EXYNOS_L2_OPTION(0));
		value &= ~EXYNOS5_USE_RETENTION;
		__raw_writel(value, EXYNOS_L2_OPTION(0));

		value = __raw_readl(EXYNOS_L2_OPTION(1));
		value &= ~EXYNOS5_USE_RETENTION;
		__raw_writel(value, EXYNOS_L2_OPTION(1));

		/*
		 * If L2_COMMON is turned off, clocks related to ATB async
		 * bridge are gated. Thus, when ISP power is gated, LPI
		 * may get stuck.
		 */
		value = __raw_readl(EXYNOS5420_LPI_MASK);
		value |= EXYNOS5420_ATB_ISP_ARM;
		__raw_writel(value, EXYNOS5420_LPI_MASK);
		value = __raw_readl(EXYNOS5420_LPI_MASK1);
		value |= EXYNOS5420_ATB_KFC;
		__raw_writel(value, EXYNOS5420_LPI_MASK1);

		/* Prevent issue of new bus request from L2 memory */
		value = __raw_readl(EXYNOS5420_ARM_COMMON_OPTION);
		value |= EXYNOS5_SKIP_DEACTIVATE_ACEACP_IN_PWDN;
		__raw_writel(value, EXYNOS5420_ARM_COMMON_OPTION);

		value = __raw_readl(EXYNOS5420_KFC_COMMON_OPTION);
		value |= EXYNOS5_SKIP_DEACTIVATE_ACEACP_IN_PWDN;
		__raw_writel(value, EXYNOS5420_KFC_COMMON_OPTION);

		/*
		 * This setting is to reduce suspend/resume time.
		 */
		__raw_writel(DUR_WAIT_RESET, EXYNOS5420_LOGIC_RESET_DURATION3);

		/* Serialized CPU wakeup of Eagle */
		__raw_writel(SPREAD_ENABLE, EXYNOS5420_ARM_INTR_SPREAD_ENABLE);
		__raw_writel(SPREAD_USE_STANDWFI,
			EXYNOS5420_ARM_INTR_SPREAD_USE_STANDBYWFI);
		__raw_writel(0x1, EXYNOS5420_UP_SCHEDULER);

		exynos_pmu_config = exynos5420_pmu_config;
		pm_power_off = exynos5_power_off;
		pr_info("EXYNOS5420 PMU Initialized\n");
	} else {
		pr_info("EXYNOS: PMU not supported\n");
	}

	return 0;
}
Beispiel #5
0
static int __init exynos_pmu_init(void)
{
	unsigned int value, i, j;

	if (soc_is_exynos4210()) {
		exynos_pmu_config = exynos4210_pmu_config;
		pr_info("EXYNOS4210 PMU Initialize\n");
	} else if (soc_is_exynos4212()) {
		exynos_pmu_config = exynos4212_pmu_config;
		pr_info("EXYNOS4212 PMU Initialize\n");
	} else if (soc_is_exynos4412()) {

		/* Follow registers should be set with 0x0 */
		for (i = 0; i < ARRAY_SIZE(exynos4_list_disable_pmu_reg); i++)
			__raw_writel(0x0, exynos4_list_disable_pmu_reg[i]);

		exynos_pmu_config = exynos4412_pmu_config;
		pr_info("EXYNOS4412 PMU Initialize\n");
	} else if (soc_is_exynos5250()) {

		/* Initialize for using delay reset assertion */
		exynos_reset_assert_ctrl(true);

		/*
		 * Set logic reset duration
		 */
		value = __raw_readl(EXYNOS5_LOGIC_RESET_DURATION3);
		value &= ~EXYNOS5_DUR_WAIT_RESET_MASK;
		value |= EXYNOS5_DUR_WAIT_RESET_MIN;
		__raw_writel(value, EXYNOS5_LOGIC_RESET_DURATION3);


		/*
		 * Follow registers should be set with 0x0
		 */
		for (i = 0; i < ARRAY_SIZE(exynos5_list_disable_pmu_reg); i++)
			__raw_writel(0x0, exynos5_list_disable_pmu_reg[i]);

		exynos_pmu_config = exynos5250_pmu_config;
		pr_info("EXYNOS5250 PMU Initialize\n");
	} else if (soc_is_exynos5410()) {
		/* Set Stable counter */
		__raw_writel(0x3a98, EXYNOS5_XXTI_DURATION3);
		__raw_writel(0x3fff, EXYNOS5_EXT_REGULATOR_DURATION3);

		/* Enable USE_STANDBY_WFI for all CORE */
		__raw_writel(EXYNOS5410_USE_STANDBY_WFI_ALL,
				EXYNOS_CENTRAL_SEQ_OPTION);

		value = __raw_readl(EXYNOS_L2_OPTION(0));
		value &= ~EXYNOS5_USE_RETENTION;
		__raw_writel(value, EXYNOS_L2_OPTION(0));

		value = __raw_readl(EXYNOS_L2_OPTION(1));
		value &= ~EXYNOS5_USE_RETENTION;
		__raw_writel(value, EXYNOS_L2_OPTION(1));

		/*
		* If turn L2_COMMON off, clocks relating ATB async bridge is gated.
		* So when ISP power is gated, LPI is stucked.
		*/
		value = __raw_readl(EXYNOS5410_LPI_MASK0);
		value |= (ATB_ISP_ARM | ATB_KFC | ATB_NOC);
		__raw_writel(value, EXYNOS5410_LPI_MASK0);

		/*
		* To prevent form issuing new bus request form L2 memory system
		* If core status is power down, should be set '1' to L2  power down
		*/
		value = __raw_readl(EXYNOS5410_ARM_COMMON_OPTION);
		value |= EXYNOS5_SKIP_DEACTIVATE_ACEACP_IN_PWDN;
		__raw_writel(value, EXYNOS5410_ARM_COMMON_OPTION);

		/*
		* DUR_WAIT_RESET : 0xF
		* This setting is to reduce suspend/resume time.
		*/
		__raw_writel(DUR_WAIT_RESET, EXYNOS5410_LOGIC_RESET_DURATION3);

		/* Serialized CPU wakeup of Eagle */
		__raw_writel(SPREAD_ENABLE, EXYNOS5410_ARM_INTR_SPREAD_ENABLE);
		__raw_writel(SPREAD_USE_STANDWFI, EXYNOS5410_ARM_INTR_SPREAD_USE_STANDBYWFI);
		__raw_writel(0x1, EXYNOS5410_UP_SCHEDULER);

		/*
		 * Set measure power on/off duration
		 * Use SC_USE_FEEDBACK
		 */
		exynos5410_init_pmu();

		exynos_reset_assert_ctrl(true);

		if (samsung_rev() < EXYNOS5410_REV_2_3) {
			for (i = 0, j = 0; (exynos5410_pmu_config[i].reg != PMU_TABLE_END); i++) {
				if (exynos5410_pmu_config[i].reg ==
					exynos5410_rev21_pmu_config[j].reg) {
					exynos5410_pmu_config[i].val[SYS_AFTR] =
						exynos5410_rev21_pmu_config[j].val[SYS_AFTR];
					exynos5410_pmu_config[i].val[SYS_LPA] =
						exynos5410_rev21_pmu_config[j].val[SYS_LPA];
					exynos5410_pmu_config[i].val[SYS_SLEEP] =
						exynos5410_rev21_pmu_config[j].val[SYS_SLEEP];

					if (exynos5410_rev21_pmu_config[++j].reg == PMU_TABLE_END)
						break;
				}
			}
		}

		/* Follow registers should be set with 0x0 */
		for (i = 0; i < ARRAY_SIZE(exynos5_list_disable_pmu_reg); i++)
			__raw_writel(0x0, exynos5_list_disable_pmu_reg[i]);

		exynos_pmu_config = exynos5410_pmu_config;
		pr_info("EXYNOS5410 PMU Initialize\n");
	} else {
		pr_info("EXYNOS: PMU not supported\n");
	}

	return 0;
}