Beispiel #1
0
nbuf_t         *
nbuf_rx_allocate(  )
{
    /* This routine alters shared data. Disable interrupts! */
    int             old_ipl = asm_set_ipl( 6 );

    /* Return a pointer to the next empty Rx Buffer Descriptor */
    int             i = rx_bd_idx;


    /* Check to see if the ring of BDs is full */
    if( rx_nbuf[i].status & RX_BD_INUSE )
        return NULL;

    /* Mark the buffer as in use */
    rx_nbuf[i].status |= RX_BD_INUSE;

    /* increment the circular index */
    rx_bd_idx = ( uint8 ) ( ( rx_bd_idx + 1 ) % NUM_RXBDS );

    /* Restore previous IPL */
    asm_set_ipl( old_ipl );

    return &rx_nbuf[i];
}
Beispiel #2
0
nbuf_t         *
nbuf_tx_allocate(  )
{
    /* This routine alters shared data. Disable interrupts! */
    int             old_ipl = asm_set_ipl( 6 );

    /* Return a pointer to the next empty Tx Buffer Descriptor */
    int             i = tx_bd_idx;

    /* Check to see if ring of BDs is full */
    if( ( tx_nbuf[i].status & TX_BD_INUSE ) || ( tx_nbuf[i].status & TX_BD_R ) )
        return NULL;

    /* Mark the buffer as Ready (in use) */
    /* FEC must set R bit in transmit routine */
    tx_nbuf[i].status |= TX_BD_INUSE;

    /* increment the circular index */
    tx_bd_idx = ( uint8 ) ( ( tx_bd_idx + 1 ) % NUM_TXBDS );

    /* Restore previous IPL */
    asm_set_ipl( old_ipl );

    return &tx_nbuf[i];
}
Beispiel #3
0
void
mcf523xfec_disable( mcf523xfec_if_t * fecif )
{
    ( void )fecif;

    int             old_ipl = asm_set_ipl( 7 );

    /* Set the Graceful Transmit Stop bit */
    MCF_FEC_TCR = ( MCF_FEC_TCR | MCF_FEC_TCR_GTS );

    /* Wait for the current transmission to complete */
    while( !( MCF_FEC_EIR & MCF_FEC_EIR_GRA ) );

    /* Clear the GRA event */
    MCF_FEC_EIR = MCF_FEC_EIR_GRA;

    /* Disable the FEC */
    MCF_FEC_ECR = 0;

    /* Disable all FEC interrupts by clearing the IMR register */
    MCF_FEC_EIMR = 0;

    /* Unconfigure the interrupt controller. */
    MCF_INTC0_ICR27 = MCF_INTC0_ICRn_IL( 0 ) | MCF_INTC0_ICRn_IP( 0 );
    MCF_INTC0_IMRL |= MCF_INTC0_IMRL_INT_MASK27;

    /* Clear the GTS bit so frames can be tranmitted when restarted */
    MCF_FEC_TCR = ( MCF_FEC_TCR & ~MCF_FEC_TCR_GTS );

    /* Disable I/O pins used by the FEC. */
    MCF_GPIO_PAR_FECI2C &= ~( MCF_GPIO_PAR_FECI2C_PAR_EMDC_FEC |
                              MCF_GPIO_PAR_FECI2C_PAR_EMDIO_FEC );
    ( void )asm_set_ipl( old_ipl );
}
Beispiel #4
0
void
mcf523xfec_enable( mcf523xfec_if_t * fecif )
{
    ( void )fecif;

    int             old_ipl = asm_set_ipl( 7 );

    /* Configure I/O pins for the FEC. */
    MCF_GPIO_PAR_FECI2C = ( MCF_GPIO_PAR_FECI2C_PAR_EMDC_FEC | MCF_GPIO_PAR_FECI2C_PAR_EMDIO_FEC );

    /* Allow interrupts by setting IMR register */
    MCF_FEC_EIMR = MCF_FEC_EIMR_RXF;

    /* Configure the interrupt controller. */
    MCF_INTC0_ICR27 = ( MCF_INTC0_ICRn_IL( MCF_FEC_INT_LEVEL ) |
                        MCF_INTC0_ICRn_IP( MCF_FEC_INT_PRIORITY ) );
    MCF_INTC0_IMRL &= ~( MCF_INTC0_IMRL_INT_MASK27 | MCF_INTC0_IMRL_MASKALL );

    /* Enable FEC */
    MCF_FEC_ECR = MCF_FEC_ECR_ETHER_EN;

    /* Indicate that there have been empty receive buffers produced */
    MCF_FEC_RDAR = 1;
    ( void )asm_set_ipl( old_ipl );
}
Beispiel #5
0
void
mcf523xfec_reset( mcf523xfec_if_t * fecif )
{
    extern void     ( *__RAMVEC[] ) (  );

    int             old_ipl = asm_set_ipl( 7 );

    /* Reset the FEC - equivalent to a hard reset */
    MCF_FEC_ECR = MCF_FEC_ECR_RESET;

    /* Wait for the reset sequence to complete */
    while( MCF_FEC_ECR & MCF_FEC_ECR_RESET );

    /* Disable all FEC interrupts by clearing the EIMR register */
    MCF_FEC_EIMR = 0;

    /* Clear any interrupts by setting all bits in the EIR register */
    MCF_FEC_EIR = 0xFFFFFFFFUL;

    /* Configure Interrupt vectors. */
    __RAMVEC[MCF_FEC_VEC_RXF] = mcf523xfec_rx_irq;

    /* Set the source address for the controller */
    MCF_FEC_PALR =
        ( fecif->self->addr[0] << 24U ) | ( fecif->self->addr[1] << 16U ) |
        ( fecif->self->addr[2] << 8U ) | ( fecif->self->addr[3] << 0U );
    MCF_FEC_PAUR = ( fecif->self->addr[4] << 24U ) | ( fecif->self->addr[5] << 16U );

    /* Initialize the hash table registers */
    MCF_FEC_IAUR = 0;
    MCF_FEC_IALR = 0;

    /* Set Receive Buffer Size */
#if RX_BUFFER_SIZE != 2048
#error "RX_BUFFER_SIZE must be set to 2048 for safe FEC operation."
#endif
    MCF_FEC_EMRBR = RX_BUFFER_SIZE - 1;

    /* Point to the start of the circular Rx buffer descriptor queue */
    MCF_FEC_ERDSR = nbuf_get_start( NBUF_RX );

    /* Point to the start of the circular Tx buffer descriptor queue */
    MCF_FEC_ETDSR = nbuf_get_start( NBUF_TX );

    /* Set the tranceiver interface to MII mode */
    MCF_FEC_RCR = MCF_FEC_RCR_MAX_FL( MCF_FEC_MTU ) | MCF_FEC_RCR_MII_MODE;

    /* Set MII Speed Control Register for 2.5Mhz */
    MCF_FEC_MSCR = MCF_FEC_MSCR_MII_SPEED( FSYS_2 / ( 2UL * 2500000UL ) );

    /* Only operate in half-duplex, no heart beat control */
    MCF_FEC_TCR = 0;

    /* Enable Debug support */
    FEC_DEBUG_INIT;
    FEC_DEBUG_RX_TIMING( 0 );
    FEC_DEBUG_TX_TIMING( 0 );
    ( void )asm_set_ipl( old_ipl );
}
Beispiel #6
0
void
nbuf_tx_release( nbuf_t * pNbuf )
{
    /* This routine alters shared data. Disable interrupts! */
    int             old_ipl = asm_set_ipl( 6 );

    /* Mark the buffer as not in use */
    pNbuf->status &= ~TX_BD_INUSE;

    /* Restore previous IPL */
    asm_set_ipl( old_ipl );
}
Beispiel #7
0
/**
 * Release a tx buffer inside buffer descriptor ring
 * @param pointer to buffer
 * @return none
 */
void
NBUF_ReadyTx( nbuf_t * pNbuf )
{
    /* This routine alters shared data. Disable interrupts! */
    uint8 old_ipl = asm_set_ipl( 6 );

    /* Mark the buffer as not in use */
    pNbuf->status |= TX_BD_R;

    /* Restore previous IPL */
    asm_set_ipl( old_ipl );
}
Beispiel #8
0
/**
 * Release a rx buffer for internal processing
 * @param pointer to buffer
 * @return none
 */
void
NBUF_ReleaseRX( nbuf_t * pNbuf )
{
    /* This routine alters shared data. Disable interrupts! */
    uint8             old_ipl = asm_set_ipl( 6 );

    /* Mark the buffer as empty and not in use */
    pNbuf->status |= RX_BD_E;
    pNbuf->status &= ~RX_BD_INUSE;

    /* Restore previous IPL */
    asm_set_ipl( old_ipl );
}
Beispiel #9
0
void
mcf5xxx_irq_disable (void)
{
    asm_set_ipl(7);
}
Beispiel #10
0
void
mcf5xxx_irq_enable (void)
{
    asm_set_ipl(0);
}
Beispiel #11
0
void
prvvPortExitCritical(  )
{
    ( void )asm_set_ipl( ( uint32 ) uiRegSR );
}
Beispiel #12
0
/* ----------------------- Start implementation -----------------------------*/
void
prvvPortEnterCritical(  )
{

    uiRegSR = asm_set_ipl( 7 );
}