void millis_init(void)
{
//AST generic clock 8MHz / (2*(249+1) = 16kHz
scif_gc_setup(AVR32_SCIF_GCLK_AST,SCIF_GCCTRL_RC8M,AVR32_SCIF_GC_DIV_CLOCK,249);
// Now enable the generic clock
scif_gc_enable(AVR32_SCIF_GCLK_AST);
//set up timer
ast_init_counter(&AVR32_AST,AST_OSC_GCLK,4,counta); //16kHz / (2^(4+1)) = 1kHz
ast_enable(&AVR32_AST);
}
/**
* \brief Detects extern OSC frequency and initialize system clocks on it
*/
void sysclk_auto_init(void)
{
int mul;
// Switch to OSC ISP
// Set max startup time to make sure any crystal will be supported
// We cannot use a TC to measure this OSC frequency
// because the master clock must be faster than the clock selected by the TC
// Configure OSC0 in crystal mode, external crystal with a fcrystal Hz frequency.
// Replace "scif_configure_osc_crystalmode(SCIF_OSC0, 16000000)" by
// inline routine to safe code (160B)
{
u_avr32_scif_oscctrl0_t u_avr32_scif_oscctrl0 = {AVR32_SCIF.oscctrl0};
// Modify : Configure the oscillator mode to crystal and set the gain according to the
// crystal frequency.
u_avr32_scif_oscctrl0.OSCCTRL0.mode = SCIF_OSC_MODE_2PIN_CRYSTAL;
u_avr32_scif_oscctrl0.OSCCTRL0.gain =
(16000000 < 900000) ? AVR32_SCIF_OSCCTRL0_GAIN_G0 :
(16000000 < 3000000) ? AVR32_SCIF_OSCCTRL0_GAIN_G1 :
(16000000 < 8000000) ? AVR32_SCIF_OSCCTRL0_GAIN_G2 :
AVR32_SCIF_OSCCTRL0_GAIN_G3;
AVR32_ENTER_CRITICAL_REGION( );
// Unlock the write-protected OSCCTRL0 register
SCIF_UNLOCK(AVR32_SCIF_OSCCTRL0);
// Write Back
AVR32_SCIF.oscctrl0 = u_avr32_scif_oscctrl0.oscctrl0;
AVR32_LEAVE_CRITICAL_REGION( );
}
// Enable the OSC0
scif_enable_osc(SCIF_OSC0, AVR32_SCIF_OSCCTRL0_STARTUP_16384_RCOSC, true);
pm_set_mclk_source(PM_CLK_SRC_OSC0);
// Initialize the AST with the internal RC oscillator
// AST will count at the frequency of 115KHz/2
if (!ast_init_counter(&AVR32_AST, AST_OSC_RC, 0, 0)) {
while (1);
}
// Enable the AST
ast_enable(&AVR32_AST);
// Detect the frequency
switch (freq_detect_start()) {
case 8000000:
mul = 11;
break;
case 16000000:
mul = 5;
break;
case 12000000:
default:
mul = 7;
break;
}
scif_pll_opt_t opt;
// Set PLL0 VCO @ 96 MHz
// Set PLL0 @ 48 MHz
opt.osc = SCIF_OSC0;
opt.lockcount = 63;
opt.div = 1;
opt.mul = mul;
opt.pll_div2 = 1;
opt.pll_wbwdisable = 0;
opt.pll_freq = 1;
// lockcount in main clock for the PLL wait lock
scif_pll0_setup((const scif_pll_opt_t *)&opt);
/* Enable PLL0 */
scif_pll0_enable();
/* Wait for PLL0 locked */
scif_wait_for_pll0_locked();
// Configure and start the RC120Mhz internal oscillator.
scif_start_rc120M();
// Since our target is to set the CPU&HSB frequency domains to 30MHz, we must
// set one wait-state and enable the High-speed read mode on the flash controller.
flashcdw_set_flash_waitstate_and_readmode(30000000UL);
// Set the CPU clock domain to 30MHz (by applying a division ratio = 4).
pm_set_clk_domain_div((pm_clk_domain_t)AVR32_PM_CLK_GRP_CPU, PM_CKSEL_DIVRATIO_4);
// Set the PBA clock domain to 30MHz (by applying a division ratio = 4).
pm_set_clk_domain_div((pm_clk_domain_t)AVR32_PM_CLK_GRP_PBA, PM_CKSEL_DIVRATIO_4);
// Set the PBB clock domain to 30MHz (by applying a division ratio = 4).
pm_set_clk_domain_div((pm_clk_domain_t)AVR32_PM_CLK_GRP_PBB, PM_CKSEL_DIVRATIO_4);
// Set the main clock source to be DFLL0.
pm_set_mclk_source(PM_CLK_SRC_RC120M);
}
int main(void)
{
enum sleepmgr_mode current_sleep_mode = SLEEPMGR_ACTIVE;
uint32_t ast_counter = 0;
/*
* Initialize the synchronous clock system to the default configuration
* set in conf_clock.h.
* \note All non-essential peripheral clocks are initially disabled.
*/
sysclk_init();
/*
* Initialize the resources used by this example to the default
* configuration set in conf_board.h
*/
board_init();
/*
* Turn the activity status LED on to inform the user that the device
* is active.
*/
gpio_set_pin_low(LED_ACTIVITY_STATUS_PIN);
/*
* Configure pin change interrupt for asynchronous wake-up (required to
* wake up from the STATIC sleep mode) and enable the EIC clock.
*
* First, enable the clock for the EIC module.
*/
sysclk_enable_pba_module(SYSCLK_EIC);
/*
* Map the interrupt line to the GPIO pin with the right peripheral
* function.
*/
gpio_enable_module_pin(WAKE_BUTTON_EIC_PIN, WAKE_BUTTON_EIC_FUNCTION);
/*
* Enable the internal pull-up resistor on that pin (because the EIC is
* configured such that the interrupt will trigger on low-level, see
* eic_options.eic_level).
*/
gpio_enable_pin_pull_up(WAKE_BUTTON_EIC_PIN);
// Init the EIC controller with the options
eic_init(&AVR32_EIC, &eic_options, sizeof(eic_options) /
sizeof(eic_options_t));
// Enable External Interrupt Controller Line
eic_enable_line(&AVR32_EIC, WAKE_BUTTON_EIC_LINE);
// Enable the AST clock.
sysclk_enable_pba_module(SYSCLK_AST);
// Initialize the AST in Counter mode
ast_init_counter(&AVR32_AST, AST_OSC_RC, AST_PSEL_RC_1_76HZ,
ast_counter);
/*
* Configure the AST to wake up the CPU when the counter reaches the
* selected alarm0 value.
*/
AVR32_AST.WER.alarm0 = 1;
// Enable the AST
ast_enable(&AVR32_AST);
// Initialize the sleep manager, lock initial mode.
sleepmgr_init();
sleepmgr_lock_mode(current_sleep_mode);
while (1) {
ast_counter = ast_get_counter_value(&AVR32_AST);
// disable alarm 0
ast_disable_alarm0(&AVR32_AST);
// Set Alarm to current time + (6/1.76) seconds
ast_counter += 6;
ast_set_alarm0_value(&AVR32_AST, ast_counter);
// Enable alarm 0
ast_enable_alarm0(&AVR32_AST);
/*
* Turn the activity status LED off to inform the user that the
* device is in a sleep mode.
*/
gpio_set_pin_high(LED_ACTIVITY_STATUS_PIN);
/*
* Go to sleep in the deepest allowed sleep mode (i.e. no
* deeper than the currently locked sleep mode).
*/
sleepmgr_enter_sleep();
/*
* Turn the activity status LED on to inform the user that the
* device is active.
*/
gpio_set_pin_low(LED_ACTIVITY_STATUS_PIN);
// After wake up, clear the Alarm0
AVR32_AST.SCR.alarm0 = 1;
// Unlock the current sleep mode.
sleepmgr_unlock_mode(current_sleep_mode);
// Add a 3s delay
cpu_delay_ms(3000, sysclk_get_cpu_hz());
// Clear the External Interrupt Line (in case it was raised).
eic_clear_interrupt_line(&AVR32_EIC, WAKE_BUTTON_EIC_LINE);
// Lock the next sleep mode.
++current_sleep_mode;
if ((current_sleep_mode >= SLEEPMGR_NR_OF_MODES)
#if UC3L && (BOARD == UC3L_EK)
/* Note concerning the SHUTDOWN sleep mode: the shutdown sleep
* mode can only be used when the UC3L supply mode is the 3.3V
* Supply Mode with 1.8V Regulated I/O Lines. That is not how
* the UC3L is powered on the ATUC3L-EK so the SHUTDOWN mode
* cannot be used on this board. Thus we skip this sleep mode
* in this example for this board.
*/
|| (current_sleep_mode == SLEEPMGR_SHUTDOWN)
#endif
) {
current_sleep_mode = SLEEPMGR_ACTIVE;
}
sleepmgr_lock_mode(current_sleep_mode);
}
}
/*!
* \brief main function : do init and loop (poll if configured so)
*/
int main(void)
{
char temp[20];
char *ptemp;
uint32_t ast_alarm;
static const gpio_map_t USART_GPIO_MAP = {
{EXAMPLE_USART_RX_PIN, EXAMPLE_USART_RX_FUNCTION},
{EXAMPLE_USART_TX_PIN, EXAMPLE_USART_TX_FUNCTION}
};
/* USART options */
static const usart_options_t USART_OPTIONS = {
.baudrate = 57600,
.charlength = 8,
.paritytype = USART_NO_PARITY,
.stopbits = USART_1_STOPBIT,
.channelmode = 0
};
#if BOARD == UC3L_EK
scif_osc32_opt_t opt = {
/* 2-pin Crystal connected to XIN32/XOUT32 and high current
* mode. */
SCIF_OSC_MODE_2PIN_CRYSTAL_HICUR,
/* oscillator startup time */
AVR32_SCIF_OSCCTRL32_STARTUP_0_RCOSC,
/* select alternate xin32_2 and xout32_2 for 32kHz crystal
* oscillator */
true,
/* disable the 1kHz output */
false,
/* enable the 32kHz output */
true
};
#else
scif_osc32_opt_t opt;
opt.mode = SCIF_OSC_MODE_2PIN_CRYSTAL;
opt.startup = AVR32_SCIF_OSCCTRL32_STARTUP_0_RCOSC;
#endif
#if BOARD == UC3L_EK
/*
* Note: on the AT32UC3L-EK board, there is no crystal/external clock
* connected to the OSC0 pinout XIN0/XOUT0. We shall then program the
* DFLL and switch the main clock source to the DFLL.
*/
pcl_configure_clocks(&pcl_dfll_freq_param);
/*
* Note: since it is dynamically computing the appropriate field values
* of the configuration registers from the parameters structure, this
* function is not optimal in terms of code size. For a code size
* optimal solution, it is better to create a new function from
* pcl_configure_clocks_dfll0() and modify it to use preprocessor
* computation from pre-defined target frequencies.
*/
#else
pcl_switch_to_osc(PCL_OSC0, FOSC0, OSC0_STARTUP);
#endif
/* Start OSC_32KHZ */
scif_start_osc32(&opt, true);
/* Assign GPIO pins to USART0. */
gpio_enable_module(USART_GPIO_MAP,
sizeof(USART_GPIO_MAP) / sizeof(USART_GPIO_MAP[0]));
/* Initialize USART in RS232 mode */
usart_init_rs232(EXAMPLE_USART, &USART_OPTIONS, FPBA);
/* Welcome sentence // 2-pin Crystal and high current mode. */
/* Crystal is connected to XIN32/XOUT32. */
usart_write_line(EXAMPLE_USART, "\x1B[2J\x1B[H\r\nATMEL\r\n");
usart_write_line(EXAMPLE_USART, "AVR32 UC3 - AST example 2\r\n");
usart_write_line(EXAMPLE_USART,
"AST 32 KHz oscillator counter example.\r\n");
usart_write_line(EXAMPLE_USART,
"Alarm0 wakeup from static sleep mode every second.\r\n");
/* Using counter mode and set it to 0 */
unsigned long ast_counter = 0;
/* Initialize the AST */
if (!ast_init_counter(&AVR32_AST,
AST_OSC_32KHZ, AST_PSEL_32KHZ_1HZ, ast_counter)) {
usart_write_line(EXAMPLE_USART,
"Error initializing the AST\r\n");
while (1) {
}
}
/* Alarm 0 sends a wakeup signal to the Power manager */
ast_enable_alarm_async_wakeup(&AVR32_AST, 0);
/* Enable the AST */
ast_enable(&AVR32_AST);
while (1) {
/* disable alarm 0 */
ast_disable_alarm0(&AVR32_AST);
/* ast_init_counter Set Alarm to current time+30 seconds */
ast_alarm = ast_counter + 1;
ast_set_alarm0_value(&AVR32_AST, ast_alarm);
/* Enable alarm 0 */
ast_enable_alarm0(&AVR32_AST);
/*
* Precautions when entering a sleep mode
* Modules communicating with external circuits should normally
* be disabled before entering a sleep mode that will stop the
* module operation.
* Make sure the USART dumps the last message completely before
* turning it off.
*/
while (!usart_tx_empty(EXAMPLE_USART)) {
}
pcl_disable_module(EXAMPLE_USART_CLOCK_MASK);
/*
* Since we're going into a sleep mode deeper than IDLE, all HSB
* masters must be stopped before entering the sleep mode.
* Note: since we're not using the PDCA, we don't have to stop
*it.
*/
/*
* If there is a chance that any PB write operations are
*incomplete,
* the CPU should perform a read operation from any register on
*the
* PB bus before executing the sleep instruction.
*/
AVR32_INTC.ipr[0]; /* Dummy read */
/* Go into static sleep mode */
SLEEP(AVR32_PM_SMODE_STATIC);
/* We're out of the static sleep mode now => re-enable the USART
* module */
pcl_enable_module(EXAMPLE_USART_CLOCK_MASK);
/* After wake up, clear the Alarm0 */
ast_clear_alarm_status_flag(&AVR32_AST, 0);
/* Toggle Led0 */
gpio_tgl_gpio_pin(LED0_GPIO);
/* Set cursor to the position (1; 6) */
usart_write_line(EXAMPLE_USART, "\x1B[6;1H");
ast_counter = ast_get_counter_value(&AVR32_AST);
usart_write_line(EXAMPLE_USART, "Timer: ");
ptemp = print_i(temp, ast_counter);
usart_write_line(EXAMPLE_USART, ptemp);
usart_write_line(EXAMPLE_USART, " sec ");
}
}
int main(void)
{
enum sleepmgr_mode current_sleep_mode = SLEEPMGR_ACTIVE;
uint32_t ast_counter = 0;
/*
* Initialize the synchronous clock system to the default configuration
* set in conf_clock.h.
* \note All non-essential peripheral clocks are initially disabled.
*/
sysclk_init();
/*
* Initialize the resources used by this example to the default
* configuration set in conf_board.h
*/
board_init();
/*
* Turn the activity status LED on to inform the user that the device
* is active.
*/
ioport_set_pin_level(LED_ACTIVITY_STATUS_PIN, LED_STATUS_ON);
osc_priv_enable_osc32();
/* Enable the AST clock. */
sysclk_enable_pba_module(SYSCLK_AST);
/* Initialize the AST in Counter mode. */
ast_init_counter(AST, AST_OSC_1KHZ, AST_PSEL_32KHZ_1HZ - 6,
ast_counter);
/*
* Configure the AST to wake up the CPU when the counter reaches the
* selected periodic0 value.
*/
ast_set_periodic0_value(AST,AST_PSEL_32KHZ_1HZ - 3);
ast_enable_periodic_interrupt(AST,0);
ast_enable_periodic_async_wakeup(AST,0);
ast_enable_periodic0(AST);
ast_clear_periodic_status_flag(AST,0);
NVIC_ClearPendingIRQ(AST_PER_IRQn);
NVIC_EnableIRQ(AST_PER_IRQn);
/* Enable the AST. */
ast_enable(AST);
/* AST can wakeup the device */
bpm_enable_wakeup_source(BPM, (1 << BPM_BKUPWEN_AST));
// Initialize the sleep manager, lock initial mode.
sleepmgr_init();
sleepmgr_lock_mode(current_sleep_mode);
while (1) {
/*
* Turn the activity status LED off to inform the user that the
* device is in a sleep mode.
*/
ioport_set_pin_level(LED_ACTIVITY_STATUS_PIN, LED_STATUS_OFF);
/*
* Go to sleep in the deepest allowed sleep mode (i.e. no
* deeper than the currently locked sleep mode).
*/
sleepmgr_enter_sleep();
/*
* Turn the activity status LED on to inform the user that the
* device is active.
*/
ioport_set_pin_level(LED_ACTIVITY_STATUS_PIN, LED_STATUS_ON);
/* Unlock the current sleep mode. */
sleepmgr_unlock_mode(current_sleep_mode);
/* Add a 3s delay. */
delay_s(3);
/* Lock the next sleep mode. */
++current_sleep_mode;
if ((current_sleep_mode >= SLEEPMGR_NR_OF_MODES)) {
current_sleep_mode = SLEEPMGR_ACTIVE;
}
sleepmgr_lock_mode(current_sleep_mode);
}
}
/**
* \brief Initializes the ACIFB module with trigger
* - Start the GCLK for ACIFB
* - Initialize the trigger mode & compare interrupts for ACIFB
*
* \retval STATUS_OK Configuration OK
* \retval ERR_TIMEOUT Timeout on configuring ACIFB module
* \retval ERR_BUSY ACIFB module unable to configure the trigger
*/
static status_code_t ac_init()
{
/* struct genclk_config gcfg; */
uint32_t div = sysclk_get_pba_hz() / AC_GCLK_FREQUENCY;
scif_gc_setup(AC_GCLK_ID, AC_GCLK_SRC, AVR32_GC_DIV_CLOCK, div);
/* Now enable the generic clock */
scif_gc_enable(AC_GCLK_ID);
/* GPIO pin/acifb - function map. */
static const gpio_map_t ACIFB_GPIO_MAP = {
{EXAMPLE_ACIFBP_PIN, EXAMPLE_ACIFBP_FUNCTION},
{EXAMPLE_ACIFBN_PIN, EXAMPLE_ACIFBN_FUNCTION},
};
/* ACIFB Configuration */
const acifb_t acifb_opt = {
.sut = 6, /* Resolution mode */
.actest = TESTMODE_OFF,
.eventen = true
};
/* ACIFB Channel Configuration */
const acifb_channel_t acifb_channel_opt = {
/* Filter length */
.filter_len = 0,
/* Hysteresis value */
.hysteresis_value = 0,
/* Output event when ACOUT is zero? */
.event_negative = false,
/* Output event when ACOUT is one? */
.event_positive = false,
/* Set the positive input */
.positive_input = PI_ACP,
/* Set the negative input */
.negative_input = NI_ACN,
/* Set the comparator mode */
.mode = MODE_EVENT_TRIGGERED,
/* Interrupt settings */
.interrupt_settings = IS_VINP_LT_VINN,
/* Analog comparator channel number */
.ac_n = EXAMPLE_ACIFB_CHANNEL
};
/* Enable Analog Comparator clock */
sysclk_enable_pba_module(SYSCLK_ACIFB);
/* Disable pullup on ACIFB channel input pins */
gpio_disable_pin_pull_up(EXAMPLE_ACIFBP_PIN);
gpio_disable_pin_pull_up(EXAMPLE_ACIFBN_PIN);
/* Enable the ACIFB pins */
gpio_enable_module(ACIFB_GPIO_MAP,
sizeof(ACIFB_GPIO_MAP) / sizeof(ACIFB_GPIO_MAP[0]));
/* Configure the ACIFB peripheral */
acifb_setup_and_enable(acifb, &acifb_opt);
/* Configure the ACIFB channel with interrupt & trigger */
acifb_channels_setup(acifb, &acifb_channel_opt, AC_NB_CHANNELS);
/* Disable global interrupts */
cpu_irq_disable();
/*
* Initialize the interrupt vectors
* Note: This function adds nothing for IAR as the interrupts are
* handled by the IAR compiler itself. It provides an abstraction
* between GCC & IAR compiler to use interrupts.
* Refer function implementation in interrupt_avr32.h
*/
irq_initialize_vectors();
/*
* Register the ACIFB interrupt handler
* Note: This function adds nothing for IAR as the interrupts are
* handled by the IAR compiler itself. It provides an abstraction
* between GCC & IAR compiler to use interrupts.
* Refer function implementation in interrupt_avr32.h
*/
irq_register_handler(&ACIFB_interrupt_handler, AVR32_ACIFB_IRQ,
AC_INTERRUPT_PRIORITY);
/* Enable Analog Comparator Channel interrupt */
acifb_enable_comparison_interrupt(acifb, EXAMPLE_ACIFB_CHANNEL);
/* Enable global interrupts */
cpu_irq_enable();
return STATUS_OK;
} /* End of ac_init() */
/**
* \brief Asynchronous Timer Initialization
* - Start the 32KHz Oscillator
* - Initializes the AST module with periodic trigger events
*
* \retval STATUS_OK Configuration OK
* \retval ERR_BUSY Error in configuring the AST module
*/
static status_code_t ast_init()
{
/* Initial Count value to write in AST */
unsigned long ast_counter = 0;
/* Set the prescaler to set a periodic trigger from AST */
avr32_ast_pir0_t pir = {
.insel = AST_TRIGGER_PRESCALER
};
/* Set the OSC32 parameters */
scif_osc32_opt_t osc32_opt = {
.mode = SCIF_OSC_MODE_2PIN_CRYSTAL_HICUR,
.startup = OSC32_STARTUP_8192,
.pinsel = BOARD_OSC32_PINSEL,
.en1k = false,
.en32k = true
};
/* Enable the 32KHz Oscillator */
scif_start_osc32(&osc32_opt, true);
/* Enable the Peripheral Event System Clock */
sysclk_enable_hsb_module(SYSCLK_EVENT);
/* Enable PBA clock for AST clock to switch its source */
sysclk_enable_pba_module(SYSCLK_AST);
/* Initialize the AST in counter mode */
if (!ast_init_counter(&AVR32_AST, AST_CLOCK_SOURCE, AST_PRESCALER,
ast_counter)) {
return ERR_BUSY;
}
/* Initialize the periodic value register with the prescaler */
ast_set_periodic0_value(&AVR32_AST, pir);
/* Enable the AST periodic event */
ast_enable_periodic0(&AVR32_AST);
/* Clear All AST Interrupt request and clear SR */
ast_clear_all_status_flags(&AVR32_AST);
/* Enable the AST */
ast_enable(&AVR32_AST);
/* Disable PBA clock for AST after switching its source to OSC32 */
sysclk_disable_pba_module(SYSCLK_AST);
return STATUS_OK;
} /* End of ast_init() */
/**
* \brief Low Power Configuration
* Initializes the power saving measures to reduce power consumption
* - Enable pull-ups on GPIO pins
* - Disable the clocks to unwanted modules
* - Disable internal voltage regulator when in 1.8V supply mode
*/
static void power_save_measures_init()
{
uint8_t i;
uint32_t gpio_mask[AVR32_GPIO_PORT_LENGTH] = {0};
/*
* Enable internal pull-ups on all unused GPIO pins
* Note: Pull-ups on Oscillator or JTAG pins can be enabled only if they
* are not used as an oscillator or JTAG pin respectively.
*/
for (i = 0; i < (sizeof(gpio_used_pins) / sizeof(uint32_t)); i++) {
gpio_mask[gpio_used_pins[i] >>
5] |= 1 << (gpio_used_pins[i] & 0x1F);
}
for (i = 0; i < AVR32_GPIO_PORT_LENGTH; i++) {
gpio_configure_group(i, ~(gpio_mask[i]),
GPIO_PULL_UP | GPIO_DIR_INPUT);
}
/* Disable OCD clock which is not disabled by sysclk service */
sysclk_disable_cpu_module(SYSCLK_OCD);
#if POWER_SUPPLY_MODE_1_8V
/*
* When using 1.8V Single supply mode, the Voltage Regulator can be
* shut-down using the code below, in-order to save power.
* See Voltage Regulator Calibration Register in datasheet for more
*info.
* CAUTION: When using 3.3V Single supply mode, the Voltage Regulator
* cannot be shut-down and the application will hang in this loop.
*/
uint32_t tmp = (AVR32_SCIF.vregcr);
tmp &= (~(1 << 5 | 1 << 18));
AVR32_SCIF.unlock = 0xAA000000 | AVR32_SCIF_VREGCR;
AVR32_SCIF.vregcr = tmp;
/* Wait until internal voltage regulator is disabled. */
while ((AVR32_SCIF.vregcr & 0x00040020)) {
}
#endif
} /* End of power_save_measures_init() */
/**
* \brief Detects extern OSC frequency and initialize system clocks on it
*/
void sysclk_auto_init(void)
{
int mul;
// Switch to OSC ISP
// Set max startup time to make sure any crystal will be supported
// We cannot use a TC to measure this OSC frequency
// because the master clock must be faster than the clock selected by the TC
// Configure OSC0 in crystal mode, external crystal with a fcrystal Hz frequency.
// Replace "scif_configure_osc_crystalmode(SCIF_OSC0, 16000000)" by
// inline routine to safe code (160B)
{
typedef union
{
unsigned long oscctrl[2];
avr32_scif_oscctrl_t OSCCTRL[2];
} u_avr32_scif_oscctrl_t;
u_avr32_scif_oscctrl_t u_avr32_scif_oscctrl;
// Read Register
u_avr32_scif_oscctrl.OSCCTRL[SCIF_OSC0] = AVR32_SCIF.OSCCTRL[SCIF_OSC0] ;
// Modify : Configure the oscillator mode to crystal and set the gain according to the
// crystal frequency.
u_avr32_scif_oscctrl.OSCCTRL[SCIF_OSC0].mode = SCIF_OSC_MODE_2PIN_CRYSTAL;
u_avr32_scif_oscctrl.OSCCTRL[SCIF_OSC0].gain =
(16000000 < 900000) ? AVR32_SCIF_OSCCTRL0_GAIN_G0 :
(16000000 < 3000000) ? AVR32_SCIF_OSCCTRL0_GAIN_G1 :
(16000000 < 8000000) ? AVR32_SCIF_OSCCTRL0_GAIN_G2 :
AVR32_SCIF_OSCCTRL0_GAIN_G3;
AVR32_ENTER_CRITICAL_REGION( );
// Unlock the write-protected OSCCTRL0 register
SCIF_UNLOCK(AVR32_SCIF_OSCCTRL);
// Write Back
AVR32_SCIF.OSCCTRL[SCIF_OSC0] = u_avr32_scif_oscctrl.OSCCTRL[SCIF_OSC0];
AVR32_LEAVE_CRITICAL_REGION( );
}
// Enable the OSC0
scif_enable_osc(SCIF_OSC0, AVR32_SCIF_OSCCTRL0_STARTUP_16384_RCOSC, true);
flashc_set_flash_waitstate_and_readmode(16000000);
pm_set_mclk_source(PM_CLK_SRC_OSC0);
// Initialize the AST with the internal RC oscillator
// AST will count at the frequency of 115KHz/2
if (!ast_init_counter(&AVR32_AST, AST_OSC_RC, 0, 0)) {
while (1);
}
// Enable the AST
ast_enable(&AVR32_AST);
// Detect the frequency
switch (freq_detect_start()) {
case 8000000:
mul = 5;
break;
case 16000000:
mul = 2;
break;
case 12000000:
default:
mul = 3;
break;
}
scif_pll_opt_t opt;
// Set PLL0 VCO @ 96 MHz
// Set PLL0 @ 48 MHz
opt.osc = SCIF_OSC0;
opt.lockcount = 63;
opt.div = 0;
opt.mul = mul;
opt.pll_div2 = 1;
opt.pll_wbwdisable = 0;
opt.pll_freq = 1;
// lockcount in main clock for the PLL wait lock
scif_pll_setup(SCIF_PLL0, &opt);
/* Enable PLL0 */
scif_pll_enable(SCIF_PLL0);
/* Wait for PLL0 locked */
scif_wait_for_pll_locked(SCIF_PLL0);
// Use 1 flash wait state
flashc_set_wait_state(1);
// Switch the main clock to PLL0
pm_set_mclk_source(PM_CLK_SRC_PLL0);
// fCPU: 48 MHz // USBC request a CPU clock >25MHz
// fPBA: 48 MHz
// fHSB: 48 MHz
// fPBB: 48 MHz must be the same that CPU
// fPBC: 48 MHz
pm_disable_clk_domain_div(PM_CLK_DOMAIN_0); // CPU
pm_disable_clk_domain_div(PM_CLK_DOMAIN_1); // HSB
pm_disable_clk_domain_div(PM_CLK_DOMAIN_2); // PBA
pm_disable_clk_domain_div(PM_CLK_DOMAIN_3); // PBB
pm_disable_clk_domain_div(PM_CLK_DOMAIN_4); // PBC
// Use 0 flash wait state
flashc_set_wait_state(1);
}
void time_keeper_init(void)
{
ast_init_counter(&AVR32_AST, AST_OSC_PB, AST_PRESCALER_SETTING, 0);
ast_enable(&AVR32_AST);
}
/**
* \brief Initializes the ADCIFB module with trigger
* - Initialize the trigger mode & compare interrupts for ADCIFB
*
* \retval STATUS_OK Configuration OK
* \retval ERR_TIMEOUT Timeout on configuring ADCIFB module
* \retval ERR_BUSY ADCIFB module unable to configure the trigger
*/
static status_code_t adc_init()
{
/* GPIO pin/adc - function map. */
static const gpio_map_t ADCIFB_GPIO_MAP = {
{EXAMPLE_ADCIFB_PIN, EXAMPLE_ADCIFB_FUNCTION}
};
/* ADCIFB Configuration */
adcifb_opt_t adcifb_opt = {
/* Resolution mode */
.resolution = AVR32_ADCIFB_ACR_RES_10BIT,
/* Channels Sample & Hold Time in [0,15] */
.shtim = ADC_SAMPLE_HOLD_TIME,
/* ADC Clock Prescaler */
.ratio_clkadcifb_clkadc = (sysclk_get_pba_hz()) / ADC_FREQUENCY,
.startup = ADC_STARTUP_TIME,
/* ADCIFB Sleep Mode enabled */
.sleep_mode_enable = true
};
/* Disable pull up on ADCIFB channel input pin */
gpio_disable_pin_pull_up(EXAMPLE_ADCIFB_PIN);
/* Enable the ADC pins */
gpio_enable_module(ADCIFB_GPIO_MAP,
sizeof(ADCIFB_GPIO_MAP) / sizeof(ADCIFB_GPIO_MAP[0]));
/* Enable ADCIFB clock */
sysclk_enable_pba_module(SYSCLK_ADCIFB);
/* Configure the ADCIFB peripheral */
if (adcifb_configure(adcifb, &adcifb_opt)) {
/* Error configuring the ADCIFB */
return ERR_TIMEOUT;
}
/* Configure the trigger for ADCIFB peripheral */
if (adcifb_configure_trigger(adcifb, AVR32_ADCIFB_TRGR_TRGMOD_EVT, 0)) {
/* Error configuring the trigger for ADCIFB */
return ERR_BUSY;
}
/* Enable ADCIFB Channel 0 */
adcifb_channels_enable(adcifb, EXAMPLE_ADCIFB_CHANNEL);
/* Disable global interrupts */
cpu_irq_disable();
/*
* Initialize the interrupt vectors
* Note: This function adds nothing for IAR as the interrupts are
* handled by the IAR compiler itself. It provides an abstraction
* between GCC & IAR compiler to use interrupts.
* Refer function implementation in interrupt_avr32.h
*/
irq_initialize_vectors();
/*
* Register the ADCIFB interrupt handler
* Note: This function adds nothing for IAR as the interrupts are
* handled by the IAR compiler itself. It provides an abstraction
* between GCC & IAR compiler to use interrupts.
* Refer function implementation in interrupt_avr32.h
*/
irq_register_handler(&ADCIFB_interrupt_handler, AVR32_ADCIFB_IRQ,
ADC_INTERRUPT_PRIORITY);
/*
* Set the threshold value in CVR.LV register to generate interrupt
* when the value detected is above the threshold.
* 1.500 V with 10-bit resolution
*/
adcifb_set_high_compare_value(adcifb, ADC_COMPARE_VALUE);
/* Enable the Analog Compare option in ADCIFB */
adcifb_enable_analog_compare_mode(adcifb);
/* Enable the data ready interrupt for ADCIFB */
adcifb_enable_compare_gt_interrupt(adcifb);
return STATUS_OK;
} /* End of adc_init() */
/**
* \brief Asynchronous Timer Initialization
* - Start the 32KHz Oscillator
* - Initializes the AST module with periodic trigger events
*
* \retval STATUS_OK Configuration OK
* \retval ERR_TIMEOUT Error in configuring the AST module
*/
static status_code_t ast_init()
{
/* Initial Count value to write in AST */
unsigned long ast_counter = 0;
/* Set the prescaler to set a periodic trigger from AST */
avr32_ast_pir0_t pir = {
.insel = AST_TRIGGER_PRESCALER
};
/* Set the OSC32 parameters */
scif_osc32_opt_t osc32_opt = {
.mode = SCIF_OSC_MODE_2PIN_CRYSTAL_HICUR,
.startup = OSC32_STARTUP_8192,
.pinsel = BOARD_OSC32_PINSEL,
.en1k = false,
.en32k = true
};
/* Enable the 32KHz Oscillator */
scif_start_osc32(&osc32_opt, true);
/* Enable the Peripheral Event System Clock */
sysclk_enable_hsb_module(SYSCLK_EVENT);
/* Enable PBA clock for AST clock to switch its source */
sysclk_enable_pba_module(SYSCLK_AST);
/* Initialize the AST in counter mode */
if (!ast_init_counter(&AVR32_AST, AST_CLOCK_SOURCE, AST_PRESCALER,
ast_counter)) {
return ERR_TIMEOUT;
}
/* Initialize the periodic value register with the prescaler */
ast_set_periodic0_value(&AVR32_AST, pir);
/* Enable the AST periodic event */
ast_enable_periodic0(&AVR32_AST);
/* Clear All AST Interrupt request and clear SR */
ast_clear_all_status_flags(&AVR32_AST);
/* Enable the AST */
ast_enable(&AVR32_AST);
/* Disable PBA clock for AST after switching its source to OSC32 */
sysclk_disable_pba_module(SYSCLK_AST);
return STATUS_OK;
} /* End of ast_init() */
/**
* \brief Low Power Configuration
* Initializes the power saving measures to reduce power consumption
* - Enable pullups on GPIO pins
* - Disable the clocks to unused modules
* - Disable internal voltage regulator when in 1.8V supply mode
*/
static void power_save_measures_init()
{
uint8_t i;
uint32_t gpio_mask[AVR32_GPIO_PORT_LENGTH] = {0};
/*
* Enable internal pull-ups on all unused GPIO pins
* Note: Pull-ups on Oscillator or JTAG pins can be enabled only if they
* are not used as an oscillator or JTAG pin respectively.
*/
for (i = 0; i < (sizeof(gpio_used_pins) / sizeof(uint32_t)); i++) {
gpio_mask[gpio_used_pins[i] >>
5] |= 1 << (gpio_used_pins[i] & 0x1F);
}
for (i = 0; i < AVR32_GPIO_PORT_LENGTH; i++) {
gpio_configure_group(i, ~(gpio_mask[i]),
GPIO_PULL_UP | GPIO_DIR_INPUT);
}
/* Disable OCD clock which is not disabled by sysclk service */
sysclk_disable_cpu_module(SYSCLK_OCD);
#if POWER_SUPPLY_MODE_1_8V
/*
* When using 1.8V Single supply mode, the Voltage Regulator can be
* shut-down using the code below, in-order to save power.
* See Voltage Regulator Calibration Register in datasheet for more
*info.
* CAUTION: When using 3.3V Single supply mode, the Voltage Regulator
* cannot be shut-down and the application will hang in this loop.
*/
uint32_t tmp = (AVR32_SCIF.vregcr);
tmp &= (~(1 << 5 | 1 << 18));
AVR32_SCIF.unlock = 0xAA000000 | AVR32_SCIF_VREGCR;
AVR32_SCIF.vregcr = tmp;
/* Wait until internal voltage regulator is disabled. */
while ((AVR32_SCIF.vregcr & 0x00040020)) {
}
#endif
} /* End of power_save_measures_init() */
static status_code_t ast_init()
{
/* Initial Count value to write in AST */
unsigned long ast_counter = 0;
/* Set the prescaler to set a periodic trigger from AST */
avr32_ast_pir0_t pir = {
.insel = AST_TRIGGER_PRESCALER
};
/* Set the OSC32 parameters */
scif_osc32_opt_t osc32_opt = {
#if BOARD_OSC32_IS_XTAL
.mode = SCIF_OSC_MODE_2PIN_CRYSTAL_HICUR,
#else
.mode = SCIF_OSC_MODE_EXT_CLK,
#endif
.startup = OSC32_STARTUP_8192,
.pinsel = BOARD_OSC32_PINSEL,
.en1k = false,
.en32k = true
};
/* Enable the 32KHz Oscillator */
scif_start_osc32(&osc32_opt, true);
/* Enable the Peripheral Event System Clock */
sysclk_enable_hsb_module(SYSCLK_EVENT);
/* Enable PBA clock for AST clock to switch its source */
sysclk_enable_pba_module(SYSCLK_AST);
/* Initialize the AST in counter mode */
if (!ast_init_counter(&AVR32_AST, AST_CLOCK_SOURCE, AST_PRESCALER,
ast_counter)) {
return ERR_BUSY; /* Check AST timer */
}
/* Initialize the periodic value register with the prescaler */
ast_set_periodic0_value(&AVR32_AST, pir);
/* Enable the AST periodic event */
ast_enable_periodic0(&AVR32_AST);
/* Clear All AST Interrupt request and clear SR */
ast_clear_all_status_flags(&AVR32_AST);
/* Enable the AST */
ast_enable(&AVR32_AST);
/* Disable PBA clock for AST after switching its source to OSC32 */
sysclk_disable_pba_module(SYSCLK_AST);
return STATUS_OK;
} /* End of ast_init() */
#endif
/**
* \brief Low Power Configuration
* Initializes the power saving measures to reduce power consumption
* - Enable pull ups on GPIO pins
* - Disable the clocks to unwanted modules
* - Disable internal voltage regulator when in 1.8V supply mode
*/
void power_save_measures_init()
{
uint8_t i;
uint32_t gpio_mask[AVR32_GPIO_PORT_LENGTH] = {0};
/*
* Enable internal pull-ups on all unused GPIO pins
* Note: Pull-ups on Oscillator or JTAG pins can be enabled only if they
* are not used as an oscillator or JTAG pin respectively.
*/
for (i = 0; i < (sizeof(gpio_used_pins) / sizeof(uint32_t)); i++) {
gpio_mask[gpio_used_pins[i] >>
5] |= 1 << (gpio_used_pins[i] & 0x1F);
}
for (i = 0; i < AVR32_GPIO_PORT_LENGTH; i++) {
gpio_configure_group(i, gpio_mask[i],
GPIO_PULL_UP | GPIO_DIR_INPUT);
}
/* Disable OCD clock which is not disabled by sysclk service */
sysclk_disable_cpu_module(SYSCLK_OCD);
#if POWER_SUPPLY_MODE_1_8V
/*
* When using 1.8V Single supply mode, the Voltage Regulator can be
* shut-down using the code below, in-order to save power.
* See Voltage Regulator Calibration Register in datasheet for more
*info.
* CAUTION: When using 3.3V Single supply mode, the Voltage Regulator
* cannot be shut-down and the application will hang in this loop.
*/
uint32_t tmp = (AVR32_SCIF.vregcr);
tmp &= (~(1 << 5));
AVR32_SCIF.unlock = 0xAA000000 | AVR32_SCIF_VREGCR;
AVR32_SCIF.vregcr = tmp;
/* Wait until internal voltage regulator is disabled. */
while ((AVR32_SCIF.vregcr & 0x20)) {
}
#endif
} /* End of power_save_measures_init() */
/**
* \brief Detects extern OSC frequency and initialize system clocks on it
*/
void sysclk_auto_init(void)
{
int mul;
// Switch to OSC ISP
// Set max startup time to make sure any crystal will be supported
// We cannot use a TC to measure this OSC frequency
// because the master clock must be faster than the clock selected by the TC
// Configure OSC0 in crystal mode, external crystal
// with a fcrystal Hz frequency.
scif_configure_osc_crystalmode(SCIF_OSC0, 12000000);
// Enable the OSC0
scif_enable_osc(SCIF_OSC0, AVR32_SCIF_OSCCTRL0_STARTUP_16384_RCOSC,
true);
flashcdw_set_flash_waitstate_and_readmode(12000000);
pm_set_mclk_source(PM_CLK_SRC_OSC0);
// Initialize the AST with the internal RC oscillator
// AST will count at the frequency of 115KHz/2
if (!ast_init_counter(&AVR32_AST, AST_OSC_RC, 0, 0)) {
while (1);
}
// Enable the AST
ast_enable(&AVR32_AST);
// Detect the frequency
switch (freq_detect_start()) {
case 8000000:
mul = 5;
break;
case 16000000:
mul = 2;
break;
case 12000000:
default:
mul = 3;
break;
}
scif_pll_opt_t opt;
// Set PLL0 VCO @ 96 MHz
// Set PLL0 @ 48 MHz
opt.osc = SCIF_OSC0;
opt.lockcount = 63;
opt.div = 0;
opt.mul = mul;
opt.pll_div2 = 1;
opt.pll_wbwdisable = 0;
opt.pll_freq = 1;
// lockcount in main clock for the PLL wait lock
scif_pll_setup(SCIF_PLL0, &opt);
/* Enable PLL0 */
scif_pll_enable(SCIF_PLL0);
/* Wait for PLL0 locked */
scif_wait_for_pll_locked(SCIF_PLL0);
// Use 1 flash wait state
flashcdw_set_wait_state(1);
// Switch the main clock to PLL0
pm_set_mclk_source(PM_CLK_SRC_PLL0);
// fCPU: 48 MHz // USBC request a CPU clock >25MHz
// fHSB: 48 MHz
// fPBA: 48 MHz
// fPBB: 48 MHz
pm_disable_clk_domain_div(PM_CLK_DOMAIN_0); // CPU
pm_disable_clk_domain_div(PM_CLK_DOMAIN_1); // HSB
pm_disable_clk_domain_div(PM_CLK_DOMAIN_2); // PBA
pm_disable_clk_domain_div(PM_CLK_DOMAIN_3); // PBB
// Use 0 flash wait state
flashcdw_set_wait_state(1);
}
