static void x86_cpu_decode_thread(int core, int thread)
{
struct list_t *fetchq = X86_THREAD.fetch_queue;
struct list_t *uopq = X86_THREAD.uop_queue;
struct x86_uop_t *uop;
int i;
for (i = 0; i < x86_cpu_decode_width; i++)
{
/* Empty fetch queue, full uop_queue */
if (!list_count(fetchq))
break;
if (list_count(uopq) >= x86_uop_queue_size)
break;
uop = list_get(fetchq, 0);
assert(x86_uop_exists(uop));
/* If instructions come from the trace cache, i.e., are located in
* the trace cache queue, copy all of them
* into the uop queue in one single decode slot. */
if (uop->trace_cache)
{
do {
x86_fetch_queue_remove(core, thread, 0);
list_add(uopq, uop);
uop->in_uop_queue = 1;
uop = list_get(fetchq, 0);
} while (uop && uop->trace_cache);
break;
}
/* Decode one macro-instruction coming from a block in the instruction
* cache. If the cache access finished, extract it from the fetch queue. */
assert(!uop->mop_index);
if (!mod_in_flight_access(X86_THREAD.inst_mod, uop->fetch_access, uop->fetch_address))
{
do {
/* Move from fetch queue to uop queue */
x86_fetch_queue_remove(core, thread, 0);
list_add(uopq, uop);
uop->in_uop_queue = 1;
/* Trace */
x86_trace("x86.inst id=%lld core=%d stg=\"dec\"\n",
uop->id_in_core, uop->core);
/* Next */
uop = list_get(fetchq, 0);
} while (uop && uop->mop_index);
}
}
}
static void decode_thread(int core, int thread)
{
struct list_t *fetchq = THREAD.fetchq;
struct list_t *uopq = THREAD.uopq;
struct uop_t *uop;
int i;
for (i = 0; i < cpu_decode_width; i++)
{
/* Empty fetch queue, full uopq */
if (!list_count(fetchq))
break;
if (list_count(uopq) >= uopq_size)
break;
uop = list_get(fetchq, 0);
assert(uop_exists(uop));
/* If instructions come from the trace cache, i.e., are located in
* the trace cache queue, copy all of them
* into the uop queue in one single decode slot. */
if (uop->fetch_trace_cache) {
do {
fetchq_remove(core, thread, 0);
list_add(uopq, uop);
uop->in_uopq = 1;
uop = list_get(fetchq, 0);
} while (uop && uop->fetch_trace_cache);
break;
}
/* Decode one macro-instruction coming from a block in the instruction
* cache. If the cache access finished, extract it from the fetch queue. */
assert(!uop->mop_index);
if (!mod_in_flight_access(THREAD.inst_mod, uop->fetch_access, uop->fetch_address))
{
do {
fetchq_remove(core, thread, 0);
list_add(uopq, uop);
uop->in_uopq = 1;
uop = list_get(fetchq, 0);
} while (uop && uop->mop_index);
}
}
}
