int ddr_init( void )
{
// tell dramc to configure
set_val( P1MEMCCMD, 0x4 );
// set refresh period
set_val( P1REFRESH, nstoclk(7800) );
// set timing para
set_val( P1CASLAT, ( 3 << 1 ) );
set_val( P1T_DQSS, 0x1 ); // 0.75 - 1.25
set_val( P1T_MRD, 0x2 );
set_val( P1T_RAS, nstoclk(45) );
set_val( P1T_RC, nstoclk(68) );
unsigned int trcd = nstoclk( 23 );
set_val( P1T_RCD, trcd | (( trcd - 3 ) << 3 ) );
unsigned int trfc = nstoclk( 80 );
set_val( P1T_RFC, trfc | ( ( trfc-3 ) << 5 ) );
unsigned int trp = nstoclk( 23 );
set_val( P1T_RP, trp | ( ( trp - 3 ) << 3 ) );
set_val( P1T_RRD, nstoclk(15) );
set_val( P1T_WR, nstoclk(15) );
set_val( P1T_WTR, 0x7 );
set_val( P1T_XP, 0x2 );
set_val( P1T_XSR, nstoclk(120) );
set_val( P1T_ESR, nstoclk(120) );
// set mem cfg
set_nbit( P1MEMCFG, 0, 3, 0x2 ); /* 10 column address */
/* set_nbit: 把从第bit位开始的一共len位消零，然后把这几位设为val */
set_nbit( P1MEMCFG, 3, 3, 0x3 ); /* 14 row address */
set_zero( P1MEMCFG, 6 ); /* A10/AP */
set_nbit( P1MEMCFG, 15, 3, 0x2 ); /* Burst 4 */
set_nbit( P1MEMCFG2, 0, 4, 0x5 );
set_2bit( P1MEMCFG2, 6, 0x1 ); /* 32 bit */
set_nbit( P1MEMCFG2, 8, 3, 0x3 ); /* Mobile DDR SDRAM */
set_2bit( P1MEMCFG2, 11, 0x1 );
set_one( P1_chip_0_cfg, 16 ); /* Bank-Row-Column organization */
// memory init
set_val( P1DIRECTCMD, 0xc0000 ); // NOP
set_val( P1DIRECTCMD, 0x000 ); // precharge
set_val( P1DIRECTCMD, 0x40000 );// auto refresh
set_val( P1DIRECTCMD, 0x40000 );// auto refresh
set_val( P1DIRECTCMD, 0xa0000 ); // EMRS
set_val( P1DIRECTCMD, 0x80032 ); // MRS
set_val( MEM_SYS_CFG, 0x0 );
// set dramc to "go" status
set_val( P1MEMCCMD, 0x000 );
// wait ready
while( !(( read_val( P1MEMSTAT ) & 0x3 ) == 0x1));
}
void ddr_init(void)
{
/*makes DRAM enter "config" state*/
P1MEMCCMD = 0x04;
/*set memory timing parameter, chip config ,
id config register,etc...
*/
P1REFRESH = nstoclk(7800); //7.8us
P1CASLAT = (3 << 1);
P1T_DQSS = 0X1;
P1T_MRD = 0X2;
P1T_RAS = nstoclk(45);
P1T_RC = nstoclk(68);
P1T_RCD = nstoclk(23);//| ((nstoclk(23)-3) << 3);
P1T_RFC = nstoclk(80);//| ((nstoclk(80)-3) << 5);
P1T_RP = nstoclk(23);//| ((nstoclk(23)-3) << 3);
P1T_RRD = nstoclk(15);
P1T_WR = nstoclk(15);
P1T_WTR = 0X7;
P1T_XP = 0X2;
P1T_XSR = nstoclk(120);
P1T_ESR = nstoclk(120);
/*mem config*/
P1MEMCFG &= ~(0x3f);
P1MEMCFG |= 0x2; //10 columns
P1MEMCFG |= (1 << 4); //13 rows , 256M
P1MEMCFG &= ~(0x7 << 15);
P1MEMCFG |= (1 << 16); //burst 4
P1MEMCFG2 |= 0x5;
P1MEMCFG2 &= ~(0x3 << 6);
P1MEMCFG2 |= (1 << 6); //32bit
P1MEMCFG2 &= ~(0x7 << 8);
P1MEMCFG2 |= (0x3 << 8);
P1MEMCFG2 &= ~(0x3 << 11);
P1MEMCFG2 |= (1 << 11);
p1_chip_0_cfg |= 1 << 16;
P1DIRECTCMD = 0xc0000; //nop
P1DIRECTCMD = 0x000; //prechargeAII
P1DIRECTCMD = 0x40000; //autorefresh
P1DIRECTCMD = 0x40000;
P1DIRECTCMD = 0xa0000; //MRS
P1DIRECTCMD = 0x80032; //EMRS
MEM_SYS_CFG = 0X0;
/*set DRAM to "ready" state*/
P1MEMCCMD = 0x000;
/*wait for "ready" state*/
while ((P1MEMSTAT & 0X3) != 0X1);
}
