// get random seed from wideband noise rssi
void radio_init () {
hal_disableIRQs();
// manually reset radio
#ifdef CFG_sx1276_radio
hal_pin_rst(0); // drive RST pin low
#else
hal_pin_rst(1); // drive RST pin high
#endif
hal_waitUntil(os_getTime()+ms2osticks(1)); // wait >100us
hal_pin_rst(2); // configure RST pin floating!
hal_waitUntil(os_getTime()+ms2osticks(5)); // wait 5ms
opmode(OPMODE_SLEEP);
// some sanity checks, e.g., read version number
u1_t v = readReg(RegVersion);
#ifdef CFG_sx1276_radio
ASSERT(v == 0x12 );
#elif CFG_sx1272_radio
ASSERT(v == 0x22);
#else
#error Missing CFG_sx1272_radio/CFG_sx1276_radio
#endif
// seed 15-byte randomness via noise rssi
rxlora(RXMODE_RSSI);
while( (readReg(RegOpMode) & OPMODE_MASK) != OPMODE_RX ); // continuous rx
for(int i=1; i<16; i++) {
for(int j=0; j<8; j++) {
u1_t b; // wait for two non-identical subsequent least-significant bits
while( (b = readReg(LORARegRssiWideband) & 0x01) == (readReg(LORARegRssiWideband) & 0x01) );
randbuf[i] = (randbuf[i] << 1) | b;
}
}
randbuf[0] = 16; // set initial index
#ifdef CFG_sx1276mb1_board
// chain calibration
writeReg(RegPaConfig, 0);
// Launch Rx chain calibration for LF band
writeReg(FSKRegImageCal, (readReg(FSKRegImageCal) & RF_IMAGECAL_IMAGECAL_MASK)|RF_IMAGECAL_IMAGECAL_START);
while((readReg(FSKRegImageCal)&RF_IMAGECAL_IMAGECAL_RUNNING) == RF_IMAGECAL_IMAGECAL_RUNNING){ ; }
// Sets a Frequency in HF band
u4_t frf = 868000000;
writeReg(RegFrfMsb, (u1_t)(frf>>16));
writeReg(RegFrfMid, (u1_t)(frf>> 8));
writeReg(RegFrfLsb, (u1_t)(frf>> 0));
// Launch Rx chain calibration for HF band
writeReg(FSKRegImageCal, (readReg(FSKRegImageCal) & RF_IMAGECAL_IMAGECAL_MASK)|RF_IMAGECAL_IMAGECAL_START);
while((readReg(FSKRegImageCal) & RF_IMAGECAL_IMAGECAL_RUNNING) == RF_IMAGECAL_IMAGECAL_RUNNING) { ; }
#endif /* CFG_sx1276mb1_board */
opmode(OPMODE_SLEEP);
hal_enableIRQs();
}
static void rxfsk (u1_t rxmode) {
// only single rx (no continuous scanning, no noise sampling)
ASSERT( rxmode == RXMODE_SINGLE );
// select FSK modem (from sleep mode)
//writeReg(RegOpMode, 0x00); // (not LoRa)
opmodeFSK();
ASSERT((readReg(RegOpMode) & OPMODE_LORA) == 0);
// enter standby mode (warm up))
opmode(OPMODE_STANDBY);
// configure frequency
configChannel();
// set LNA gain
//writeReg(RegLna, 0x20|0x03); // max gain, boost enable
writeReg(RegLna, LNA_RX_GAIN);
// configure receiver
writeReg(FSKRegRxConfig, 0x1E); // AFC auto, AGC, trigger on preamble?!?
// set receiver bandwidth
writeReg(FSKRegRxBw, 0x0B); // 50kHz SSb
// set AFC bandwidth
writeReg(FSKRegAfcBw, 0x12); // 83.3kHz SSB
// set preamble detection
writeReg(FSKRegPreambleDetect, 0xAA); // enable, 2 bytes, 10 chip errors
// set sync config
writeReg(FSKRegSyncConfig, 0x12); // no auto restart, preamble 0xAA, enable, fill FIFO, 3 bytes sync
// set packet config
writeReg(FSKRegPacketConfig1, 0xD8); // var-length, whitening, crc, no auto-clear, no adr filter
writeReg(FSKRegPacketConfig2, 0x40); // packet mode
// set sync value
writeReg(FSKRegSyncValue1, 0xC1);
writeReg(FSKRegSyncValue2, 0x94);
writeReg(FSKRegSyncValue3, 0xC1);
// set preamble timeout
writeReg(FSKRegRxTimeout2, 0xFF);//(LMIC.rxsyms+1)/2);
// set bitrate
writeReg(FSKRegBitrateMsb, 0x02); // 50kbps
writeReg(FSKRegBitrateLsb, 0x80);
// set frequency deviation
writeReg(FSKRegFdevMsb, 0x01); // +/- 25kHz
writeReg(FSKRegFdevLsb, 0x99);
// configure DIO mapping DIO0=PayloadReady DIO1=NOP DIO2=TimeOut
writeReg(RegDioMapping1, MAP_DIO0_FSK_READY|MAP_DIO1_FSK_NOP|MAP_DIO2_FSK_TIMEOUT);
// enable antenna switch for RX
hal_pin_rxtx(0);
// now instruct the radio to receive
hal_waitUntil(LMIC.rxtime); // busy wait until exact rx time
opmode(OPMODE_RX); // no single rx mode available in FSK
}
void os_radio (u1_t mode) {
hal_disableIRQs();
switch (mode) {
case RADIO_RST:
// put radio to sleep
opmode(OPMODE_SLEEP);
break;
case RADIO_TX:
// transmit frame now
starttx(); // buf=LMIC.frame, len=LMIC.dataLen
break;
case RADIO_RX:
// receive frame now (exactly at rxtime)
startrx(RXMODE_SINGLE); // buf=LMIC.frame, time=LMIC.rxtime, timeout=LMIC.rxsyms
break;
case RADIO_RXON:
// start scanning for beacon now
startrx(RXMODE_SCAN); // buf=LMIC.frame
break;
}
hal_enableIRQs();
}
// start LoRa receiver (time=LMIC.rxtime, timeout=LMIC.rxsyms, result=LMIC.frame[LMIC.dataLen])
static void rxlora (u1_t rxmode) {
// select LoRa modem (from sleep mode)
opmodeLora();
ASSERT((readReg(RegOpMode) & OPMODE_LORA) != 0);
// enter standby mode (warm up))
opmode(OPMODE_STANDBY);
// don't use MAC settings at startup
if(rxmode == RXMODE_RSSI) { // use fixed settings for rssi scan
writeReg(LORARegModemConfig1, RXLORA_RXMODE_RSSI_REG_MODEM_CONFIG1);
writeReg(LORARegModemConfig2, RXLORA_RXMODE_RSSI_REG_MODEM_CONFIG2);
} else { // single or continuous rx mode
// configure LoRa modem (cfg1, cfg2)
configLoraModem();
// configure frequency
configChannel();
}
// set LNA gain
writeReg(RegLna, LNA_RX_GAIN);
// set max payload size
writeReg(LORARegPayloadMaxLength, 64);
// use inverted I/Q signal (prevent mote-to-mote communication)
writeReg(LORARegInvertIQ, readReg(LORARegInvertIQ)|(1<<6));
// set symbol timeout (for single rx)
writeReg(LORARegSymbTimeoutLsb, LMIC.rxsyms);
// set sync word
writeReg(LORARegSyncWord, LORA_MAC_PREAMBLE);
// configure DIO mapping DIO0=RxDone DIO1=RxTout DIO2=NOP
writeReg(RegDioMapping1, MAP_DIO0_LORA_RXDONE|MAP_DIO1_LORA_RXTOUT|MAP_DIO2_LORA_NOP);
// clear all radio IRQ flags
writeReg(LORARegIrqFlags, 0xFF);
// enable required radio IRQs
writeReg(LORARegIrqFlagsMask, ~rxlorairqmask[rxmode]);
// enable antenna switch for RX
hal_pin_rxtx(0);
// now instruct the radio to receive
if (rxmode == RXMODE_SINGLE) { // single rx
hal_waitUntil(LMIC.rxtime); // busy wait until exact rx time
opmode(OPMODE_RX_SINGLE);
} else { // continous rx (scan or rssi)
opmode(OPMODE_RX);
}
}
static void txfsk () {
// select FSK modem (from sleep mode)
writeReg(RegOpMode, 0x10); // FSK, BT=0.5
ASSERT(readReg(RegOpMode) == 0x10);
// enter standby mode (required for FIFO loading))
opmode(OPMODE_STANDBY);
// set bitrate
writeReg(FSKRegBitrateMsb, 0x02); // 50kbps
writeReg(FSKRegBitrateLsb, 0x80);
// set frequency deviation
writeReg(FSKRegFdevMsb, 0x01); // +/- 25kHz
writeReg(FSKRegFdevLsb, 0x99);
// frame and packet handler settings
writeReg(FSKRegPreambleMsb, 0x00);
writeReg(FSKRegPreambleLsb, 0x05);
writeReg(FSKRegSyncConfig, 0x12);
writeReg(FSKRegPacketConfig1, 0xD0);
writeReg(FSKRegPacketConfig2, 0x40);
writeReg(FSKRegSyncValue1, 0xC1);
writeReg(FSKRegSyncValue2, 0x94);
writeReg(FSKRegSyncValue3, 0xC1);
// configure frequency
configChannel();
// configure output power
configPower();
// set the IRQ mapping DIO0=PacketSent DIO1=NOP DIO2=NOP
writeReg(RegDioMapping1, MAP_DIO0_FSK_READY|MAP_DIO1_FSK_NOP|MAP_DIO2_FSK_TXNOP);
// initialize the payload size and address pointers
writeReg(FSKRegPayloadLength, LMIC.dataLen+1); // (insert length byte into payload))
// download length byte and buffer to the radio FIFO
writeReg(RegFifo, LMIC.dataLen);
writeBuf(RegFifo, LMIC.frame, LMIC.dataLen);
// enable antenna switch for TX
hal_pin_rxtx(1);
// now we actually start the transmission
opmode(OPMODE_TX);
}
static void txlora () {
// select LoRa modem (from sleep mode)
//writeReg(RegOpMode, OPMODE_LORA);
opmodeLora();
ASSERT((readReg(RegOpMode) & OPMODE_LORA) != 0);
// enter standby mode (required for FIFO loading))
opmode(OPMODE_STANDBY);
// configure LoRa modem (cfg1, cfg2)
configLoraModem();
// configure frequency
configChannel();
// configure output power
writeReg(RegPaRamp, (readReg(RegPaRamp) & 0xF0) | 0x08); // set PA ramp-up time 50 uSec
configPower();
// set sync word
writeReg(LORARegSyncWord, LORA_MAC_PREAMBLE);
// set the IRQ mapping DIO0=TxDone DIO1=NOP DIO2=NOP
writeReg(RegDioMapping1, MAP_DIO0_LORA_TXDONE|MAP_DIO1_LORA_NOP|MAP_DIO2_LORA_NOP);
// clear all radio IRQ flags
writeReg(LORARegIrqFlags, 0xFF);
// mask all IRQs but TxDone
writeReg(LORARegIrqFlagsMask, ~IRQ_LORA_TXDONE_MASK);
// initialize the payload size and address pointers
writeReg(LORARegFifoTxBaseAddr, 0x00);
writeReg(LORARegFifoAddrPtr, 0x00);
writeReg(LORARegPayloadLength, LMIC.dataLen);
// download buffer to the radio FIFO
writeBuf(RegFifo, LMIC.frame, LMIC.dataLen);
// enable antenna switch for TX
hal_pin_rxtx(1);
// now we actually start the transmission
opmode(OPMODE_TX);
}
"FORLOOP",
"FORPREP",
"TFORLOOP",
"SETLIST",
"CLOSE",
"CLOSURE",
"VARARG",
NULL
};
#define opmode(t,a,b,c,m) (((t)<<7) | ((a)<<6) | ((b)<<4) | ((c)<<2) | (m))
const lu_byte luaP_opmodes[NUM_OPCODES] = {
/* T A B C mode opcode */
opmode(0, 1, OpArgR, OpArgN, iABC) /* OP_MOVE */
, opmode(0, 1, OpArgK, OpArgN, iABx) /* OP_LOADK */
, opmode(0, 1, OpArgU, OpArgU, iABC) /* OP_LOADBOOL */
, opmode(0, 1, OpArgR, OpArgN, iABC) /* OP_LOADNIL */
, opmode(0, 1, OpArgU, OpArgN, iABC) /* OP_GETUPVAL */
, opmode(0, 1, OpArgK, OpArgN, iABx) /* OP_GETGLOBAL */
, opmode(0, 1, OpArgR, OpArgK, iABC) /* OP_GETTABLE */
, opmode(0, 0, OpArgK, OpArgN, iABx) /* OP_SETGLOBAL */
, opmode(0, 0, OpArgU, OpArgN, iABC) /* OP_SETUPVAL */
, opmode(0, 0, OpArgK, OpArgK, iABC) /* OP_SETTABLE */
, opmode(0, 1, OpArgU, OpArgU, iABC) /* OP_NEWTABLE */
, opmode(0, 1, OpArgR, OpArgK, iABC) /* OP_SELF */
, opmode(0, 1, OpArgK, OpArgK, iABC) /* OP_ADD */
, opmode(0, 1, OpArgK, OpArgK, iABC) /* OP_SUB */
, opmode(0, 1, OpArgK, OpArgK, iABC) /* OP_MUL */
, opmode(0, 1, OpArgK, OpArgK, iABC) /* OP_DIV */
// called by hal ext IRQ handler
// (radio goes to stanby mode after tx/rx operations)
void radio_irq_handler (u1_t dio) {
ostime_t now = os_getTime();
if( (readReg(RegOpMode) & OPMODE_LORA) != 0) { // LORA modem
u1_t flags = readReg(LORARegIrqFlags);
if( flags & IRQ_LORA_TXDONE_MASK ) {
// save exact tx time
LMIC.txend = now - us2osticks(43); // TXDONE FIXUP
} else if( flags & IRQ_LORA_RXDONE_MASK ) {
// save exact rx time
if(getBw(LMIC.rps) == BW125) {
now -= LORA_RXDONE_FIXUP[getSf(LMIC.rps)];
}
LMIC.rxtime = now;
// read the PDU and inform the MAC that we received something
LMIC.dataLen = (readReg(LORARegModemConfig1) & SX1272_MC1_IMPLICIT_HEADER_MODE_ON) ?
readReg(LORARegPayloadLength) : readReg(LORARegRxNbBytes);
// set FIFO read address pointer
writeReg(LORARegFifoAddrPtr, readReg(LORARegFifoRxCurrentAddr));
// now read the FIFO
readBuf(RegFifo, LMIC.frame, LMIC.dataLen);
// read rx quality parameters
LMIC.snr = readReg(LORARegPktSnrValue); // SNR [dB] * 4
LMIC.rssi = readReg(LORARegPktRssiValue) - 125 + 64; // RSSI [dBm] (-196...+63)
} else if( flags & IRQ_LORA_RXTOUT_MASK ) {
// indicate timeout
LMIC.dataLen = 0;
}
// mask all radio IRQs
writeReg(LORARegIrqFlagsMask, 0xFF);
// clear radio IRQ flags
writeReg(LORARegIrqFlags, 0xFF);
} else { // FSK modem
u1_t flags1 = readReg(FSKRegIrqFlags1);
u1_t flags2 = readReg(FSKRegIrqFlags2);
if( flags2 & IRQ_FSK2_PACKETSENT_MASK ) {
// save exact tx time
LMIC.txend = now;
} else if( flags2 & IRQ_FSK2_PAYLOADREADY_MASK ) {
// save exact rx time
LMIC.rxtime = now;
// read the PDU and inform the MAC that we received something
LMIC.dataLen = readReg(FSKRegPayloadLength);
// now read the FIFO
readBuf(RegFifo, LMIC.frame, LMIC.dataLen);
// read rx quality parameters
LMIC.snr = 0; // determine snr
LMIC.rssi = 0; // determine rssi
} else if( flags1 & IRQ_FSK1_TIMEOUT_MASK ) {
// indicate timeout
LMIC.dataLen = 0;
} else {
//while(1);
// Do not infinite loop when interrupt triggers unexpectedly
// Instead, call ASSERT, which calls hal_failed, so there is at least a
// traceable error. (MK)
ASSERT(0);
}
}
// go from stanby to sleep
opmode(OPMODE_SLEEP);
// run os job (use preset func ptr)
os_setCallback(&LMIC.osjob, LMIC.osjob.func);
}
"SETLIST",
"SETLISTO",
"CLOSE",
"CLOSURE"
};
#endif
#define opmode(t,b,bk,ck,sa,k,m) (((t)<<OpModeT) | \
((b)<<OpModeBreg) | ((bk)<<OpModeBrk) | ((ck)<<OpModeCrk) | \
((sa)<<OpModesetA) | ((k)<<OpModeK) | (m))
const lu_byte luaP_opmodes[NUM_OPCODES] = {
/* T B Bk Ck sA K mode opcode */
opmode(0, 1, 0, 0, 1, 0, iABC) /* OP_MOVE */
,opmode(0, 0, 0, 0, 1, 1, iABx) /* OP_LOADK */
,opmode(0, 0, 0, 0, 1, 0, iABC) /* OP_LOADBOOL */
,opmode(0, 1, 0, 0, 1, 0, iABC) /* OP_LOADNIL */
,opmode(0, 0, 0, 0, 1, 0, iABC) /* OP_GETUPVAL */
,opmode(0, 0, 0, 0, 1, 1, iABx) /* OP_GETGLOBAL */
,opmode(0, 1, 0, 1, 1, 0, iABC) /* OP_GETTABLE */
,opmode(0, 0, 0, 0, 0, 1, iABx) /* OP_SETGLOBAL */
,opmode(0, 0, 0, 0, 0, 0, iABC) /* OP_SETUPVAL */
,opmode(0, 0, 1, 1, 0, 0, iABC) /* OP_SETTABLE */
,opmode(0, 0, 0, 0, 1, 0, iABC) /* OP_NEWTABLE */
,opmode(0, 1, 0, 1, 1, 0, iABC) /* OP_SELF */
,opmode(0, 0, 1, 1, 1, 0, iABC) /* OP_ADD */
,opmode(0, 0, 1, 1, 1, 0, iABC) /* OP_SUB */
,opmode(0, 0, 1, 1, 1, 0, iABC) /* OP_MUL */
,opmode(0, 0, 1, 1, 1, 0, iABC) /* OP_DIV */
"EQ_II", /* A B C if ((RK(B) == RK(C)) ~= A) then pc++ */
"EQ_FF", /* A B C if ((RK(B) == RK(C)) ~= A) then pc++ */
"LT_II", /* A B C if ((RK(B) < RK(C)) ~= A) then pc++ */
"LT_FF", /* A B C if ((RK(B) < RK(C)) ~= A) then pc++ */
"LE_II", /* A B C if ((RK(B) <= RK(C)) ~= A) then pc++ */
"LE_FF", /* A B C if ((RK(B) <= RK(C)) ~= A) then pc++ */
NULL
};
#define opmode(t,a,b,c,m) (((t)<<7) | ((a)<<6) | ((b)<<4) | ((c)<<2) | (m))
LUAI_DDEF const lu_byte luaP_opmodes[NUM_OPCODES] = {
/* T A B C mode opcode */
opmode(0, 1, OpArgR, OpArgN, iABC) /* OP_MOVE */
,opmode(0, 1, OpArgK, OpArgN, iABx) /* OP_LOADK */
,opmode(0, 1, OpArgN, OpArgN, iABx) /* OP_LOADKX */
,opmode(0, 1, OpArgU, OpArgU, iABC) /* OP_LOADBOOL */
,opmode(0, 1, OpArgU, OpArgN, iABC) /* OP_LOADNIL */
,opmode(0, 1, OpArgU, OpArgN, iABC) /* OP_GETUPVAL */
,opmode(0, 1, OpArgU, OpArgK, iABC) /* OP_GETTABUP */
,opmode(0, 1, OpArgR, OpArgK, iABC) /* OP_GETTABLE */
,opmode(0, 0, OpArgK, OpArgK, iABC) /* OP_SETTABUP */
,opmode(0, 0, OpArgU, OpArgN, iABC) /* OP_SETUPVAL */
,opmode(0, 0, OpArgK, OpArgK, iABC) /* OP_SETTABLE */
,opmode(0, 1, OpArgU, OpArgU, iABC) /* OP_NEWTABLE */
,opmode(0, 1, OpArgR, OpArgK, iABC) /* OP_SELF */
,opmode(0, 1, OpArgK, OpArgK, iABC) /* OP_ADD */
,opmode(0, 1, OpArgK, OpArgK, iABC) /* OP_SUB */
,opmode(0, 1, OpArgK, OpArgK, iABC) /* OP_MUL */
void Parameters::parse_options(int argc, char* argv[])
{
unsigned log_level = 2;
std::string log_file;
po::options_description general("General options");
auto general_add = general.add_options();
general_add("version,V", "print version string");
general_add("help,h", "produce help message");
general_add("log-level,l", po::value<unsigned>(&log_level),
"set the log level (default:2, all:0)");
general_add("log-file,L", po::value<std::string>(&log_file),
"name of target log file");
general_add("maximum-number,n", po::value<uint64_t>(&maximum_number),
"set the maximum number of microslices to process (default: "
"unlimited)");
po::options_description source("Source options");
auto source_add = source.add_options();
source_add("shm-channel,c", po::value<size_t>(&shm_channel),
"use given shared memory channel as data source");
source_add("input-shm,I", po::value<std::string>(&input_shm),
"name of a shared memory to use as data source");
source_add("input-archive,i", po::value<std::string>(&input_archive),
"name of an input file archive to read");
po::options_description opmode("Operation mode options");
auto opmode_add = opmode.add_options();
opmode_add("debugger,d", po::value<bool>(&debugger)->implicit_value(true),
"enable/disable debugger (raw message unpacking and printout)");
opmode_add("sorter,s", po::value<bool>(&sorter)->implicit_value(true),
"enable/disable sorting by epoch in epoch buffer for sink(s) (build output ms from epochs)");
opmode_add("ep_in_ms,N", po::value<uint32_t>(&epoch_per_ms),
"Number of epochs stored in each output MS in case sorter is used (default:1)");
opmode_add("sortmesg", po::value<bool>(&sortmesg)->implicit_value(true),
"enable/disable message sorting inside epoch buffer before creation of new ms");
po::options_description sink("Sink options");
auto sink_add = sink.add_options();
sink_add("dump_verbosity,v", po::value<size_t>(&dump_verbosity),
"set output debug dump verbosity");
sink_add("output-shm,O", po::value<std::string>(&output_shm),
"name of a shared memory to write to");
sink_add("output-archive,o", po::value<std::string>(&output_archive),
"name of an output file archive to write");
po::options_description desc;
desc.add(general).add(source).add(opmode).add(sink);
po::variables_map vm;
po::store(po::parse_command_line(argc, argv, desc), vm);
po::notify(vm);
if (vm.count("help") != 0u) {
std::cout << "ngdpbtool, git revision " << g_GIT_REVISION << std::endl;
std::cout << desc << std::endl;
exit(EXIT_SUCCESS);
}
if (vm.count("version") != 0u) {
std::cout << "ngdpbtool, git revision " << g_GIT_REVISION << std::endl;
exit(EXIT_SUCCESS);
}
logging::add_console(static_cast<severity_level>(log_level));
if (vm.count("log-file")) {
L_(info) << "Logging output to " << log_file;
logging::add_file(log_file, static_cast<severity_level>(log_level));
}
size_t input_sources = vm.count("input-archive") + vm.count("input-shm");
if (input_sources == 0) {
throw ParametersException("no input source specified");
}
if (input_sources > 1) {
throw ParametersException("more than one input source specified");
}
}
"FORPREP",
"TFORCALL",
"TFORLOOP",
"SETLIST",
"CLOSURE",
"VARARG",
"EXTRAARG",
NULL
};
#define opmode(t,a,b,c,m) (((t)<<7) | ((a)<<6) | ((b)<<4) | ((c)<<2) | (m))
LUAI_DDEF const NameDef(lu_byte) NameDef(luaP_opmodes)[NUM_OPCODES] = {
/* T A B C mode opcode */
opmode(0, 1, NameDef(OpArgR), NameDef(OpArgN), NameDef(iABC)) /* OP_MOVE */
,opmode(0, 1, NameDef(OpArgK), NameDef(OpArgN), NameDef(iABx)) /* OP_LOADK */
,opmode(0, 1, NameDef(OpArgN), NameDef(OpArgN), NameDef(iABx)) /* OP_LOADKX */
,opmode(0, 1, NameDef(OpArgU), NameDef(OpArgU), NameDef(iABC)) /* OP_LOADBOOL */
,opmode(0, 1, NameDef(OpArgU), NameDef(OpArgN), NameDef(iABC)) /* OP_LOADNIL */
,opmode(0, 1, NameDef(OpArgU), NameDef(OpArgN), NameDef(iABC)) /* OP_GETUPVAL */
,opmode(0, 1, NameDef(OpArgU), NameDef(OpArgK), NameDef(iABC)) /* OP_GETTABUP */
,opmode(0, 1, NameDef(OpArgR), NameDef(OpArgK), NameDef(iABC)) /* OP_GETTABLE */
,opmode(0, 0, NameDef(OpArgK), NameDef(OpArgK), NameDef(iABC)) /* OP_SETTABUP */
,opmode(0, 0, NameDef(OpArgU), NameDef(OpArgN), NameDef(iABC)) /* OP_SETUPVAL */
,opmode(0, 0, NameDef(OpArgK), NameDef(OpArgK), NameDef(iABC)) /* OP_SETTABLE */
,opmode(0, 1, NameDef(OpArgU), NameDef(OpArgU), NameDef(iABC)) /* OP_NEWTABLE */
,opmode(0, 1, NameDef(OpArgR), NameDef(OpArgK), NameDef(iABC)) /* OP_SELF */
,opmode(0, 1, NameDef(OpArgK), NameDef(OpArgK), NameDef(iABC)) /* OP_ADD */
,opmode(0, 1, NameDef(OpArgK), NameDef(OpArgK), NameDef(iABC)) /* OP_SUB */
,opmode(0, 1, NameDef(OpArgK), NameDef(OpArgK), NameDef(iABC)) /* OP_MUL */
"VT_CLONE",
"VT_IADD",
"VT_ISUB",
"VT_IMUL",
"VT_ISCALE",
"EXTRAARG",
NULL
};
#define opmode(t,a,b,c,m) (((t)<<7) | ((a)<<6) | ((b)<<4) | ((c)<<2) | (m))
LUAI_DDEF const lu_byte luaP_opmodes[NUM_OPCODES] = {
/* T A B C mode opcode */
opmode(0, 1, OpArgR, OpArgN, iABC) /* OP_MOVE */
,opmode(0, 1, OpArgK, OpArgN, iABx) /* OP_LOADK */
,opmode(0, 1, OpArgN, OpArgN, iABx) /* OP_LOADKX */
,opmode(0, 1, OpArgU, OpArgU, iABC) /* OP_LOADBOOL */
,opmode(0, 1, OpArgU, OpArgN, iABC) /* OP_LOADNIL */
,opmode(0, 1, OpArgU, OpArgN, iABC) /* OP_GETUPVAL */
,opmode(0, 1, OpArgU, OpArgK, iABC) /* OP_GETTABUP */
,opmode(0, 1, OpArgR, OpArgK, iABC) /* OP_GETTABLE */
,opmode(0, 0, OpArgK, OpArgK, iABC) /* OP_SETTABUP */
,opmode(0, 0, OpArgU, OpArgN, iABC) /* OP_SETUPVAL */
,opmode(0, 0, OpArgK, OpArgK, iABC) /* OP_SETTABLE */
,opmode(0, 1, OpArgU, OpArgU, iABC) /* OP_NEWTABLE */
,opmode(0, 1, OpArgR, OpArgK, iABC) /* OP_SELF */
,opmode(0, 1, OpArgK, OpArgK, iABC) /* OP_ADD */
,opmode(0, 1, OpArgK, OpArgK, iABC) /* OP_SUB */
,opmode(0, 1, OpArgK, OpArgK, iABC) /* OP_MUL */
#define opmode(t,a,b,c,m) (((t)<<7) | ((a)<<6) | ((b)<<4) | ((c)<<2) | (m))
LUAI_DDEF const lu_byte luaP_opmodes[NUM_OPCODES] = {
/* T A B C mode opcode */
//@POSEIDON_LUA: BEGIN
//============================================================================================
// opmode(0, 1, OpArgU, OpArgU, iABC) /* OP_LOAD_INT_1 */
// ,opmode(0, 1, OpArgU, OpArgU, iABC), /* OP_LOAD_INT_2 */
opmode(0, 1, OpArgU, OpArgU, iABC) /* OP_CS_MALLOC */
,opmode(0, 1, OpArgU, OpArgU, iABC) /* OP_CS_FREE */
,opmode(0, 1, OpArgU, OpArgU, iABC) /* OP_CS_LOAD_INT */
,opmode(0, 1, OpArgU, OpArgU, iABC) /* OP_CS_STORE_INT */
,opmode(0, 1, OpArgU, OpArgU, iABC) /* OP_CS_LOAD_DOUBLE */
,opmode(0, 1, OpArgU, OpArgU, iABC) /* OP_CS_STORE_DOUBLE */
,opmode(0, 1, OpArgU, OpArgU, iABC) /* OP_CS_LOAD_BOOL */
,opmode(0, 1, OpArgU, OpArgU, iABC) /* OP_CS_STORE_BOOL */
,opmode(0, 1, OpArgU, OpArgU, iABC) /* OP_CS_LOAD_POINTER */
,opmode(0, 1, OpArgU, OpArgU, iABC) /* OP_CS_STORE_POINTER */
,opmode(0, 1, OpArgU, OpArgU, iABC) /* OP_CS_LOAD_OFFSET */
,opmode(0, 1, OpArgU, OpArgU, iABC) /* OP_CS_LOAD_CHAR */
,opmode(0, 1, OpArgU, OpArgU, iABC) /* OP_CS_STORE_CHAR */
,opmode(0, 1, OpArgU, OpArgU, iABC) /* OP_CS_LOAD_STRING */
,opmode(0, 1, OpArgU, OpArgU, iABC), /* OP_CS_STORE_STRING */
