/*
* Initialize mips and configure to run kernel
*/
void
mips_proc0_init(void)
{
#ifdef SMP
if (platform_processor_id() != 0)
panic("BSP must be processor number 0");
#endif
proc_linkup0(&proc0, &thread0);
KASSERT((kstack0 & PAGE_MASK) == 0,
("kstack0 is not aligned on a page boundary: 0x%0lx",
(long)kstack0));
thread0.td_kstack = kstack0;
thread0.td_kstack_pages = KSTACK_PAGES;
/*
* Do not use cpu_thread_alloc to initialize these fields
* thread0 is the only thread that has kstack located in KSEG0
* while cpu_thread_alloc handles kstack allocated in KSEG2.
*/
thread0.td_pcb = (struct pcb *)(thread0.td_kstack +
thread0.td_kstack_pages * PAGE_SIZE) - 1;
thread0.td_frame = &thread0.td_pcb->pcb_regs;
/* Steal memory for the dynamic per-cpu area. */
dpcpu_init((void *)pmap_steal_memory(DPCPU_SIZE), 0);
PCPU_SET(curpcb, thread0.td_pcb);
/*
* There is no need to initialize md_upte array for thread0 as it's
* located in .bss section and should be explicitly zeroed during
* kernel initialization.
*/
}
static void
init_proc0(vm_offset_t kstack)
{
pcpup = &__pcpu[0];
proc_linkup0(&proc0, &thread0);
thread0.td_kstack = kstack;
thread0.td_pcb = (struct pcb *)(thread0.td_kstack) - 1;
thread0.td_frame = &proc0_tf;
pcpup->pc_curpcb = thread0.td_pcb;
}
static void
init_proc0(vm_offset_t kstack)
{
struct pcpu *pcpup = &__pcpu[0];
proc_linkup0(&proc0, &thread0);
thread0.td_kstack = kstack;
thread0.td_pcb = (struct pcb *)(thread0.td_kstack) - 1;
thread0.td_pcb->pcb_fpflags = 0;
thread0.td_pcb->pcb_vfpcpu = UINT_MAX;
thread0.td_frame = &proc0_tf;
pcpup->pc_curpcb = thread0.td_pcb;
}
void *
initarm(void *arg, void *arg2)
{
struct pcpu *pc;
struct pv_addr kernel_l1pt;
struct pv_addr md_addr;
struct pv_addr md_bla;
struct pv_addr dpcpu;
int loop;
u_int l1pagetable;
vm_offset_t freemempos;
vm_offset_t lastalloced;
vm_offset_t lastaddr;
uint32_t memsize = 32 * 1024 * 1024;
sa1110_uart_vaddr = SACOM1_VBASE;
boothowto = RB_VERBOSE | RB_SINGLE;
cninit();
set_cpufuncs();
lastaddr = fake_preload_metadata();
physmem = memsize / PAGE_SIZE;
pc = &__pcpu;
pcpu_init(pc, 0, sizeof(struct pcpu));
PCPU_SET(curthread, &thread0);
/* Do basic tuning, hz etc */
init_param1();
physical_start = (vm_offset_t) KERNBASE;
physical_end = lastaddr;
physical_freestart = (((vm_offset_t)physical_end) + PAGE_MASK) & ~PAGE_MASK;
md_addr.pv_va = md_addr.pv_pa = MDROOT_ADDR;
freemempos = (vm_offset_t)round_page(physical_freestart);
memset((void *)freemempos, 0, 256*1024);
/* Define a macro to simplify memory allocation */
#define valloc_pages(var, np) \
alloc_pages((var).pv_pa, (np)); \
(var).pv_va = (var).pv_pa;
#define alloc_pages(var, np) \
(var) = freemempos; \
freemempos += ((np) * PAGE_SIZE);\
memset((char *)(var), 0, ((np) * PAGE_SIZE));
while ((freemempos & (L1_TABLE_SIZE - 1)) != 0)
freemempos += PAGE_SIZE;
valloc_pages(kernel_l1pt, L1_TABLE_SIZE / PAGE_SIZE);
valloc_pages(md_bla, L2_TABLE_SIZE / PAGE_SIZE);
alloc_pages(sa1_cache_clean_addr, CPU_SA110_CACHE_CLEAN_SIZE / PAGE_SIZE);
for (loop = 0; loop < NUM_KERNEL_PTS; ++loop) {
if (!(loop % (PAGE_SIZE / L2_TABLE_SIZE_REAL))) {
valloc_pages(kernel_pt_table[loop],
L2_TABLE_SIZE / PAGE_SIZE);
} else {
kernel_pt_table[loop].pv_pa = freemempos +
(loop % (PAGE_SIZE / L2_TABLE_SIZE_REAL)) *
L2_TABLE_SIZE_REAL;
kernel_pt_table[loop].pv_va =
kernel_pt_table[loop].pv_pa;
}
}
/*
* Allocate a page for the system page mapped to V0x00000000
* This page will just contain the system vectors and can be
* shared by all processes.
*/
valloc_pages(systempage, 1);
/* Allocate dynamic per-cpu area. */
valloc_pages(dpcpu, DPCPU_SIZE / PAGE_SIZE);
dpcpu_init((void *)dpcpu.pv_va, 0);
/* Allocate stacks for all modes */
valloc_pages(irqstack, IRQ_STACK_SIZE);
valloc_pages(abtstack, ABT_STACK_SIZE);
valloc_pages(undstack, UND_STACK_SIZE);
valloc_pages(kernelstack, KSTACK_PAGES);
lastalloced = kernelstack.pv_va;
/*
* Allocate memory for the l1 and l2 page tables. The scheme to avoid
* wasting memory by allocating the l1pt on the first 16k memory was
* taken from NetBSD rpc_machdep.c. NKPT should be greater than 12 for
* this to work (which is supposed to be the case).
*/
/*
* Now we start construction of the L1 page table
* We start by mapping the L2 page tables into the L1.
* This means that we can replace L1 mappings later on if necessary
*/
l1pagetable = kernel_l1pt.pv_pa;
/* Map the L2 pages tables in the L1 page table */
pmap_link_l2pt(l1pagetable, 0x00000000,
&kernel_pt_table[KERNEL_PT_SYS]);
pmap_link_l2pt(l1pagetable, KERNBASE,
&kernel_pt_table[KERNEL_PT_KERNEL]);
pmap_link_l2pt(l1pagetable, 0xd0000000,
&kernel_pt_table[KERNEL_PT_IO]);
pmap_link_l2pt(l1pagetable, lastalloced & ~((L1_S_SIZE * 4) - 1),
&kernel_pt_table[KERNEL_PT_L1]);
pmap_link_l2pt(l1pagetable, 0x90000000, &kernel_pt_table[KERNEL_PT_IRQ]);
pmap_link_l2pt(l1pagetable, MDROOT_ADDR,
&md_bla);
for (loop = 0; loop < KERNEL_PT_VMDATA_NUM; ++loop)
pmap_link_l2pt(l1pagetable, KERNEL_VM_BASE + loop * 0x00100000,
&kernel_pt_table[KERNEL_PT_VMDATA + loop]);
pmap_map_chunk(l1pagetable, KERNBASE, KERNBASE,
((uint32_t)lastaddr - KERNBASE), VM_PROT_READ|VM_PROT_WRITE,
PTE_CACHE);
/* Map the DPCPU pages */
pmap_map_chunk(l1pagetable, dpcpu.pv_va, dpcpu.pv_pa, DPCPU_SIZE,
VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
/* Map the stack pages */
pmap_map_chunk(l1pagetable, irqstack.pv_va, irqstack.pv_pa,
IRQ_STACK_SIZE * PAGE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
pmap_map_chunk(l1pagetable, md_addr.pv_va, md_addr.pv_pa,
MD_ROOT_SIZE * 1024, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
pmap_map_chunk(l1pagetable, abtstack.pv_va, abtstack.pv_pa,
ABT_STACK_SIZE * PAGE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
pmap_map_chunk(l1pagetable, undstack.pv_va, undstack.pv_pa,
UND_STACK_SIZE * PAGE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
pmap_map_chunk(l1pagetable, kernelstack.pv_va, kernelstack.pv_pa,
KSTACK_PAGES * PAGE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
pmap_map_chunk(l1pagetable, kernel_l1pt.pv_va, kernel_l1pt.pv_pa,
L1_TABLE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_PAGETABLE);
for (loop = 0; loop < NUM_KERNEL_PTS; ++loop) {
pmap_map_chunk(l1pagetable, kernel_pt_table[loop].pv_va,
kernel_pt_table[loop].pv_pa, L2_TABLE_SIZE,
VM_PROT_READ|VM_PROT_WRITE, PTE_PAGETABLE);
}
pmap_map_chunk(l1pagetable, md_bla.pv_va, md_bla.pv_pa, L2_TABLE_SIZE,
VM_PROT_READ|VM_PROT_WRITE, PTE_PAGETABLE);
/* Map the vector page. */
pmap_map_entry(l1pagetable, vector_page, systempage.pv_pa,
VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
/* Map the statically mapped devices. */
pmap_devmap_bootstrap(l1pagetable, assabet_devmap);
pmap_map_chunk(l1pagetable, sa1_cache_clean_addr, 0xf0000000,
CPU_SA110_CACHE_CLEAN_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
data_abort_handler_address = (u_int)data_abort_handler;
prefetch_abort_handler_address = (u_int)prefetch_abort_handler;
undefined_handler_address = (u_int)undefinedinstruction_bounce;
undefined_init();
cpu_domains((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT);
setttb(kernel_l1pt.pv_pa);
cpu_tlb_flushID();
cpu_domains(DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2));
/*
* Pages were allocated during the secondary bootstrap for the
* stacks for different CPU modes.
* We must now set the r13 registers in the different CPU modes to
* point to these stacks.
* Since the ARM stacks use STMFD etc. we must set r13 to the top end
* of the stack memory.
*/
set_stackptr(PSR_IRQ32_MODE,
irqstack.pv_va + IRQ_STACK_SIZE * PAGE_SIZE);
set_stackptr(PSR_ABT32_MODE,
abtstack.pv_va + ABT_STACK_SIZE * PAGE_SIZE);
set_stackptr(PSR_UND32_MODE,
undstack.pv_va + UND_STACK_SIZE * PAGE_SIZE);
/*
* We must now clean the cache again....
* Cleaning may be done by reading new data to displace any
* dirty data in the cache. This will have happened in setttb()
* but since we are boot strapping the addresses used for the read
* may have just been remapped and thus the cache could be out
* of sync. A re-clean after the switch will cure this.
* After booting there are no gross relocations of the kernel thus
* this problem will not occur after initarm().
*/
cpu_idcache_wbinv_all();
bootverbose = 1;
/* Set stack for exception handlers */
proc_linkup0(&proc0, &thread0);
thread0.td_kstack = kernelstack.pv_va;
thread0.td_pcb = (struct pcb *)
(thread0.td_kstack + KSTACK_PAGES * PAGE_SIZE) - 1;
thread0.td_pcb->pcb_flags = 0;
thread0.td_frame = &proc0_tf;
/* Enable MMU, I-cache, D-cache, write buffer. */
cpufunc_control(0x337f, 0x107d);
arm_vector_init(ARM_VECTORS_LOW, ARM_VEC_ALL);
pmap_curmaxkvaddr = freemempos + KERNEL_PT_VMDATA_NUM * 0x400000;
dump_avail[0] = phys_avail[0] = round_page(virtual_avail);
dump_avail[1] = phys_avail[1] = 0xc0000000 + 0x02000000 - 1;
dump_avail[2] = phys_avail[2] = 0;
dump_avail[3] = phys_avail[3] = 0;
mutex_init();
pmap_bootstrap(freemempos, 0xd0000000, &kernel_l1pt);
init_param2(physmem);
kdb_init();
return ((void *)(kernelstack.pv_va + USPACE_SVC_STACK_TOP -
sizeof(struct pcb)));
}
void *
initarm(void *arg, void *arg2)
{
#define next_chunk2(a,b) (((a) + (b)) &~ ((b)-1))
#define next_page(a) next_chunk2(a,PAGE_SIZE)
struct pv_addr kernel_l1pt;
struct pv_addr dpcpu;
int loop, i;
u_int l1pagetable;
vm_offset_t freemempos;
vm_offset_t freemem_pt;
vm_offset_t afterkern;
vm_offset_t freemem_after;
vm_offset_t lastaddr;
uint32_t memsize;
set_cpufuncs(); /* NB: sets cputype */
lastaddr = fake_preload_metadata();
pcpu_init(pcpup, 0, sizeof(struct pcpu));
PCPU_SET(curthread, &thread0);
/* Do basic tuning, hz etc */
init_param1();
/*
* We allocate memory downwards from where we were loaded
* by RedBoot; first the L1 page table, then NUM_KERNEL_PTS
* entries in the L2 page table. Past that we re-align the
* allocation boundary so later data structures (stacks, etc)
* can be mapped with different attributes (write-back vs
* write-through). Note this leaves a gap for expansion
* (or might be repurposed).
*/
freemempos = KERNPHYSADDR;
/* macros to simplify initial memory allocation */
#define alloc_pages(var, np) do { \
freemempos -= (np * PAGE_SIZE); \
(var) = freemempos; \
/* NB: this works because locore maps PA=VA */ \
memset((char *)(var), 0, ((np) * PAGE_SIZE)); \
} while (0)
#define valloc_pages(var, np) do { \
alloc_pages((var).pv_pa, (np)); \
(var).pv_va = (var).pv_pa + (KERNVIRTADDR - KERNPHYSADDR); \
} while (0)
/* force L1 page table alignment */
while (((freemempos - L1_TABLE_SIZE) & (L1_TABLE_SIZE - 1)) != 0)
freemempos -= PAGE_SIZE;
/* allocate contiguous L1 page table */
valloc_pages(kernel_l1pt, L1_TABLE_SIZE / PAGE_SIZE);
/* now allocate L2 page tables; they are linked to L1 below */
for (loop = 0; loop < NUM_KERNEL_PTS; ++loop) {
if (!(loop % (PAGE_SIZE / L2_TABLE_SIZE_REAL))) {
valloc_pages(kernel_pt_table[loop],
L2_TABLE_SIZE / PAGE_SIZE);
} else {
kernel_pt_table[loop].pv_pa = freemempos +
(loop % (PAGE_SIZE / L2_TABLE_SIZE_REAL)) *
L2_TABLE_SIZE_REAL;
kernel_pt_table[loop].pv_va =
kernel_pt_table[loop].pv_pa +
(KERNVIRTADDR - KERNPHYSADDR);
}
}
freemem_pt = freemempos; /* base of allocated pt's */
/*
* Re-align allocation boundary so we can map the area
* write-back instead of write-through for the stacks and
* related structures allocated below.
*/
freemempos = PHYSADDR + 0x100000;
/*
* Allocate a page for the system page mapped to V0x00000000
* This page will just contain the system vectors and can be
* shared by all processes.
*/
valloc_pages(systempage, 1);
/* Allocate dynamic per-cpu area. */
valloc_pages(dpcpu, DPCPU_SIZE / PAGE_SIZE);
dpcpu_init((void *)dpcpu.pv_va, 0);
/* Allocate stacks for all modes */
valloc_pages(irqstack, IRQ_STACK_SIZE);
valloc_pages(abtstack, ABT_STACK_SIZE);
valloc_pages(undstack, UND_STACK_SIZE);
valloc_pages(kernelstack, KSTACK_PAGES);
alloc_pages(minidataclean.pv_pa, 1);
valloc_pages(msgbufpv, round_page(msgbufsize) / PAGE_SIZE);
#ifdef ARM_USE_SMALL_ALLOC
freemempos -= PAGE_SIZE;
freemem_pt = trunc_page(freemem_pt);
freemem_after = freemempos - ((freemem_pt - (PHYSADDR + 0x100000)) /
PAGE_SIZE) * sizeof(struct arm_small_page);
arm_add_smallalloc_pages(
(void *)(freemem_after + (KERNVIRTADDR - KERNPHYSADDR)),
(void *)0xc0100000,
freemem_pt - (PHYSADDR + 0x100000), 1);
freemem_after -= ((freemem_after - (PHYSADDR + 0x1000)) / PAGE_SIZE) *
sizeof(struct arm_small_page);
arm_add_smallalloc_pages(
(void *)(freemem_after + (KERNVIRTADDR - KERNPHYSADDR)),
(void *)0xc0001000,
trunc_page(freemem_after) - (PHYSADDR + 0x1000), 0);
freemempos = trunc_page(freemem_after);
freemempos -= PAGE_SIZE;
#endif
/*
* Now construct the L1 page table. First map the L2
* page tables into the L1 so we can replace L1 mappings
* later on if necessary
*/
l1pagetable = kernel_l1pt.pv_va;
/* Map the L2 pages tables in the L1 page table */
pmap_link_l2pt(l1pagetable, ARM_VECTORS_HIGH & ~(0x00100000 - 1),
&kernel_pt_table[KERNEL_PT_SYS]);
pmap_link_l2pt(l1pagetable, IXP425_IO_VBASE,
&kernel_pt_table[KERNEL_PT_IO]);
pmap_link_l2pt(l1pagetable, IXP425_MCU_VBASE,
&kernel_pt_table[KERNEL_PT_IO + 1]);
pmap_link_l2pt(l1pagetable, IXP425_PCI_MEM_VBASE,
&kernel_pt_table[KERNEL_PT_IO + 2]);
pmap_link_l2pt(l1pagetable, KERNBASE,
&kernel_pt_table[KERNEL_PT_BEFOREKERN]);
pmap_map_chunk(l1pagetable, KERNBASE, PHYSADDR, 0x100000,
VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
pmap_map_chunk(l1pagetable, KERNBASE + 0x100000, PHYSADDR + 0x100000,
0x100000, VM_PROT_READ|VM_PROT_WRITE, PTE_PAGETABLE);
pmap_map_chunk(l1pagetable, KERNEL_TEXT_BASE, KERNEL_TEXT_PHYS,
next_chunk2(((uint32_t)lastaddr) - KERNEL_TEXT_BASE, L1_S_SIZE),
VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
freemem_after = next_page((int)lastaddr);
afterkern = round_page(next_chunk2((vm_offset_t)lastaddr, L1_S_SIZE));
for (i = 0; i < KERNEL_PT_AFKERNEL_NUM; i++) {
pmap_link_l2pt(l1pagetable, afterkern + i * 0x00100000,
&kernel_pt_table[KERNEL_PT_AFKERNEL + i]);
}
pmap_map_entry(l1pagetable, afterkern, minidataclean.pv_pa,
VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
#ifdef ARM_USE_SMALL_ALLOC
if ((freemem_after + 2 * PAGE_SIZE) <= afterkern) {
arm_add_smallalloc_pages((void *)(freemem_after),
(void*)(freemem_after + PAGE_SIZE),
afterkern - (freemem_after + PAGE_SIZE), 0);
}
#endif
/* Map the Mini-Data cache clean area. */
xscale_setup_minidata(l1pagetable, afterkern,
minidataclean.pv_pa);
/* Map the vector page. */
pmap_map_entry(l1pagetable, ARM_VECTORS_HIGH, systempage.pv_pa,
VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
if (cpu_is_ixp43x())
pmap_devmap_bootstrap(l1pagetable, ixp435_devmap);
else
pmap_devmap_bootstrap(l1pagetable, ixp425_devmap);
/*
* Give the XScale global cache clean code an appropriately
* sized chunk of unmapped VA space starting at 0xff000000
* (our device mappings end before this address).
*/
xscale_cache_clean_addr = 0xff000000U;
cpu_domains((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT);
setttb(kernel_l1pt.pv_pa);
cpu_tlb_flushID();
cpu_domains(DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2));
/*
* Pages were allocated during the secondary bootstrap for the
* stacks for different CPU modes.
* We must now set the r13 registers in the different CPU modes to
* point to these stacks.
* Since the ARM stacks use STMFD etc. we must set r13 to the top end
* of the stack memory.
*/
set_stackptr(PSR_IRQ32_MODE, irqstack.pv_va + IRQ_STACK_SIZE*PAGE_SIZE);
set_stackptr(PSR_ABT32_MODE, abtstack.pv_va + ABT_STACK_SIZE*PAGE_SIZE);
set_stackptr(PSR_UND32_MODE, undstack.pv_va + UND_STACK_SIZE*PAGE_SIZE);
/*
* We must now clean the cache again....
* Cleaning may be done by reading new data to displace any
* dirty data in the cache. This will have happened in setttb()
* but since we are boot strapping the addresses used for the read
* may have just been remapped and thus the cache could be out
* of sync. A re-clean after the switch will cure this.
* After booting there are no gross relocations of the kernel thus
* this problem will not occur after initarm().
*/
cpu_idcache_wbinv_all();
/* ready to setup the console (XXX move earlier if possible) */
cninit();
/*
* Fetch the RAM size from the MCU registers. The
* expansion bus was mapped above so we can now read 'em.
*/
if (cpu_is_ixp43x())
memsize = ixp435_ddram_size();
else
memsize = ixp425_sdram_size();
physmem = memsize / PAGE_SIZE;
/* Set stack for exception handlers */
data_abort_handler_address = (u_int)data_abort_handler;
prefetch_abort_handler_address = (u_int)prefetch_abort_handler;
undefined_handler_address = (u_int)undefinedinstruction_bounce;
undefined_init();
proc_linkup0(&proc0, &thread0);
thread0.td_kstack = kernelstack.pv_va;
thread0.td_pcb = (struct pcb *)
(thread0.td_kstack + KSTACK_PAGES * PAGE_SIZE) - 1;
thread0.td_pcb->pcb_flags = 0;
thread0.td_frame = &proc0_tf;
pcpup->pc_curpcb = thread0.td_pcb;
arm_vector_init(ARM_VECTORS_HIGH, ARM_VEC_ALL);
pmap_curmaxkvaddr = afterkern + PAGE_SIZE;
dump_avail[0] = PHYSADDR;
dump_avail[1] = PHYSADDR + memsize;
dump_avail[2] = 0;
dump_avail[3] = 0;
pmap_bootstrap(pmap_curmaxkvaddr, 0xd0000000, &kernel_l1pt);
msgbufp = (void*)msgbufpv.pv_va;
msgbufinit(msgbufp, msgbufsize);
mutex_init();
i = 0;
#ifdef ARM_USE_SMALL_ALLOC
phys_avail[i++] = PHYSADDR;
phys_avail[i++] = PHYSADDR + PAGE_SIZE; /*
*XXX: Gross hack to get our
* pages in the vm_page_array.
*/
#endif
phys_avail[i++] = round_page(virtual_avail - KERNBASE + PHYSADDR);
phys_avail[i++] = trunc_page(PHYSADDR + memsize - 1);
phys_avail[i++] = 0;
phys_avail[i] = 0;
init_param2(physmem);
kdb_init();
/* use static kernel environment if so configured */
if (envmode == 1)
kern_envp = static_env;
return ((void *)(kernelstack.pv_va + USPACE_SVC_STACK_TOP -
sizeof(struct pcb)));
#undef next_page
#undef next_chunk2
}
void *
initarm(void *arg, void *arg2)
{
struct pv_addr kernel_l1pt;
struct pv_addr dpcpu;
int loop, i;
u_int l1pagetable;
vm_offset_t freemempos;
vm_offset_t freemem_pt;
vm_offset_t afterkern;
vm_offset_t freemem_after;
vm_offset_t lastaddr;
uint32_t memsize, memstart;
set_cpufuncs();
lastaddr = fake_preload_metadata();
pcpu_init(pcpup, 0, sizeof(struct pcpu));
PCPU_SET(curthread, &thread0);
freemempos = 0xa0200000;
/* Define a macro to simplify memory allocation */
#define valloc_pages(var, np) \
alloc_pages((var).pv_pa, (np)); \
(var).pv_va = (var).pv_pa + 0x20000000;
#define alloc_pages(var, np) \
freemempos -= (np * PAGE_SIZE); \
(var) = freemempos; \
memset((char *)(var), 0, ((np) * PAGE_SIZE));
while (((freemempos - L1_TABLE_SIZE) & (L1_TABLE_SIZE - 1)) != 0)
freemempos -= PAGE_SIZE;
valloc_pages(kernel_l1pt, L1_TABLE_SIZE / PAGE_SIZE);
for (loop = 0; loop < NUM_KERNEL_PTS; ++loop) {
if (!(loop % (PAGE_SIZE / L2_TABLE_SIZE_REAL))) {
valloc_pages(kernel_pt_table[loop],
L2_TABLE_SIZE / PAGE_SIZE);
} else {
kernel_pt_table[loop].pv_pa = freemempos +
(loop % (PAGE_SIZE / L2_TABLE_SIZE_REAL)) *
L2_TABLE_SIZE_REAL;
kernel_pt_table[loop].pv_va =
kernel_pt_table[loop].pv_pa + 0x20000000;
}
i++;
}
freemem_pt = freemempos;
freemempos = 0xa0100000;
/*
* Allocate a page for the system page mapped to V0x00000000
* This page will just contain the system vectors and can be
* shared by all processes.
*/
valloc_pages(systempage, 1);
/* Allocate dynamic per-cpu area. */
valloc_pages(dpcpu, DPCPU_SIZE / PAGE_SIZE);
dpcpu_init((void *)dpcpu.pv_va, 0);
/* Allocate stacks for all modes */
valloc_pages(irqstack, IRQ_STACK_SIZE);
valloc_pages(abtstack, ABT_STACK_SIZE);
valloc_pages(undstack, UND_STACK_SIZE);
valloc_pages(kernelstack, KSTACK_PAGES);
alloc_pages(minidataclean.pv_pa, 1);
valloc_pages(msgbufpv, round_page(MSGBUF_SIZE) / PAGE_SIZE);
#ifdef ARM_USE_SMALL_ALLOC
freemempos -= PAGE_SIZE;
freemem_pt = trunc_page(freemem_pt);
freemem_after = freemempos - ((freemem_pt - 0xa0100000) /
PAGE_SIZE) * sizeof(struct arm_small_page);
arm_add_smallalloc_pages((void *)(freemem_after + 0x20000000)
, (void *)0xc0100000, freemem_pt - 0xa0100000, 1);
freemem_after -= ((freemem_after - 0xa0001000) / PAGE_SIZE) *
sizeof(struct arm_small_page);
arm_add_smallalloc_pages((void *)(freemem_after + 0x20000000),
(void *)0xc0001000,
trunc_page(freemem_after) - 0xa0001000, 0);
freemempos = trunc_page(freemem_after);
freemempos -= PAGE_SIZE;
#endif
/*
* Allocate memory for the l1 and l2 page tables. The scheme to avoid
* wasting memory by allocating the l1pt on the first 16k memory was
* taken from NetBSD rpc_machdep.c. NKPT should be greater than 12 for
* this to work (which is supposed to be the case).
*/
/*
* Now we start construction of the L1 page table
* We start by mapping the L2 page tables into the L1.
* This means that we can replace L1 mappings later on if necessary
*/
l1pagetable = kernel_l1pt.pv_va;
/* Map the L2 pages tables in the L1 page table */
pmap_link_l2pt(l1pagetable, ARM_VECTORS_HIGH & ~(0x00100000 - 1),
&kernel_pt_table[KERNEL_PT_SYS]);
pmap_link_l2pt(l1pagetable, IQ80321_IOPXS_VBASE,
&kernel_pt_table[KERNEL_PT_IOPXS]);
pmap_link_l2pt(l1pagetable, KERNBASE,
&kernel_pt_table[KERNEL_PT_BEFOREKERN]);
pmap_map_chunk(l1pagetable, KERNBASE, IQ80321_SDRAM_START, 0x100000,
VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
pmap_map_chunk(l1pagetable, KERNBASE + 0x100000, IQ80321_SDRAM_START + 0x100000,
0x100000, VM_PROT_READ|VM_PROT_WRITE, PTE_PAGETABLE);
pmap_map_chunk(l1pagetable, KERNBASE + 0x200000, IQ80321_SDRAM_START + 0x200000,
(((uint32_t)(lastaddr) - KERNBASE - 0x200000) + L1_S_SIZE) & ~(L1_S_SIZE - 1),
VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
freemem_after = ((int)lastaddr + PAGE_SIZE) & ~(PAGE_SIZE - 1);
afterkern = round_page(((vm_offset_t)lastaddr + L1_S_SIZE) & ~(L1_S_SIZE
- 1));
for (i = 0; i < KERNEL_PT_AFKERNEL_NUM; i++) {
pmap_link_l2pt(l1pagetable, afterkern + i * 0x00100000,
&kernel_pt_table[KERNEL_PT_AFKERNEL + i]);
}
pmap_map_entry(l1pagetable, afterkern, minidataclean.pv_pa,
VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
#ifdef ARM_USE_SMALL_ALLOC
if ((freemem_after + 2 * PAGE_SIZE) <= afterkern) {
arm_add_smallalloc_pages((void *)(freemem_after),
(void*)(freemem_after + PAGE_SIZE),
afterkern - (freemem_after + PAGE_SIZE), 0);
}
#endif
/* Map the Mini-Data cache clean area. */
xscale_setup_minidata(l1pagetable, afterkern,
minidataclean.pv_pa);
/* Map the vector page. */
pmap_map_entry(l1pagetable, ARM_VECTORS_HIGH, systempage.pv_pa,
VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
pmap_devmap_bootstrap(l1pagetable, ep80219_devmap);
/*
* Give the XScale global cache clean code an appropriately
* sized chunk of unmapped VA space starting at 0xff000000
* (our device mappings end before this address).
*/
xscale_cache_clean_addr = 0xff000000U;
cpu_domains((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT);
setttb(kernel_l1pt.pv_pa);
cpu_tlb_flushID();
cpu_domains(DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2));
/*
* Pages were allocated during the secondary bootstrap for the
* stacks for different CPU modes.
* We must now set the r13 registers in the different CPU modes to
* point to these stacks.
* Since the ARM stacks use STMFD etc. we must set r13 to the top end
* of the stack memory.
*/
set_stackptr(PSR_IRQ32_MODE,
irqstack.pv_va + IRQ_STACK_SIZE * PAGE_SIZE);
set_stackptr(PSR_ABT32_MODE,
abtstack.pv_va + ABT_STACK_SIZE * PAGE_SIZE);
set_stackptr(PSR_UND32_MODE,
undstack.pv_va + UND_STACK_SIZE * PAGE_SIZE);
/*
* We must now clean the cache again....
* Cleaning may be done by reading new data to displace any
* dirty data in the cache. This will have happened in setttb()
* but since we are boot strapping the addresses used for the read
* may have just been remapped and thus the cache could be out
* of sync. A re-clean after the switch will cure this.
* After booting there are no gross relocations of the kernel thus
* this problem will not occur after initarm().
*/
cpu_idcache_wbinv_all();
/*
* Fetch the SDRAM start/size from the i80321 SDRAM configration
* registers.
*/
i80321_calibrate_delay();
i80321_sdram_bounds(&obio_bs_tag, IQ80321_80321_VBASE + VERDE_MCU_BASE,
&memstart, &memsize);
physmem = memsize / PAGE_SIZE;
cninit();
/* Set stack for exception handlers */
data_abort_handler_address = (u_int)data_abort_handler;
prefetch_abort_handler_address = (u_int)prefetch_abort_handler;
undefined_handler_address = (u_int)undefinedinstruction_bounce;
undefined_init();
proc_linkup0(&proc0, &thread0);
thread0.td_kstack = kernelstack.pv_va;
thread0.td_pcb = (struct pcb *)
(thread0.td_kstack + KSTACK_PAGES * PAGE_SIZE) - 1;
thread0.td_pcb->pcb_flags = 0;
thread0.td_frame = &proc0_tf;
pcpup->pc_curpcb = thread0.td_pcb;
/* Enable MMU, I-cache, D-cache, write buffer. */
arm_vector_init(ARM_VECTORS_HIGH, ARM_VEC_ALL);
pmap_curmaxkvaddr = afterkern + PAGE_SIZE;
dump_avail[0] = 0xa0000000;
dump_avail[1] = 0xa0000000 + memsize;
dump_avail[2] = 0;
dump_avail[3] = 0;
pmap_bootstrap(pmap_curmaxkvaddr,
0xd0000000, &kernel_l1pt);
msgbufp = (void*)msgbufpv.pv_va;
msgbufinit(msgbufp, MSGBUF_SIZE);
mutex_init();
i = 0;
#ifdef ARM_USE_SMALL_ALLOC
phys_avail[i++] = 0xa0000000;
phys_avail[i++] = 0xa0001000; /*
*XXX: Gross hack to get our
* pages in the vm_page_array
. */
#endif
phys_avail[i++] = round_page(virtual_avail - KERNBASE + IQ80321_SDRAM_START);
phys_avail[i++] = trunc_page(0xa0000000 + memsize - 1);
phys_avail[i++] = 0;
phys_avail[i] = 0;
/* Do basic tuning, hz etc */
init_param1();
init_param2(physmem);
kdb_init();
return ((void *)(kernelstack.pv_va + USPACE_SVC_STACK_TOP -
sizeof(struct pcb)));
}