/**Function*************************************************************
Synopsis [Transform the logic network into a netlist.]
Description [The logic network given to this procedure should
have exactly the same structure as the resulting netlist. The COs
can only point to CIs if they have identical names. Otherwise,
they should have a node between them, even if this node is
inverter or buffer.]
SideEffects []
SeeAlso []
***********************************************************************/
Abc_Ntk_t * Abc_NtkLogicToNetlist( Abc_Ntk_t * pNtk )
{
Abc_Ntk_t * pNtkNew;
Abc_Obj_t * pObj, * pNet, * pDriver, * pFanin;
int i, k;
assert( Abc_NtkIsLogic(pNtk) );
// remove dangling nodes
Abc_NtkCleanup( pNtk, 0 );
// make sure the CO names are unique
Abc_NtkCheckUniqueCiNames( pNtk );
Abc_NtkCheckUniqueCoNames( pNtk );
Abc_NtkCheckUniqueCioNames( pNtk );
// assert( Abc_NtkLogicHasSimpleCos(pNtk) );
if ( !Abc_NtkLogicHasSimpleCos(pNtk) )
{
printf( "Abc_NtkLogicToNetlist() warning: The network is converted to have simple COs.\n" );
Abc_NtkLogicMakeSimpleCos( pNtk, 0 );
}
// start the netlist by creating PI/PO/Latch objects
pNtkNew = Abc_NtkStartFrom( pNtk, ABC_NTK_NETLIST, pNtk->ntkFunc );
// create the CI nets and remember them in the new CI nodes
Abc_NtkForEachCi( pNtk, pObj, i )
{
pNet = Abc_NtkFindOrCreateNet( pNtkNew, Abc_ObjName(pObj) );
Abc_ObjAddFanin( pNet, pObj->pCopy );
pObj->pCopy->pCopy = pNet;
}
/**Function*************************************************************
Synopsis [Writes the graph structure of AIG in GML.]
Description [Useful for graph visualization using tools such as yEd:
http://www.yworks.com/]
SideEffects []
SeeAlso []
***********************************************************************/
void Io_WriteGml( Abc_Ntk_t * pNtk, char * pFileName )
{
FILE * pFile;
Abc_Obj_t * pObj, * pFanin;
int i, k;
assert( Abc_NtkIsStrash(pNtk) || Abc_NtkIsLogic(pNtk) );
// start the output stream
pFile = fopen( pFileName, "w" );
if ( pFile == NULL )
{
fprintf( stdout, "Io_WriteGml(): Cannot open the output file \"%s\".\n", pFileName );
return;
}
fprintf( pFile, "# GML for \"%s\" written by ABC on %s\n", pNtk->pName, Extra_TimeStamp() );
fprintf( pFile, "graph [\n" );
// output the POs
fprintf( pFile, "\n" );
Abc_NtkForEachPo( pNtk, pObj, i )
{
fprintf( pFile, " node [ id %5d label \"%s\"\n", pObj->Id, Abc_ObjName(pObj) );
fprintf( pFile, " graphics [ type \"triangle\" fill \"#00FFFF\" ]\n" ); // blue
fprintf( pFile, " ]\n" );
}
ABC_NAMESPACE_IMPL_START
////////////////////////////////////////////////////////////////////////
/// DECLARATIONS ///
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
/// FUNCTION DEFINITIONS ///
////////////////////////////////////////////////////////////////////////
/**Function*************************************************************
Synopsis [Converts old ABC network into new ABC network.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Nwk_Man_t * Abc_NtkToNtkNew( Abc_Ntk_t * pNtk )
{
Vec_Ptr_t * vNodes;
Nwk_Man_t * pNtkNew;
Nwk_Obj_t * pObjNew;
Abc_Obj_t * pObj, * pFanin;
int i, k;
if ( !Abc_NtkIsLogic(pNtk) )
{
fprintf( stdout, "This is not a logic network.\n" );
return 0;
}
// convert into the AIG
if ( !Abc_NtkToAig(pNtk) )
{
fprintf( stdout, "Converting to AIGs has failed.\n" );
return 0;
}
assert( Abc_NtkHasAig(pNtk) );
// construct the network
pNtkNew = Nwk_ManAlloc();
pNtkNew->pName = Extra_UtilStrsav( pNtk->pName );
pNtkNew->pSpec = Extra_UtilStrsav( pNtk->pSpec );
Abc_NtkForEachCi( pNtk, pObj, i )
pObj->pCopy = (Abc_Obj_t *)Nwk_ManCreateCi( pNtkNew, Abc_ObjFanoutNum(pObj) );
vNodes = Abc_NtkDfs( pNtk, 1 );
Vec_PtrForEachEntry( Abc_Obj_t *, vNodes, pObj, i )
{
pObjNew = Nwk_ManCreateNode( pNtkNew, Abc_ObjFaninNum(pObj), Abc_ObjFanoutNum(pObj) );
Abc_ObjForEachFanin( pObj, pFanin, k )
Nwk_ObjAddFanin( pObjNew, (Nwk_Obj_t *)pFanin->pCopy );
pObjNew->pFunc = Hop_Transfer( (Hop_Man_t *)pNtk->pManFunc, pNtkNew->pManHop, (Hop_Obj_t *)pObj->pData, Abc_ObjFaninNum(pObj) );
pObj->pCopy = (Abc_Obj_t *)pObjNew;
}
/**Function*************************************************************
Synopsis [Prints statistics about latches.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Abc_NtkPrintLatch( FILE * pFile, Abc_Ntk_t * pNtk )
{
Abc_Obj_t * pLatch, * pFanin;
int i, Counter0, Counter1, Counter2;
int InitNums[4], Init;
assert( !Abc_NtkIsNetlist(pNtk) );
if ( Abc_NtkLatchNum(pNtk) == 0 )
{
fprintf( pFile, "The network is combinational.\n" );
return;
}
for ( i = 0; i < 4; i++ )
InitNums[i] = 0;
Counter0 = Counter1 = Counter2 = 0;
Abc_NtkForEachLatch( pNtk, pLatch, i )
{
Init = Abc_LatchInit( pLatch );
assert( Init < 4 );
InitNums[Init]++;
pFanin = Abc_ObjFanin0(Abc_ObjFanin0(pLatch));
if ( Abc_NtkIsLogic(pNtk) )
{
if ( !Abc_NodeIsConst(pFanin) )
continue;
}
else if ( Abc_NtkIsStrash(pNtk) )
{
if ( !Abc_AigNodeIsConst(pFanin) )
continue;
}
else
assert( 0 );
// the latch input is a constant node
Counter0++;
if ( Abc_LatchIsInitDc(pLatch) )
{
Counter1++;
continue;
}
// count the number of cases when the constant is equal to the initial value
if ( Abc_NtkIsStrash(pNtk) )
{
if ( Abc_LatchIsInit1(pLatch) == !Abc_ObjFaninC0(pLatch) )
Counter2++;
}
else
{
if ( Abc_LatchIsInit1(pLatch) == Abc_NodeIsConst1(pLatch) )
Counter2++;
}
}
/**Function*************************************************************
Synopsis [Visualizes AIG with choices.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Abc_NtkShow( Abc_Ntk_t * pNtk, int fGateNames, int fSeq, int fUseReverse )
{
FILE * pFile;
Abc_Obj_t * pNode;
Vec_Ptr_t * vNodes;
char FileNameDot[200];
int i;
assert( Abc_NtkIsStrash(pNtk) || Abc_NtkIsLogic(pNtk) );
if ( Abc_NtkIsStrash(pNtk) && Abc_NtkGetChoiceNum(pNtk) )
{
printf( "Temporarily visualization of AIGs with choice nodes is disabled.\n" );
return;
}
// convert to logic SOP
if ( Abc_NtkIsLogic(pNtk) )
Abc_NtkToSop( pNtk, 0 );
// create the file name
Abc_ShowGetFileName( pNtk->pName, FileNameDot );
// check that the file can be opened
if ( (pFile = fopen( FileNameDot, "w" )) == NULL )
{
fprintf( stdout, "Cannot open the intermediate file \"%s\".\n", FileNameDot );
return;
}
fclose( pFile );
// collect all nodes in the network
vNodes = Vec_PtrAlloc( 100 );
Abc_NtkForEachObj( pNtk, pNode, i )
Vec_PtrPush( vNodes, pNode );
// write the DOT file
if ( fSeq )
Io_WriteDotSeq( pNtk, vNodes, NULL, FileNameDot, fGateNames, fUseReverse );
else
Io_WriteDotNtk( pNtk, vNodes, NULL, FileNameDot, fGateNames, fUseReverse );
Vec_PtrFree( vNodes );
// visualize the file
Abc_ShowFile( FileNameDot );
}
/**Function*************************************************************
Synopsis [Derives GIA manager using special pins to denote box boundaries.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Gia_Man_t * Abc_NtkTestPinDeriveGia( Abc_Ntk_t * pNtk, int fWhiteBoxOnly, int fVerbose )
{
Gia_Man_t * pTemp;
Gia_Man_t * pGia = NULL;
Vec_Ptr_t * vNodes;
Abc_Obj_t * pObj, * pFanin;
int i, k, iPinLit = 0;
// prepare logic network
assert( Abc_NtkIsLogic(pNtk) );
Abc_NtkToAig( pNtk );
// construct GIA
Abc_NtkFillTemp( pNtk );
pGia = Gia_ManStart( Abc_NtkObjNumMax(pNtk) );
Gia_ManHashAlloc( pGia );
// create primary inputs
Abc_NtkForEachCi( pNtk, pObj, i )
pObj->iTemp = Gia_ManAppendCi(pGia);
// create internal nodes in a topologic order from white boxes
vNodes = Abc_NtkDfs( pNtk, 0 );
Vec_PtrForEachEntry( Abc_Obj_t *, vNodes, pObj, i )
{
// input side
if ( !fWhiteBoxOnly || Abc_NodeIsWhiteBox(pObj) )
{
// create special pintype for this node
iPinLit = Gia_ManAppendPinType( pGia, 1 );
// create input pins
Abc_ObjForEachFanin( pObj, pFanin, k )
pFanin->iTemp = Gia_ManAppendAnd( pGia, pFanin->iTemp, iPinLit );
}
// perform GIA construction
pObj->iTemp = Abc_NtkTestTimNodeStrash( pGia, pObj );
// output side
if ( !fWhiteBoxOnly || Abc_NodeIsWhiteBox(pObj) )
{
// create special pintype for this node
iPinLit = Gia_ManAppendPinType( pGia, 1 );
// create output pins
pObj->iTemp = Gia_ManAppendAnd( pGia, pObj->iTemp, iPinLit );
}
}
Vec_PtrFree( vNodes );
// create primary outputs
Abc_NtkForEachCo( pNtk, pObj, i )
pObj->iTemp = Gia_ManAppendCo( pGia, Abc_ObjFanin0(pObj)->iTemp );
// finalize GIA
Gia_ManHashStop( pGia );
Gia_ManSetRegNum( pGia, 0 );
// clean up GIA
pGia = Gia_ManCleanup( pTemp = pGia );
Gia_ManStop( pTemp );
return pGia;
}
/**Function*************************************************************
Synopsis [Transform the logic network into a netlist.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Abc_Ntk_t * Abc_NtkToNetlist( Abc_Ntk_t * pNtk )
{
Abc_Ntk_t * pNtkNew, * pNtkTemp;
assert( Abc_NtkIsLogic(pNtk) || Abc_NtkIsStrash(pNtk) );
if ( Abc_NtkIsStrash(pNtk) )
{
pNtkTemp = Abc_NtkAigToLogicSop(pNtk);
pNtkNew = Abc_NtkLogicToNetlist( pNtkTemp );
Abc_NtkDelete( pNtkTemp );
return pNtkNew;
}
return Abc_NtkLogicToNetlist( pNtk );
}
/**Function*************************************************************
Synopsis [Used for automated debugging.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
int Abc_NtkRetimeDebug( Abc_Ntk_t * pNtk )
{
extern int Abc_NtkSecFraig( Abc_Ntk_t * pNtk1, Abc_Ntk_t * pNtk2, int nSeconds, int nFrames, int fVerbose );
Abc_Ntk_t * pNtkRet;
assert( Abc_NtkIsLogic(pNtk) );
Abc_NtkToSop( pNtk, 0 );
// if ( !Abc_NtkCheck( pNtk ) )
// fprintf( stdout, "Abc_NtkRetimeDebug(): Network check has failed.\n" );
// Io_WriteBlifLogic( pNtk, "debug_temp.blif", 1 );
pNtkRet = Abc_NtkDup( pNtk );
Abc_NtkRetime( pNtkRet, 3, 0, 1, 0, 0 ); // debugging backward flow
return !Abc_NtkSecFraig( pNtk, pNtkRet, 10000, 3, 0 );
}
/**Function*************************************************************
Synopsis [Minimizes SOP representations using Espresso.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Abc_NtkEspresso( Abc_Ntk_t * pNtk, int fVerbose )
{
Abc_Obj_t * pNode;
int i;
assert( Abc_NtkIsLogic(pNtk) );
// convert the network to have SOPs
if ( Abc_NtkHasMapping(pNtk) )
Abc_NtkMapToSop(pNtk);
else if ( Abc_NtkHasBdd(pNtk) )
{
if ( !Abc_NtkBddToSop(pNtk, -1, ABC_INFINITY) )
{
printf( "Abc_NtkEspresso(): Converting to SOPs has failed.\n" );
return;
}
}
// minimize SOPs of all nodes
Abc_NtkForEachNode( pNtk, pNode, i )
if ( i ) Abc_NodeEspresso( pNode );
}
/**Function*************************************************************
Synopsis []
Description []
SideEffects []
SeeAlso []
***********************************************************************/
int Abc_NtkMfs( Abc_Ntk_t * pNtk, Mfs_Par_t * pPars )
{
extern Aig_Man_t * Abc_NtkToDar( Abc_Ntk_t * pNtk, int fExors, int fRegisters );
Bdc_Par_t Pars = {0}, * pDecPars = &Pars;
ProgressBar * pProgress;
Mfs_Man_t * p;
Abc_Obj_t * pObj;
Vec_Vec_t * vLevels;
Vec_Ptr_t * vNodes;
int i, k, nNodes, nFaninMax;
abctime clk = Abc_Clock(), clk2;
int nTotalNodesBeg = Abc_NtkNodeNum(pNtk);
int nTotalEdgesBeg = Abc_NtkGetTotalFanins(pNtk);
assert( Abc_NtkIsLogic(pNtk) );
nFaninMax = Abc_NtkGetFaninMax(pNtk);
if ( pPars->fResub )
{
if ( nFaninMax > 8 )
{
printf( "Nodes with more than %d fanins will not be processed.\n", 8 );
nFaninMax = 8;
}
}
else
{
if ( nFaninMax > MFS_FANIN_MAX )
{
printf( "Nodes with more than %d fanins will not be processed.\n", MFS_FANIN_MAX );
nFaninMax = MFS_FANIN_MAX;
}
}
// perform the network sweep
// Abc_NtkSweep( pNtk, 0 );
// convert into the AIG
if ( !Abc_NtkToAig(pNtk) )
{
fprintf( stdout, "Converting to AIGs has failed.\n" );
return 0;
}
assert( Abc_NtkHasAig(pNtk) );
// start the manager
p = Mfs_ManAlloc( pPars );
p->pNtk = pNtk;
p->nFaninMax = nFaninMax;
// precomputer power-aware metrics
if ( pPars->fPower )
{
extern Vec_Int_t * Abc_NtkPowerEstimate( Abc_Ntk_t * pNtk, int fProbOne );
if ( pPars->fResub )
p->vProbs = Abc_NtkPowerEstimate( pNtk, 0 );
else
p->vProbs = Abc_NtkPowerEstimate( pNtk, 1 );
#if 0
printf( "Total switching before = %7.2f.\n", Abc_NtkMfsTotalSwitching(pNtk) );
#else
p->TotalSwitchingBeg = Abc_NtkMfsTotalSwitching(pNtk);
#endif
}
if ( pNtk->pExcare )
{
Abc_Ntk_t * pTemp;
if ( Abc_NtkPiNum((Abc_Ntk_t *)pNtk->pExcare) != Abc_NtkCiNum(pNtk) )
printf( "The PI count of careset (%d) and logic network (%d) differ. Careset is not used.\n",
Abc_NtkPiNum((Abc_Ntk_t *)pNtk->pExcare), Abc_NtkCiNum(pNtk) );
else
{
pTemp = Abc_NtkStrash( (Abc_Ntk_t *)pNtk->pExcare, 0, 0, 0 );
p->pCare = Abc_NtkToDar( pTemp, 0, 0 );
Abc_NtkDelete( pTemp );
p->vSuppsInv = Aig_ManSupportsInverse( p->pCare );
}
}
if ( p->pCare != NULL )
printf( "Performing optimization with %d external care clauses.\n", Aig_ManCoNum(p->pCare) );
// prepare the BDC manager
if ( !pPars->fResub )
{
pDecPars->nVarsMax = (nFaninMax < 3) ? 3 : nFaninMax;
pDecPars->fVerbose = pPars->fVerbose;
p->vTruth = Vec_IntAlloc( 0 );
p->pManDec = Bdc_ManAlloc( pDecPars );
}
// label the register outputs
if ( p->pCare )
{
Abc_NtkForEachCi( pNtk, pObj, i )
pObj->pData = (void *)(ABC_PTRUINT_T)i;
}
// compute levels
Abc_NtkLevel( pNtk );
Abc_NtkStartReverseLevels( pNtk, pPars->nGrowthLevel );
// compute don't-cares for each node
nNodes = 0;
p->nTotalNodesBeg = nTotalNodesBeg;
p->nTotalEdgesBeg = nTotalEdgesBeg;
if ( pPars->fResub )
{
#if 0
printf( "TotalSwitching (%7.2f --> ", Abc_NtkMfsTotalSwitching(pNtk) );
#endif
if (pPars->fPower)
{
Abc_NtkMfsPowerResub( p, pPars);
} else
{
pProgress = Extra_ProgressBarStart( stdout, Abc_NtkObjNumMax(pNtk) );
Abc_NtkForEachNode( pNtk, pObj, i )
{
if ( p->pPars->nDepthMax && (int)pObj->Level > p->pPars->nDepthMax )
continue;
if ( Abc_ObjFaninNum(pObj) < 2 || Abc_ObjFaninNum(pObj) > nFaninMax )
continue;
if ( !p->pPars->fVeryVerbose )
Extra_ProgressBarUpdate( pProgress, i, NULL );
if ( pPars->fResub )
Abc_NtkMfsResub( p, pObj );
else
Abc_NtkMfsNode( p, pObj );
}
Extra_ProgressBarStop( pProgress );
#if 0
printf( " %7.2f )\n", Abc_NtkMfsTotalSwitching(pNtk) );
#endif
}
} else
/**Function*************************************************************
Synopsis [Performs minimum-register retiming.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Abc_Ntk_t *
Abc_FlowRetime_MinReg( Abc_Ntk_t * pNtk, int fVerbose,
int fComputeInitState, int fGuaranteeInitState, int fBlockConst,
int fForwardOnly, int fBackwardOnly, int nMaxIters,
int maxDelay, int fFastButConservative ) {
int i;
Abc_Obj_t *pObj, *pNext;
InitConstraint_t *pData;
// create manager
pManMR = ALLOC( MinRegMan_t, 1 );
pManMR->pNtk = pNtk;
pManMR->fVerbose = fVerbose;
pManMR->fComputeInitState = fComputeInitState;
pManMR->fGuaranteeInitState = fGuaranteeInitState;
pManMR->fBlockConst = fBlockConst;
pManMR->fForwardOnly = fForwardOnly;
pManMR->fBackwardOnly = fBackwardOnly;
pManMR->nMaxIters = nMaxIters;
pManMR->maxDelay = maxDelay;
pManMR->fComputeInitState = fComputeInitState;
pManMR->fConservTimingOnly = fFastButConservative;
pManMR->vNodes = Vec_PtrAlloc(100);
pManMR->vInitConstraints = Vec_PtrAlloc(2);
pManMR->pInitNtk = NULL;
pManMR->pInitToOrig = NULL;
pManMR->sizeInitToOrig = 0;
vprintf("Flow-based minimum-register retiming...\n");
if (!Abc_NtkHasOnlyLatchBoxes(pNtk)) {
printf("\tERROR: Can not retime with black/white boxes\n");
return pNtk;
}
if (maxDelay) {
vprintf("\tmax delay constraint = %d\n", maxDelay);
if (maxDelay < (i = Abc_NtkLevel(pNtk))) {
printf("ERROR: max delay constraint (%d) must be > current max delay (%d)\n", maxDelay, i);
return pNtk;
}
}
// print info about type of network
vprintf("\tnetlist type = ");
if (Abc_NtkIsNetlist( pNtk )) { vprintf("netlist/"); }
else if (Abc_NtkIsLogic( pNtk )) { vprintf("logic/"); }
else if (Abc_NtkIsStrash( pNtk )) { vprintf("strash/"); }
else { vprintf("***unknown***/"); }
if (Abc_NtkHasSop( pNtk )) { vprintf("sop\n"); }
else if (Abc_NtkHasBdd( pNtk )) { vprintf("bdd\n"); }
else if (Abc_NtkHasAig( pNtk )) { vprintf("aig\n"); }
else if (Abc_NtkHasMapping( pNtk )) { vprintf("mapped\n"); }
else { vprintf("***unknown***\n"); }
vprintf("\tinitial reg count = %d\n", Abc_NtkLatchNum(pNtk));
vprintf("\tinitial levels = %d\n", Abc_NtkLevel(pNtk));
// remove bubbles from latch boxes
if (pManMR->fVerbose) Abc_FlowRetime_PrintInitStateInfo(pNtk);
vprintf("\tpushing bubbles out of latch boxes\n");
Abc_NtkForEachLatch( pNtk, pObj, i )
Abc_FlowRetime_RemoveLatchBubbles(pObj);
if (pManMR->fVerbose) Abc_FlowRetime_PrintInitStateInfo(pNtk);
// check for box inputs/outputs
Abc_NtkForEachLatch( pNtk, pObj, i ) {
assert(Abc_ObjFaninNum(pObj) == 1);
assert(Abc_ObjFanoutNum(pObj) == 1);
assert(!Abc_ObjFaninC0(pObj));
pNext = Abc_ObjFanin0(pObj);
assert(Abc_ObjIsBi(pNext));
assert(Abc_ObjFaninNum(pNext) <= 1);
if(Abc_ObjFaninNum(pNext) == 0) // every Bi should have a fanin
Abc_FlowRetime_AddDummyFanin( pNext );
pNext = Abc_ObjFanout0(pObj);
assert(Abc_ObjIsBo(pNext));
assert(Abc_ObjFaninNum(pNext) == 1);
assert(!Abc_ObjFaninC0(pNext));
}
/**Function*************************************************************
Synopsis [Write the network into file.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Io_WriteHie( Abc_Ntk_t * pNtk, char * pBaseName, char * pFileName )
{
Abc_Ntk_t * pNtkTemp, * pNtkResult, * pNtkBase = NULL;
// check if the current network is available
if ( pNtk == NULL )
{
fprintf( stdout, "Empty network.\n" );
return;
}
// read the base network
assert( Abc_NtkIsStrash(pNtk) || Abc_NtkIsLogic(pNtk) );
if ( Io_ReadFileType(pBaseName) == IO_FILE_BLIF )
pNtkBase = Io_ReadBlifMv( pBaseName, 0, 1 );
else if ( Io_ReadFileType(pBaseName) == IO_FILE_BLIFMV )
pNtkBase = Io_ReadBlifMv( pBaseName, 1, 1 );
else if ( Io_ReadFileType(pBaseName) == IO_FILE_VERILOG )
pNtkBase = Io_ReadVerilog( pBaseName, 1 );
else
fprintf( stderr, "Unknown input file format.\n" );
if ( pNtkBase == NULL )
return;
// flatten logic hierarchy if present
if ( Abc_NtkWhiteboxNum(pNtkBase) > 0 )
{
pNtkBase = Abc_NtkFlattenLogicHierarchy( pNtkTemp = pNtkBase );
if ( pNtkBase == NULL )
return;
Abc_NtkDelete( pNtkTemp );
}
// reintroduce the boxes into the netlist
if ( Io_ReadFileType(pBaseName) == IO_FILE_BLIFMV )
{
if ( Abc_NtkBlackboxNum(pNtkBase) > 0 )
{
printf( "Hierarchy writer does not support BLIF-MV with blackboxes.\n" );
Abc_NtkDelete( pNtkBase );
return;
}
// convert the current network to BLIF-MV
assert( !Abc_NtkIsNetlist(pNtk) );
pNtkResult = Abc_NtkToNetlist( pNtk );
if ( !Abc_NtkConvertToBlifMv( pNtkResult ) )
return;
// reintroduce the network
pNtkResult = Abc_NtkInsertBlifMv( pNtkBase, pNtkTemp = pNtkResult );
Abc_NtkDelete( pNtkTemp );
}
else if ( Abc_NtkBlackboxNum(pNtkBase) > 0 )
{
// derive the netlist
pNtkResult = Abc_NtkToNetlist( pNtk );
pNtkResult = Abc_NtkInsertNewLogic( pNtkBase, pNtkTemp = pNtkResult );
Abc_NtkDelete( pNtkTemp );
if ( pNtkResult )
printf( "Hierarchy writer reintroduced %d instances of blackboxes.\n", Abc_NtkBlackboxNum(pNtkBase) );
}
else
{
printf( "Warning: The output network does not contain blackboxes.\n" );
pNtkResult = Abc_NtkToNetlist( pNtk );
}
Abc_NtkDelete( pNtkBase );
if ( pNtkResult == NULL )
return;
// write the resulting network
if ( Io_ReadFileType(pFileName) == IO_FILE_BLIF )
{
if ( !Abc_NtkHasSop(pNtkResult) && !Abc_NtkHasMapping(pNtkResult) )
Abc_NtkToSop( pNtkResult, 0 );
Io_WriteBlif( pNtkResult, pFileName, 1 );
}
else if ( Io_ReadFileType(pFileName) == IO_FILE_VERILOG )
{
if ( !Abc_NtkHasAig(pNtkResult) && !Abc_NtkHasMapping(pNtkResult) )
Abc_NtkToAig( pNtkResult );
Io_WriteVerilog( pNtkResult, pFileName );
}
else if ( Io_ReadFileType(pFileName) == IO_FILE_BLIFMV )
{
Io_WriteBlifMv( pNtkResult, pFileName );
}
else
fprintf( stderr, "Unknown output file format.\n" );
Abc_NtkDelete( pNtkResult );
}
/**Function*************************************************************
Synopsis [Transfers names from one netlist to the other.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Abc_NtkDress( Abc_Ntk_t * pNtkLogic, char * pFileName, int fVerbose )
{
Abc_Ntk_t * pNtkOrig, * pNtkLogicOrig;
Abc_Ntk_t * pMiter, * pMiterFraig;
stmm_table * tMapping;
assert( Abc_NtkIsLogic(pNtkLogic) );
// get the original netlist
pNtkOrig = Io_ReadNetlist( pFileName, Io_ReadFileType(pFileName), 1 );
if ( pNtkOrig == NULL )
return;
assert( Abc_NtkIsNetlist(pNtkOrig) );
Abc_NtkCleanCopy(pNtkLogic);
Abc_NtkCleanCopy(pNtkOrig);
// convert it into the logic network
pNtkLogicOrig = Abc_NtkToLogic( pNtkOrig );
// check that the networks have the same PIs/POs/latches
if ( !Abc_NtkCompareSignals( pNtkLogic, pNtkLogicOrig, 1, 1 ) )
{
Abc_NtkDelete( pNtkOrig );
Abc_NtkDelete( pNtkLogicOrig );
return;
}
// convert the current logic network into an AIG
pMiter = Abc_NtkStrash( pNtkLogic, 1, 0, 0 );
// convert it into the AIG and make the netlist point to the AIG
Abc_NtkAppend( pMiter, pNtkLogicOrig, 1 );
Abc_NtkTransferCopy( pNtkOrig );
Abc_NtkDelete( pNtkLogicOrig );
if ( fVerbose )
{
printf( "After mitering:\n" );
printf( "Logic: Nodes = %5d. Copy = %5d. \n", Abc_NtkNodeNum(pNtkLogic), Abc_NtkCountCopy(pNtkLogic) );
printf( "Orig: Nodes = %5d. Copy = %5d. \n", Abc_NtkNodeNum(pNtkOrig), Abc_NtkCountCopy(pNtkOrig) );
}
// fraig the miter (miter nodes point to the fraiged miter)
pMiterFraig = Abc_NtkIvyFraig( pMiter, 100, 1, 0, 1, 0 );
// make netlists point to the fraiged miter
Abc_NtkTransferCopy( pNtkLogic );
Abc_NtkTransferCopy( pNtkOrig );
Abc_NtkDelete( pMiter );
if ( fVerbose )
{
printf( "After fraiging:\n" );
printf( "Logic: Nodes = %5d. Copy = %5d. \n", Abc_NtkNodeNum(pNtkLogic), Abc_NtkCountCopy(pNtkLogic) );
printf( "Orig: Nodes = %5d. Copy = %5d. \n", Abc_NtkNodeNum(pNtkOrig), Abc_NtkCountCopy(pNtkOrig) );
}
// derive mapping from the fraiged nodes into their prototype nodes in the original netlist
tMapping = Abc_NtkDressDeriveMapping( pNtkOrig );
// transfer the names to the new netlist
Abc_NtkDressTransferNames( pNtkLogic, tMapping, fVerbose );
// clean up
stmm_free_table( tMapping );
Abc_NtkDelete( pMiterFraig );
Abc_NtkDelete( pNtkOrig );
}
/**Function*************************************************************
Synopsis [Writes the graph structure of network for DOT.]
Description [Useful for graph visualization using tools such as GraphViz:
http://www.graphviz.org/]
SideEffects []
SeeAlso []
***********************************************************************/
void Io_WriteDotNtk( Abc_Ntk_t * pNtk, Vec_Ptr_t * vNodes, Vec_Ptr_t * vNodesShow, char * pFileName, int fGateNames, int fUseReverse )
{
FILE * pFile;
Abc_Obj_t * pNode, * pFanin;
char * pSopString;
int LevelMin, LevelMax, fHasCos, Level, i, k, fHasBdds, fCompl;
int Limit = 300;
assert( Abc_NtkIsStrash(pNtk) || Abc_NtkIsLogic(pNtk) );
if ( vNodes->nSize < 1 )
{
printf( "The set has no nodes. DOT file is not written.\n" );
return;
}
if ( vNodes->nSize > Limit )
{
printf( "The set has more than %d nodes. DOT file is not written.\n", Limit );
return;
}
// start the stream
if ( (pFile = fopen( pFileName, "w" )) == NULL )
{
fprintf( stdout, "Cannot open the intermediate file \"%s\".\n", pFileName );
return;
}
// transform logic functions from BDD to SOP
if ( fHasBdds = Abc_NtkIsBddLogic(pNtk) )
{
if ( !Abc_NtkBddToSop(pNtk, 0) )
{
printf( "Io_WriteDotNtk(): Converting to SOPs has failed.\n" );
return;
}
}
// mark the nodes from the set
Vec_PtrForEachEntry( vNodes, pNode, i )
pNode->fMarkC = 1;
if ( vNodesShow )
Vec_PtrForEachEntry( vNodesShow, pNode, i )
pNode->fMarkB = 1;
// get the levels of nodes
LevelMax = Abc_NtkLevel( pNtk );
if ( fUseReverse )
{
LevelMin = Abc_NtkLevelReverse( pNtk );
assert( LevelMax == LevelMin );
Vec_PtrForEachEntry( vNodes, pNode, i )
if ( Abc_ObjIsNode(pNode) )
pNode->Level = LevelMax - pNode->Level + 1;
}
// find the largest and the smallest levels
LevelMin = 10000;
LevelMax = -1;
fHasCos = 0;
Vec_PtrForEachEntry( vNodes, pNode, i )
{
if ( Abc_ObjIsCo(pNode) )
{
fHasCos = 1;
continue;
}
if ( LevelMin > (int)pNode->Level )
LevelMin = pNode->Level;
if ( LevelMax < (int)pNode->Level )
LevelMax = pNode->Level;
}
// set the level of the CO nodes
if ( fHasCos )
{
LevelMax++;
Vec_PtrForEachEntry( vNodes, pNode, i )
{
if ( Abc_ObjIsCo(pNode) )
pNode->Level = LevelMax;
}
}
// write the DOT header
fprintf( pFile, "# %s\n", "Network structure generated by ABC" );
fprintf( pFile, "\n" );
fprintf( pFile, "digraph network {\n" );
fprintf( pFile, "size = \"7.5,10\";\n" );
// fprintf( pFile, "size = \"10,8.5\";\n" );
// fprintf( pFile, "size = \"14,11\";\n" );
// fprintf( pFile, "page = \"8,11\";\n" );
// fprintf( pFile, "ranksep = 0.5;\n" );
// fprintf( pFile, "nodesep = 0.5;\n" );
fprintf( pFile, "center = true;\n" );
// fprintf( pFile, "orientation = landscape;\n" );
// fprintf( pFile, "edge [fontsize = 10];\n" );
// fprintf( pFile, "edge [dir = none];\n" );
fprintf( pFile, "edge [dir = back];\n" );
fprintf( pFile, "\n" );
// labels on the left of the picture
fprintf( pFile, "{\n" );
fprintf( pFile, " node [shape = plaintext];\n" );
fprintf( pFile, " edge [style = invis];\n" );
fprintf( pFile, " LevelTitle1 [label=\"\"];\n" );
fprintf( pFile, " LevelTitle2 [label=\"\"];\n" );
// generate node names with labels
for ( Level = LevelMax; Level >= LevelMin; Level-- )
{
// the visible node name
fprintf( pFile, " Level%d", Level );
fprintf( pFile, " [label = " );
// label name
fprintf( pFile, "\"" );
fprintf( pFile, "\"" );
fprintf( pFile, "];\n" );
}
// genetate the sequence of visible/invisible nodes to mark levels
fprintf( pFile, " LevelTitle1 -> LevelTitle2 ->" );
for ( Level = LevelMax; Level >= LevelMin; Level-- )
{
// the visible node name
fprintf( pFile, " Level%d", Level );
// the connector
if ( Level != LevelMin )
fprintf( pFile, " ->" );
else
fprintf( pFile, ";" );
}
fprintf( pFile, "\n" );
fprintf( pFile, "}" );
fprintf( pFile, "\n" );
fprintf( pFile, "\n" );
// generate title box on top
fprintf( pFile, "{\n" );
fprintf( pFile, " rank = same;\n" );
fprintf( pFile, " LevelTitle1;\n" );
fprintf( pFile, " title1 [shape=plaintext,\n" );
fprintf( pFile, " fontsize=20,\n" );
fprintf( pFile, " fontname = \"Times-Roman\",\n" );
fprintf( pFile, " label=\"" );
fprintf( pFile, "%s", "Network structure visualized by ABC" );
fprintf( pFile, "\\n" );
fprintf( pFile, "Benchmark \\\"%s\\\". ", pNtk->pName );
fprintf( pFile, "Time was %s. ", Extra_TimeStamp() );
fprintf( pFile, "\"\n" );
fprintf( pFile, " ];\n" );
fprintf( pFile, "}" );
fprintf( pFile, "\n" );
fprintf( pFile, "\n" );
// generate statistics box
fprintf( pFile, "{\n" );
fprintf( pFile, " rank = same;\n" );
fprintf( pFile, " LevelTitle2;\n" );
fprintf( pFile, " title2 [shape=plaintext,\n" );
fprintf( pFile, " fontsize=18,\n" );
fprintf( pFile, " fontname = \"Times-Roman\",\n" );
fprintf( pFile, " label=\"" );
if ( Abc_NtkObjNum(pNtk) == Vec_PtrSize(vNodes) )
fprintf( pFile, "The network contains %d logic nodes and %d latches.", Abc_NtkNodeNum(pNtk), Abc_NtkLatchNum(pNtk) );
else
fprintf( pFile, "The set contains %d logic nodes and spans %d levels.", Abc_NtkCountLogicNodes(vNodes), LevelMax - LevelMin + 1 );
fprintf( pFile, "\\n" );
fprintf( pFile, "\"\n" );
fprintf( pFile, " ];\n" );
fprintf( pFile, "}" );
fprintf( pFile, "\n" );
fprintf( pFile, "\n" );
// generate the POs
if ( fHasCos )
{
fprintf( pFile, "{\n" );
fprintf( pFile, " rank = same;\n" );
// the labeling node of this level
fprintf( pFile, " Level%d;\n", LevelMax );
// generate the PO nodes
Vec_PtrForEachEntry( vNodes, pNode, i )
{
if ( !Abc_ObjIsCo(pNode) )
continue;
fprintf( pFile, " Node%d [label = \"%s%s\"",
pNode->Id,
(Abc_ObjIsBi(pNode)? Abc_ObjName(Abc_ObjFanout0(pNode)):Abc_ObjName(pNode)),
(Abc_ObjIsBi(pNode)? "_in":"") );
fprintf( pFile, ", shape = %s", (Abc_ObjIsBi(pNode)? "box":"invtriangle") );
if ( pNode->fMarkB )
fprintf( pFile, ", style = filled" );
fprintf( pFile, ", color = coral, fillcolor = coral" );
fprintf( pFile, "];\n" );
}
fprintf( pFile, "}" );
fprintf( pFile, "\n" );
fprintf( pFile, "\n" );
}
// generate nodes of each rank
for ( Level = LevelMax - fHasCos; Level >= LevelMin && Level > 0; Level-- )
{
fprintf( pFile, "{\n" );
fprintf( pFile, " rank = same;\n" );
// the labeling node of this level
fprintf( pFile, " Level%d;\n", Level );
Vec_PtrForEachEntry( vNodes, pNode, i )
{
if ( (int)pNode->Level != Level )
continue;
if ( Abc_ObjFaninNum(pNode) == 0 )
continue;
// fprintf( pFile, " Node%d [label = \"%d\"", pNode->Id, pNode->Id );
if ( Abc_NtkIsStrash(pNtk) )
pSopString = "";
else if ( Abc_NtkHasMapping(pNtk) && fGateNames )
pSopString = Mio_GateReadName(pNode->pData);
else if ( Abc_NtkHasMapping(pNtk) )
pSopString = Abc_NtkPrintSop(Mio_GateReadSop(pNode->pData));
else
pSopString = Abc_NtkPrintSop(pNode->pData);
fprintf( pFile, " Node%d [label = \"%d\\n%s\"", pNode->Id, pNode->Id, pSopString );
fprintf( pFile, ", shape = ellipse" );
if ( pNode->fMarkB )
fprintf( pFile, ", style = filled" );
fprintf( pFile, "];\n" );
}
fprintf( pFile, "}" );
fprintf( pFile, "\n" );
fprintf( pFile, "\n" );
}
// generate the PI nodes if any
if ( LevelMin == 0 )
{
fprintf( pFile, "{\n" );
fprintf( pFile, " rank = same;\n" );
// the labeling node of this level
fprintf( pFile, " Level%d;\n", LevelMin );
// generate the PO nodes
Vec_PtrForEachEntry( vNodes, pNode, i )
{
if ( !Abc_ObjIsCi(pNode) )
{
// check if the costant node is present
if ( Abc_ObjFaninNum(pNode) == 0 && Abc_ObjFanoutNum(pNode) > 0 )
{
fprintf( pFile, " Node%d [label = \"Const%d\"", pNode->Id, Abc_NtkIsStrash(pNode->pNtk) || Abc_NodeIsConst1(pNode) );
fprintf( pFile, ", shape = ellipse" );
if ( pNode->fMarkB )
fprintf( pFile, ", style = filled" );
fprintf( pFile, ", color = coral, fillcolor = coral" );
fprintf( pFile, "];\n" );
}
continue;
}
fprintf( pFile, " Node%d [label = \"%s\"",
pNode->Id,
(Abc_ObjIsBo(pNode)? Abc_ObjName(Abc_ObjFanin0(pNode)):Abc_ObjName(pNode)) );
fprintf( pFile, ", shape = %s", (Abc_ObjIsBo(pNode)? "box":"triangle") );
if ( pNode->fMarkB )
fprintf( pFile, ", style = filled" );
fprintf( pFile, ", color = coral, fillcolor = coral" );
fprintf( pFile, "];\n" );
}
fprintf( pFile, "}" );
fprintf( pFile, "\n" );
fprintf( pFile, "\n" );
}
/**Function*************************************************************
Synopsis [Checks the integrity of the network.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
int Abc_NtkDoCheck( Abc_Ntk_t * pNtk )
{
Abc_Obj_t * pObj, * pNet, * pNode;
int i;
// check network types
if ( !Abc_NtkIsNetlist(pNtk) && !Abc_NtkIsLogic(pNtk) && !Abc_NtkIsStrash(pNtk) )
{
fprintf( stdout, "NetworkCheck: Unknown network type.\n" );
return 0;
}
if ( !Abc_NtkHasSop(pNtk) && !Abc_NtkHasBdd(pNtk) && !Abc_NtkHasAig(pNtk) && !Abc_NtkHasMapping(pNtk) && !Abc_NtkHasBlifMv(pNtk) && !Abc_NtkHasBlackbox(pNtk) )
{
fprintf( stdout, "NetworkCheck: Unknown functionality type.\n" );
return 0;
}
if ( Abc_NtkHasMapping(pNtk) )
{
if ( pNtk->pManFunc != Abc_FrameReadLibGen() )
{
fprintf( stdout, "NetworkCheck: The library of the mapped network is not the global library.\n" );
return 0;
}
}
if ( Abc_NtkHasOnlyLatchBoxes(pNtk) )
{
// check CI/CO numbers
if ( Abc_NtkPiNum(pNtk) + Abc_NtkLatchNum(pNtk) != Abc_NtkCiNum(pNtk) )
{
fprintf( stdout, "NetworkCheck: Number of CIs does not match number of PIs and latches.\n" );
fprintf( stdout, "One possible reason is that latches are added twice:\n" );
fprintf( stdout, "in procedure Abc_NtkCreateObj() and in the user's code.\n" );
return 0;
}
if ( Abc_NtkPoNum(pNtk) + Abc_NtkLatchNum(pNtk) != Abc_NtkCoNum(pNtk) )
{
fprintf( stdout, "NetworkCheck: Number of COs does not match number of POs, asserts, and latches.\n" );
fprintf( stdout, "One possible reason is that latches are added twice:\n" );
fprintf( stdout, "in procedure Abc_NtkCreateObj() and in the user's code.\n" );
return 0;
}
}
// check the names
if ( !Abc_NtkCheckNames( pNtk ) )
return 0;
// check PIs and POs
Abc_NtkCleanCopy( pNtk );
if ( !Abc_NtkCheckPis( pNtk ) )
return 0;
if ( !Abc_NtkCheckPos( pNtk ) )
return 0;
if ( Abc_NtkHasBlackbox(pNtk) )
return 1;
// check the connectivity of objects
Abc_NtkForEachObj( pNtk, pObj, i )
if ( !Abc_NtkCheckObj( pNtk, pObj ) )
return 0;
// if it is a netlist change nets and latches
if ( Abc_NtkIsNetlist(pNtk) )
{
if ( Abc_NtkNetNum(pNtk) == 0 )
fprintf( stdout, "NetworkCheck: Warning! Netlist has no nets.\n" );
// check the nets
Abc_NtkForEachNet( pNtk, pNet, i )
if ( !Abc_NtkCheckNet( pNtk, pNet ) )
return 0;
}
else
{
if ( Abc_NtkNetNum(pNtk) != 0 )
