Ejemplo n.º 1
0
#define WMT_PIN_UART2CTS	WMT_PIN(5, 26)
#define WMT_PIN_UART2RXD	WMT_PIN(5, 27)
#define WMT_PIN_UART3RTS	WMT_PIN(5, 28)
#define WMT_PIN_UART3TXD	WMT_PIN(5, 29)
#define WMT_PIN_UART3CTS	WMT_PIN(5, 30)
#define WMT_PIN_UART3RXD	WMT_PIN(5, 31)
#define WMT_PIN_KPADROW0	WMT_PIN(6, 16)
#define WMT_PIN_KPADROW1	WMT_PIN(6, 17)
#define WMT_PIN_KPADCOL0	WMT_PIN(6, 18)
#define WMT_PIN_KPADCOL1	WMT_PIN(6, 19)
#define WMT_PIN_SD1CLK		WMT_PIN(7, 0)
#define WMT_PIN_SD1CMD		WMT_PIN(7, 1)
#define WMT_PIN_SD1WP		WMT_PIN(7, 13)

static const struct pinctrl_pin_desc wm8650_pins[] = {
	PINCTRL_PIN(WMT_PIN_EXTGPIO0, "extgpio0"),
	PINCTRL_PIN(WMT_PIN_EXTGPIO1, "extgpio1"),
	PINCTRL_PIN(WMT_PIN_EXTGPIO2, "extgpio2"),
	PINCTRL_PIN(WMT_PIN_EXTGPIO3, "extgpio3"),
	PINCTRL_PIN(WMT_PIN_EXTGPIO4, "extgpio4"),
	PINCTRL_PIN(WMT_PIN_EXTGPIO5, "extgpio5"),
	PINCTRL_PIN(WMT_PIN_EXTGPIO6, "extgpio6"),
	PINCTRL_PIN(WMT_PIN_EXTGPIO7, "extgpio7"),
	PINCTRL_PIN(WMT_PIN_WAKEUP0, "wakeup0"),
	PINCTRL_PIN(WMT_PIN_WAKEUP1, "wakeup1"),
	PINCTRL_PIN(WMT_PIN_SUSGPIO0, "susgpio0"),
	PINCTRL_PIN(WMT_PIN_SD0CD, "sd0_cd"),
	PINCTRL_PIN(WMT_PIN_SD1CD, "sd1_cd"),
	PINCTRL_PIN(WMT_PIN_VDOUT0, "vdout0"),
	PINCTRL_PIN(WMT_PIN_VDOUT1, "vdout1"),
	PINCTRL_PIN(WMT_PIN_VDOUT2, "vdout2"),
Ejemplo n.º 2
0
 * edges of the silicon, finger by finger. LTCORNER upper left is pad 0.
 * Data taken from the PadRing chart, arranged like this:
 *
 *   0 ..... 104
 * 466        105
 *   .        .
 *   .        .
 * 358        224
 *  357 .... 225
 */
#define U300_NUM_PADS 467

/* Pad names for the pinmux subsystem */
static const struct pinctrl_pin_desc u300_pads[] = {
	/* Pads along the top edge of the chip */
	PINCTRL_PIN(0, "P PAD VDD 28"),
	PINCTRL_PIN(1, "P PAD GND 28"),
	PINCTRL_PIN(2, "PO SIM RST N"),
	PINCTRL_PIN(3, "VSSIO 25"),
	PINCTRL_PIN(4, "VSSA ADDA ESDSUB"),
	PINCTRL_PIN(5, "PWR VSSCOMMON"),
	PINCTRL_PIN(6, "PI ADC I1 POS"),
	PINCTRL_PIN(7, "PI ADC I1 NEG"),
	PINCTRL_PIN(8, "PWR VSSAD0"),
	PINCTRL_PIN(9, "PWR VCCAD0"),
	PINCTRL_PIN(10, "PI ADC Q1 NEG"),
	PINCTRL_PIN(11, "PI ADC Q1 POS"),
	PINCTRL_PIN(12, "PWR VDDAD"),
	PINCTRL_PIN(13, "PWR GNDAD"),
	PINCTRL_PIN(14, "PI ADC I2 POS"),
	PINCTRL_PIN(15, "PI ADC I2 NEG"),
Ejemplo n.º 3
0
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/pinctrl.h>

#include "pinctrl-msm.h"

static const struct pinctrl_pin_desc apq8064_pins[] = {
	PINCTRL_PIN(0, "GPIO_0"),
	PINCTRL_PIN(1, "GPIO_1"),
	PINCTRL_PIN(2, "GPIO_2"),
	PINCTRL_PIN(3, "GPIO_3"),
	PINCTRL_PIN(4, "GPIO_4"),
	PINCTRL_PIN(5, "GPIO_5"),
	PINCTRL_PIN(6, "GPIO_6"),
	PINCTRL_PIN(7, "GPIO_7"),
	PINCTRL_PIN(8, "GPIO_8"),
	PINCTRL_PIN(9, "GPIO_9"),
	PINCTRL_PIN(10, "GPIO_10"),
	PINCTRL_PIN(11, "GPIO_11"),
	PINCTRL_PIN(12, "GPIO_12"),
	PINCTRL_PIN(13, "GPIO_13"),
	PINCTRL_PIN(14, "GPIO_14"),
	PINCTRL_PIN(15, "GPIO_15"),
Ejemplo n.º 4
0
#define BXT_GPI_IE	0x110

#define BXT_COMMUNITY(s, e)				\
	{						\
		.padown_offset = BXT_PAD_OWN,		\
		.padcfglock_offset = BXT_PADCFGLOCK,	\
		.hostown_offset = BXT_HOSTSW_OWN,	\
		.ie_offset = BXT_GPI_IE,		\
		.gpp_size = 32,                         \
		.pin_base = (s),			\
		.npins = ((e) - (s) + 1),		\
	}

/* BXT */
static const struct pinctrl_pin_desc bxt_north_pins[] = {
	PINCTRL_PIN(0, "GPIO_0"),
	PINCTRL_PIN(1, "GPIO_1"),
	PINCTRL_PIN(2, "GPIO_2"),
	PINCTRL_PIN(3, "GPIO_3"),
	PINCTRL_PIN(4, "GPIO_4"),
	PINCTRL_PIN(5, "GPIO_5"),
	PINCTRL_PIN(6, "GPIO_6"),
	PINCTRL_PIN(7, "GPIO_7"),
	PINCTRL_PIN(8, "GPIO_8"),
	PINCTRL_PIN(9, "GPIO_9"),
	PINCTRL_PIN(10, "GPIO_10"),
	PINCTRL_PIN(11, "GPIO_11"),
	PINCTRL_PIN(12, "GPIO_12"),
	PINCTRL_PIN(13, "GPIO_13"),
	PINCTRL_PIN(14, "GPIO_14"),
	PINCTRL_PIN(15, "GPIO_15"),
Ejemplo n.º 5
0
static const struct of_device_id omap_rtc_of_match[] = {
	{
		.compatible	= "ti,am3352-rtc",
		.data		= &omap_rtc_am3352_type,
	}, {
		.compatible	= "ti,da830-rtc",
		.data		= &omap_rtc_da830_type,
	}, {
		/* sentinel */
	}
};
MODULE_DEVICE_TABLE(of, omap_rtc_of_match);

static const struct pinctrl_pin_desc rtc_pins_desc[] = {
	PINCTRL_PIN(0, "ext_wakeup0"),
	PINCTRL_PIN(1, "ext_wakeup1"),
	PINCTRL_PIN(2, "ext_wakeup2"),
	PINCTRL_PIN(3, "ext_wakeup3"),
};

static int rtc_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
{
	return 0;
}

static const char *rtc_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
					unsigned int group)
{
	return NULL;
}
Ejemplo n.º 6
0
	PXA168_MUX_SSP3,
	PXA168_MUX_SSP3_TX,
	PXA168_MUX_SSP4,
	PXA168_MUX_SSP4_TX,
	PXA168_MUX_SSP5,
	PXA168_MUX_SSP5_TX,
	PXA168_MUX_USB,
	PXA168_MUX_JTAG,
	PXA168_MUX_RESET,
	PXA168_MUX_WAKEUP,
	PXA168_MUX_EXT_32K_IN,
	PXA168_MUX_NONE = 0xffff,
};

static struct pinctrl_pin_desc pxa168_pads[] = {
	PINCTRL_PIN(GPIO0, "GPIO0"),
	PINCTRL_PIN(GPIO1, "GPIO1"),
	PINCTRL_PIN(GPIO2, "GPIO2"),
	PINCTRL_PIN(GPIO3, "GPIO3"),
	PINCTRL_PIN(GPIO4, "GPIO4"),
	PINCTRL_PIN(GPIO5, "GPIO5"),
	PINCTRL_PIN(GPIO6, "GPIO6"),
	PINCTRL_PIN(GPIO7, "GPIO7"),
	PINCTRL_PIN(GPIO8, "GPIO8"),
	PINCTRL_PIN(GPIO9, "GPIO9"),
	PINCTRL_PIN(GPIO10, "GPIO10"),
	PINCTRL_PIN(GPIO11, "GPIO11"),
	PINCTRL_PIN(GPIO12, "GPIO12"),
	PINCTRL_PIN(GPIO13, "GPIO13"),
	PINCTRL_PIN(GPIO14, "GPIO14"),
	PINCTRL_PIN(GPIO15, "GPIO15"),
Ejemplo n.º 7
0
	ZYNQ_PMUX_smc0_nor,
	ZYNQ_PMUX_smc0_nor_cs1,
	ZYNQ_PMUX_smc0_nor_addr25,
	ZYNQ_PMUX_smc0_nand,
	ZYNQ_PMUX_ttc0,
	ZYNQ_PMUX_ttc1,
	ZYNQ_PMUX_uart0,
	ZYNQ_PMUX_uart1,
	ZYNQ_PMUX_usb0,
	ZYNQ_PMUX_usb1,
	ZYNQ_PMUX_swdt0,
	ZYNQ_PMUX_MAX_FUNC
};

static const struct pinctrl_pin_desc zynq_pins[] = {
	PINCTRL_PIN(0,  "MIO0"),
	PINCTRL_PIN(1,  "MIO1"),
	PINCTRL_PIN(2,  "MIO2"),
	PINCTRL_PIN(3,  "MIO3"),
	PINCTRL_PIN(4,  "MIO4"),
	PINCTRL_PIN(5,  "MIO5"),
	PINCTRL_PIN(6,  "MIO6"),
	PINCTRL_PIN(7,  "MIO7"),
	PINCTRL_PIN(8,  "MIO8"),
	PINCTRL_PIN(9,  "MIO9"),
	PINCTRL_PIN(10, "MIO10"),
	PINCTRL_PIN(11, "MIO11"),
	PINCTRL_PIN(12, "MIO12"),
	PINCTRL_PIN(13, "MIO13"),
	PINCTRL_PIN(14, "MIO14"),
	PINCTRL_PIN(15, "MIO15"),
/*
 * Pinctrl Driver for ADI GPIO2 controller
 *
 * Copyright 2007-2013 Analog Devices Inc.
 *
 * Licensed under the GPLv2 or later
 */

#include <asm/portmux.h>
#include "pinctrl-adi2.h"

static const struct pinctrl_pin_desc adi_pads[] = {
	PINCTRL_PIN(0, "PA0"),
	PINCTRL_PIN(1, "PA1"),
	PINCTRL_PIN(2, "PA2"),
	PINCTRL_PIN(3, "PG3"),
	PINCTRL_PIN(4, "PA4"),
	PINCTRL_PIN(5, "PA5"),
	PINCTRL_PIN(6, "PA6"),
	PINCTRL_PIN(7, "PA7"),
	PINCTRL_PIN(8, "PA8"),
	PINCTRL_PIN(9, "PA9"),
	PINCTRL_PIN(10, "PA10"),
	PINCTRL_PIN(11, "PA11"),
	PINCTRL_PIN(12, "PA12"),
	PINCTRL_PIN(13, "PA13"),
	PINCTRL_PIN(14, "PA14"),
	PINCTRL_PIN(15, "PA15"),
	PINCTRL_PIN(16, "PB0"),
	PINCTRL_PIN(17, "PB1"),
	PINCTRL_PIN(18, "PB2"),
Ejemplo n.º 9
0
#define AB9540_PIN_G12		ABX500_GPIO(51)
#define AB9540_PIN_E17		ABX500_GPIO(52)
#define AB9540_PIN_D11		ABX500_GPIO(53)
#define AB9540_PIN_M18		ABX500_GPIO(54)

/* indicates the highest GPIO number */
#define AB9540_GPIO_MAX_NUMBER	54

/*
 * The names of the pins are denoted by GPIO number and ball name, even
 * though they can be used for other things than GPIO, this is the first
 * column in the table of the data sheet and often used on schematics and
 * such.
 */
static const struct pinctrl_pin_desc ab9540_pins[] = {
	PINCTRL_PIN(AB9540_PIN_R4, "GPIO1_R4"),
	PINCTRL_PIN(AB9540_PIN_V3, "GPIO2_V3"),
	PINCTRL_PIN(AB9540_PIN_T4, "GPIO3_T4"),
	PINCTRL_PIN(AB9540_PIN_T5, "GPIO4_T5"),
	/* hole */
	PINCTRL_PIN(AB9540_PIN_B18, "GPIO10_B18"),
	PINCTRL_PIN(AB9540_PIN_C18, "GPIO11_C18"),
	/* hole */
	PINCTRL_PIN(AB9540_PIN_D18, "GPIO13_D18"),
	PINCTRL_PIN(AB9540_PIN_B19, "GPIO14_B19"),
	PINCTRL_PIN(AB9540_PIN_C19, "GPIO15_C19"),
	PINCTRL_PIN(AB9540_PIN_D19, "GPIO16_D19"),
	PINCTRL_PIN(AB9540_PIN_R3, "GPIO17_R3"),
	PINCTRL_PIN(AB9540_PIN_T2, "GPIO18_T2"),
	PINCTRL_PIN(AB9540_PIN_U2, "GPIO19_U2"),
	PINCTRL_PIN(AB9540_PIN_V2, "GPIO20_V2"),
Ejemplo n.º 10
0
{
	P_PERIPHS_PIN_MUX_0,
	P_PERIPHS_PIN_MUX_1,
	P_PERIPHS_PIN_MUX_2,
	P_PERIPHS_PIN_MUX_3,
	P_PERIPHS_PIN_MUX_4,
	P_PERIPHS_PIN_MUX_5,
	P_PERIPHS_PIN_MUX_6,
	P_PERIPHS_PIN_MUX_7,
	P_PERIPHS_PIN_MUX_8,
	P_PERIPHS_PIN_MUX_9,
	P_AO_RTI_PIN_MUX_REG,
};
/* Pad names for the pinmux subsystem */
const static struct pinctrl_pin_desc amlogic_pads[] = {
	PINCTRL_PIN(GPIOY_0,"GPIOY_0"),
	PINCTRL_PIN(GPIOY_1,"GPIOY_1"),
	PINCTRL_PIN(GPIOY_2,"GPIOY_2"),
	PINCTRL_PIN(GPIOY_3,"GPIOY_3"),
	PINCTRL_PIN(GPIOY_4,"GPIOY_4"),
	PINCTRL_PIN(GPIOY_5,"GPIOY_5"),
	PINCTRL_PIN(GPIOY_6,"GPIOY_6"),
	PINCTRL_PIN(GPIOY_7,"GPIOY_7"),
	PINCTRL_PIN(GPIOY_8,"GPIOY_8"),
	PINCTRL_PIN(GPIOY_9,"GPIOY_9"),
	PINCTRL_PIN(GPIOY_10,"GPIOY_10"),
	PINCTRL_PIN(GPIOY_11,"GPIOY_11"),
	PINCTRL_PIN(GPIOY_12,"GPIOY_12"),
	PINCTRL_PIN(GPIOY_13,"GPIOY_13"),
	PINCTRL_PIN(GPIOY_14,"GPIOY_14"),
	PINCTRL_PIN(GPIOY_15,"GPIOY_15"),
Ejemplo n.º 11
0
#define DNV_COMMUNITY(b, s, e, g)			\
	{						\
		.barno = (b),				\
		.padown_offset = DNV_PAD_OWN,		\
		.padcfglock_offset = DNV_PADCFGLOCK,	\
		.hostown_offset = DNV_HOSTSW_OWN,	\
		.ie_offset = DNV_GPI_IE,		\
		.pin_base = (s),			\
		.npins = ((e) - (s) + 1),		\
		.gpps = (g),				\
		.ngpps = ARRAY_SIZE(g),			\
	}

static const struct pinctrl_pin_desc dnv_pins[] = {
	/* North ALL */
	PINCTRL_PIN(0, "GBE0_SDP0"),
	PINCTRL_PIN(1, "GBE1_SDP0"),
	PINCTRL_PIN(2, "GBE0_SDP1"),
	PINCTRL_PIN(3, "GBE1_SDP1"),
	PINCTRL_PIN(4, "GBE0_SDP2"),
	PINCTRL_PIN(5, "GBE1_SDP2"),
	PINCTRL_PIN(6, "GBE0_SDP3"),
	PINCTRL_PIN(7, "GBE1_SDP3"),
	PINCTRL_PIN(8, "GBE2_LED0"),
	PINCTRL_PIN(9, "GBE2_LED1"),
	PINCTRL_PIN(10, "GBE0_I2C_CLK"),
	PINCTRL_PIN(11, "GBE0_I2C_DATA"),
	PINCTRL_PIN(12, "GBE1_I2C_CLK"),
	PINCTRL_PIN(13, "GBE1_I2C_DATA"),
	PINCTRL_PIN(14, "NCSI_RXD0"),
	PINCTRL_PIN(15, "NCSI_CLK_IN"),
Ejemplo n.º 12
0
#define AB8505_PIN_L4		ABX500_GPIO(50)
/* hole */
#define AB8505_PIN_D16		ABX500_GPIO(52)
#define AB8505_PIN_D15		ABX500_GPIO(53)

/* indicates the higher GPIO number */
#define AB8505_GPIO_MAX_NUMBER	53

/*
 * The names of the pins are denoted by GPIO number and ball name, even
 * though they can be used for other things than GPIO, this is the first
 * column in the table of the data sheet and often used on schematics and
 * such.
 */
static const struct pinctrl_pin_desc ab8505_pins[] = {
	PINCTRL_PIN(AB8505_PIN_N4, "GPIO1_N4"),
	PINCTRL_PIN(AB8505_PIN_R5, "GPIO2_R5"),
	PINCTRL_PIN(AB8505_PIN_P5, "GPIO3_P5"),
/* hole */
	PINCTRL_PIN(AB8505_PIN_B16, "GPIO10_B16"),
	PINCTRL_PIN(AB8505_PIN_B17, "GPIO11_B17"),
/* hole */
	PINCTRL_PIN(AB8505_PIN_D17, "GPIO13_D17"),
	PINCTRL_PIN(AB8505_PIN_C16, "GPIO14_C16"),
/* hole */
	PINCTRL_PIN(AB8505_PIN_P2, "GPIO17_P2"),
	PINCTRL_PIN(AB8505_PIN_N3, "GPIO18_N3"),
	PINCTRL_PIN(AB8505_PIN_T1, "GPIO19_T1"),
	PINCTRL_PIN(AB8505_PIN_P3, "GPIO20_P3"),
/* hole */
	PINCTRL_PIN(AB8505_PIN_H14, "GPIO34_H14"),
Ejemplo n.º 13
0
/* All non-GPIO pins follow */
#define NUM_GPIOS				(TEGRA_PIN_SDMMC3_CLK_LB_IN_PEE5 + 1)
#define _PIN(offset)				(NUM_GPIOS + (offset))

/* Non-GPIO pins */
#define TEGRA_PIN_CORE_PWR_REQ			_PIN(0)
#define TEGRA_PIN_CPU_PWR_REQ			_PIN(1)
#define TEGRA_PIN_PWR_INT_N			_PIN(2)
#define TEGRA_PIN_RESET_OUT_N			_PIN(3)
#define TEGRA_PIN_OWR				_PIN(4)
#define TEGRA_PIN_JTAG_RTCK			_PIN(5)
#define TEGRA_PIN_CLK_32K_IN			_PIN(6)
#define TEGRA_PIN_GMI_CLK_LB			_PIN(7)

static const struct pinctrl_pin_desc tegra114_pins[] = {
	PINCTRL_PIN(TEGRA_PIN_CLK_32K_OUT_PA0, "CLK_32K_OUT PA0"),
	PINCTRL_PIN(TEGRA_PIN_UART3_CTS_N_PA1, "UART3_CTS_N PA1"),
	PINCTRL_PIN(TEGRA_PIN_DAP2_FS_PA2, "DAP2_FS PA2"),
	PINCTRL_PIN(TEGRA_PIN_DAP2_SCLK_PA3, "DAP2_SCLK PA3"),
	PINCTRL_PIN(TEGRA_PIN_DAP2_DIN_PA4, "DAP2_DIN PA4"),
	PINCTRL_PIN(TEGRA_PIN_DAP2_DOUT_PA5, "DAP2_DOUT PA5"),
	PINCTRL_PIN(TEGRA_PIN_SDMMC3_CLK_PA6, "SDMMC3_CLK PA6"),
	PINCTRL_PIN(TEGRA_PIN_SDMMC3_CMD_PA7, "SDMMC3_CMD PA7"),
	PINCTRL_PIN(TEGRA_PIN_GMI_A17_PB0, "GMI_A17 PB0"),
	PINCTRL_PIN(TEGRA_PIN_GMI_A18_PB1, "GMI_A18 PB1"),
	PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT3_PB4, "SDMMC3_DAT3 PB4"),
	PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT2_PB5, "SDMMC3_DAT2 PB5"),
	PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT1_PB6, "SDMMC3_DAT1 PB6"),
	PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT0_PB7, "SDMMC3_DAT0 PB7"),
	PINCTRL_PIN(TEGRA_PIN_UART3_RTS_N_PC0, "UART3_RTS_N PC0"),
	PINCTRL_PIN(TEGRA_PIN_UART2_TXD_PC2, "UART2_TXD PC2"),
Ejemplo n.º 14
0
#define TB10X_PORT3 (32)
#define TB10X_PORT4 (48)
#define TB10X_PORT5 (128)
#define TB10X_PORT6 (64)
#define TB10X_PORT7 (80)
#define TB10X_PORT8 (96)
#define TB10X_PORT9 (112)
#define TB10X_GPIOS (256)

#define PCFG_PORT_BITWIDTH (2)
#define PCFG_PORT_MASK(PORT) \
	(((1 << PCFG_PORT_BITWIDTH) - 1) << (PCFG_PORT_BITWIDTH * (PORT)))

static const struct pinctrl_pin_desc tb10x_pins[] = {
	/* Port 1 */
	PINCTRL_PIN(TB10X_PORT1 +  0, "MICLK_S0"),
	PINCTRL_PIN(TB10X_PORT1 +  1, "MISTRT_S0"),
	PINCTRL_PIN(TB10X_PORT1 +  2, "MIVAL_S0"),
	PINCTRL_PIN(TB10X_PORT1 +  3, "MDI_S0"),
	PINCTRL_PIN(TB10X_PORT1 +  4, "GPIOA0"),
	PINCTRL_PIN(TB10X_PORT1 +  5, "GPIOA1"),
	PINCTRL_PIN(TB10X_PORT1 +  6, "GPIOA2"),
	PINCTRL_PIN(TB10X_PORT1 +  7, "MDI_S1"),
	PINCTRL_PIN(TB10X_PORT1 +  8, "MIVAL_S1"),
	PINCTRL_PIN(TB10X_PORT1 +  9, "MISTRT_S1"),
	PINCTRL_PIN(TB10X_PORT1 + 10, "MICLK_S1"),
	/* Port 2 */
	PINCTRL_PIN(TB10X_PORT2 +  0, "MICLK_S2"),
	PINCTRL_PIN(TB10X_PORT2 +  1, "MISTRT_S2"),
	PINCTRL_PIN(TB10X_PORT2 +  2, "MIVAL_S2"),
	PINCTRL_PIN(TB10X_PORT2 +  3, "MDI_S2"),
Ejemplo n.º 15
0
#define LBG_COMMUNITY(b, s, e)				\
	{						\
		.barno = (b),				\
		.padown_offset = LBG_PAD_OWN,		\
		.padcfglock_offset = LBG_PADCFGLOCK,	\
		.hostown_offset = LBG_HOSTSW_OWN,	\
		.ie_offset = LBG_GPI_IE,		\
		.gpp_size = 24,				\
		.pin_base = (s),			\
		.npins = ((e) - (s) + 1),		\
	}

static const struct pinctrl_pin_desc lbg_pins[] = {
	/* GPP_A */
	PINCTRL_PIN(0, "RCINB"),
	PINCTRL_PIN(1, "LAD_0"),
	PINCTRL_PIN(2, "LAD_1"),
	PINCTRL_PIN(3, "LAD_2"),
	PINCTRL_PIN(4, "LAD_3"),
	PINCTRL_PIN(5, "LFRAMEB"),
	PINCTRL_PIN(6, "SERIRQ"),
	PINCTRL_PIN(7, "PIRQAB"),
	PINCTRL_PIN(8, "CLKRUNB"),
	PINCTRL_PIN(9, "CLKOUT_LPC_0"),
	PINCTRL_PIN(10, "CLKOUT_LPC_1"),
	PINCTRL_PIN(11, "PMEB"),
	PINCTRL_PIN(12, "BM_BUSYB"),
	PINCTRL_PIN(13, "SUSWARNB_SUSPWRDNACK"),
	PINCTRL_PIN(14, "ESPI_RESETB"),
	PINCTRL_PIN(15, "SUSACKB"),
Ejemplo n.º 16
0
		.barno = (b),				\
		.padown_offset = CDF_PAD_OWN,		\
		.padcfglock_offset = CDF_PADCFGLOCK,	\
		.hostown_offset = CDF_HOSTSW_OWN,	\
		.is_offset = CDF_GPI_IS,		\
		.ie_offset = CDF_GPI_IE,		\
		.pin_base = (s),			\
		.npins = ((e) - (s) + 1),		\
		.gpps = (g),				\
		.ngpps = ARRAY_SIZE(g),			\
	}

/* Cedar Fork PCH */
static const struct pinctrl_pin_desc cdf_pins[] = {
	/* WEST2 */
	PINCTRL_PIN(0, "GBE_SDP_TIMESYNC0_S2N"),
	PINCTRL_PIN(1, "GBE_SDP_TIMESYNC1_S2N"),
	PINCTRL_PIN(2, "GBE_SDP_TIMESYNC2_S2N"),
	PINCTRL_PIN(3, "GBE_SDP_TIMESYNC3_S2N"),
	PINCTRL_PIN(4, "GBE0_I2C_CLK"),
	PINCTRL_PIN(5, "GBE0_I2C_DATA"),
	PINCTRL_PIN(6, "GBE1_I2C_CLK"),
	PINCTRL_PIN(7, "GBE1_I2C_DATA"),
	PINCTRL_PIN(8, "GBE2_I2C_CLK"),
	PINCTRL_PIN(9, "GBE2_I2C_DATA"),
	PINCTRL_PIN(10, "GBE3_I2C_CLK"),
	PINCTRL_PIN(11, "GBE3_I2C_DATA"),
	PINCTRL_PIN(12, "GBE0_LED0"),
	PINCTRL_PIN(13, "GBE0_LED1"),
	PINCTRL_PIN(14, "GBE0_LED2"),
	PINCTRL_PIN(15, "GBE1_LED0"),
Ejemplo n.º 17
0
	{						\
		.barno = (b),				\
		.padown_offset = ICL_PAD_OWN,		\
		.padcfglock_offset = ICL_PADCFGLOCK,	\
		.hostown_offset = ICL_HOSTSW_OWN,	\
		.ie_offset = ICL_GPI_IE,		\
		.pin_base = (s),			\
		.npins = ((e) - (s) + 1),		\
		.gpps = (g),				\
		.ngpps = ARRAY_SIZE(g),			\
	}

/* Ice Lake-LP */
static const struct pinctrl_pin_desc icllp_pins[] = {
	/* GPP_G */
	PINCTRL_PIN(0, "SD3_CMD"),
	PINCTRL_PIN(1, "SD3_D0"),
	PINCTRL_PIN(2, "SD3_D1"),
	PINCTRL_PIN(3, "SD3_D2"),
	PINCTRL_PIN(4, "SD3_D3"),
	PINCTRL_PIN(5, "SD3_CDB"),
	PINCTRL_PIN(6, "SD3_CLK"),
	PINCTRL_PIN(7, "SD3_WP"),
	/* GPP_B */
	PINCTRL_PIN(8, "CORE_VID_0"),
	PINCTRL_PIN(9, "CORE_VID_1"),
	PINCTRL_PIN(10, "VRALERTB"),
	PINCTRL_PIN(11, "CPU_GP_2"),
	PINCTRL_PIN(12, "CPU_GP_3"),
	PINCTRL_PIN(13, "ISH_I2C0_SDA"),
	PINCTRL_PIN(14, "ISH_I2C0_SCL"),
Ejemplo n.º 18
0
 */

#include <linux/err.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include "pinctrl-spear.h"

#define DRIVER_NAME "spear1340-pinmux"

/* pins */
static const struct pinctrl_pin_desc spear1340_pins[] = {
	SPEAR_PIN_0_TO_101,
	SPEAR_PIN_102_TO_245,
	PINCTRL_PIN(246, "PLGPIO246"),
	PINCTRL_PIN(247, "PLGPIO247"),
	PINCTRL_PIN(248, "PLGPIO248"),
	PINCTRL_PIN(249, "PLGPIO249"),
	PINCTRL_PIN(250, "PLGPIO250"),
	PINCTRL_PIN(251, "PLGPIO251"),
};

/* In SPEAr1340 there are two levels of pad muxing */
/* - pads as gpio OR peripherals */
#define PAD_FUNCTION_EN_1			0x668
#define PAD_FUNCTION_EN_2			0x66C
#define PAD_FUNCTION_EN_3			0x670
#define PAD_FUNCTION_EN_4			0x674
#define PAD_FUNCTION_EN_5			0x690
#define PAD_FUNCTION_EN_6			0x694
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
#include <linux/of_platform.h>
#include <linux/bitops.h>

#define DRIVER_NAME "pinmux-sirf"

#define SIRFSOC_NUM_PADS    622
#define SIRFSOC_GPIO_PAD_EN(g) ((g)*0x100 + 0x84)
#define SIRFSOC_RSC_PIN_MUX 0x4

static const struct pinctrl_pin_desc sirfsoc_pads[] = {
	PINCTRL_PIN(4, "pwm0"),
	PINCTRL_PIN(5, "pwm1"),
	PINCTRL_PIN(6, "pwm2"),
	PINCTRL_PIN(7, "pwm3"),
	PINCTRL_PIN(8, "warm_rst_b"),
	PINCTRL_PIN(9, "odo_0"),
	PINCTRL_PIN(10, "odo_1"),
	PINCTRL_PIN(11, "dr_dir"),
	PINCTRL_PIN(13, "scl_1"),
	PINCTRL_PIN(15, "sda_1"),
	PINCTRL_PIN(16, "x_ldd[16]"),
	PINCTRL_PIN(17, "x_ldd[17]"),
	PINCTRL_PIN(18, "x_ldd[18]"),
	PINCTRL_PIN(19, "x_ldd[19]"),
	PINCTRL_PIN(20, "x_ldd[20]"),
	PINCTRL_PIN(21, "x_ldd[21]"),
Ejemplo n.º 20
0
		.pin_base = (s),			\
		.npins = (e) - (s) + 1,			\
	}

#define MRFLD_FAMILY_PROTECTED(b, s, e)			\
	{						\
		.barno = (b),				\
		.pin_base = (s),			\
		.npins = (e) - (s) + 1,			\
		.protected = true,			\
	}

static const struct pinctrl_pin_desc mrfld_pins[] = {
	/* Family 0: OCP2SSC (0 pins) */
	/* Family 1: ULPI (13 pins) */
	PINCTRL_PIN(0, "ULPI_CLK"),
	PINCTRL_PIN(1, "ULPI_D0"),
	PINCTRL_PIN(2, "ULPI_D1"),
	PINCTRL_PIN(3, "ULPI_D2"),
	PINCTRL_PIN(4, "ULPI_D3"),
	PINCTRL_PIN(5, "ULPI_D4"),
	PINCTRL_PIN(6, "ULPI_D5"),
	PINCTRL_PIN(7, "ULPI_D6"),
	PINCTRL_PIN(8, "ULPI_D7"),
	PINCTRL_PIN(9, "ULPI_DIR"),
	PINCTRL_PIN(10, "ULPI_NXT"),
	PINCTRL_PIN(11, "ULPI_REFCLK"),
	PINCTRL_PIN(12, "ULPI_STP"),
	/* Family 2: eMMC (24 pins) */
	PINCTRL_PIN(13, "EMMC_CLK"),
	PINCTRL_PIN(14, "EMMC_CMD"),
Ejemplo n.º 21
0
#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinconf-generic.h>

#include <linux/mfd/madera/core.h>
#include <linux/mfd/madera/registers.h>

#include "../pinctrl-utils.h"

#include "pinctrl-madera.h"

/*
 * Use pin GPIO names for consistency
 * NOTE: IDs are zero-indexed for coding convenience
 */
static const struct pinctrl_pin_desc madera_pins[] = {
	PINCTRL_PIN(0, "gpio1"),
	PINCTRL_PIN(1, "gpio2"),
	PINCTRL_PIN(2, "gpio3"),
	PINCTRL_PIN(3, "gpio4"),
	PINCTRL_PIN(4, "gpio5"),
	PINCTRL_PIN(5, "gpio6"),
	PINCTRL_PIN(6, "gpio7"),
	PINCTRL_PIN(7, "gpio8"),
	PINCTRL_PIN(8, "gpio9"),
	PINCTRL_PIN(9, "gpio10"),
	PINCTRL_PIN(10, "gpio11"),
	PINCTRL_PIN(11, "gpio12"),
	PINCTRL_PIN(12, "gpio13"),
	PINCTRL_PIN(13, "gpio14"),
	PINCTRL_PIN(14, "gpio15"),
	PINCTRL_PIN(15, "gpio16"),
Ejemplo n.º 22
0
#define DB8500_PIN_AD26		_GPIO(261)
#define DB8500_PIN_AE26		_GPIO(262)
#define DB8500_PIN_AG29		_GPIO(263)
#define DB8500_PIN_AE27		_GPIO(264)
#define DB8500_PIN_AD27		_GPIO(265)
#define DB8500_PIN_AC28		_GPIO(266)
#define DB8500_PIN_AC27		_GPIO(267)

/*
 * The names of the pins are denoted by GPIO number and ball name, even
 * though they can be used for other things than GPIO, this is the first
 * column in the table of the data sheet and often used on schematics and
 * such.
 */
static const struct pinctrl_pin_desc nmk_db8500_pins[] = {
	PINCTRL_PIN(DB8500_PIN_AJ5, "GPIO0_AJ5"),
	PINCTRL_PIN(DB8500_PIN_AJ3, "GPIO1_AJ3"),
	PINCTRL_PIN(DB8500_PIN_AH4, "GPIO2_AH4"),
	PINCTRL_PIN(DB8500_PIN_AH3, "GPIO3_AH3"),
	PINCTRL_PIN(DB8500_PIN_AH6, "GPIO4_AH6"),
	PINCTRL_PIN(DB8500_PIN_AG6, "GPIO5_AG6"),
	PINCTRL_PIN(DB8500_PIN_AF6, "GPIO6_AF6"),
	PINCTRL_PIN(DB8500_PIN_AG5, "GPIO7_AG5"),
	PINCTRL_PIN(DB8500_PIN_AD5, "GPIO8_AD5"),
	PINCTRL_PIN(DB8500_PIN_AE4, "GPIO9_AE4"),
	PINCTRL_PIN(DB8500_PIN_AF5, "GPIO10_AF5"),
	PINCTRL_PIN(DB8500_PIN_AG4, "GPIO11_AG4"),
	PINCTRL_PIN(DB8500_PIN_AC4, "GPIO12_AC4"),
	PINCTRL_PIN(DB8500_PIN_AF3, "GPIO13_AF3"),
	PINCTRL_PIN(DB8500_PIN_AE3, "GPIO14_AE3"),
	PINCTRL_PIN(DB8500_PIN_AC3, "GPIO15_AC3"),
Ejemplo n.º 23
0
#define WMT_PIN_SD2DATA2	WMT_PIN(6, 5)
#define WMT_PIN_SD2CMD		WMT_PIN(6, 6)
#define WMT_PIN_SD2CLK		WMT_PIN(6, 7)
#define WMT_PIN_SD2PWR		WMT_PIN(6, 9)
#define WMT_PIN_SD1CLK		WMT_PIN(7, 0)
#define WMT_PIN_SD1CMD		WMT_PIN(7, 1)
#define WMT_PIN_SD1PWR		WMT_PIN(7, 10)
#define WMT_PIN_SD1WP		WMT_PIN(7, 11)
#define WMT_PIN_SD1CD		WMT_PIN(7, 12)
#define WMT_PIN_SPI0SS3		WMT_PIN(7, 24)
#define WMT_PIN_SPI0SS2		WMT_PIN(7, 25)
#define WMT_PIN_PWMOUT1		WMT_PIN(7, 26)
#define WMT_PIN_PWMOUT0		WMT_PIN(7, 27)

static const struct pinctrl_pin_desc wm8750_pins[] = {
	PINCTRL_PIN(WMT_PIN_EXTGPIO0, "extgpio0"),
	PINCTRL_PIN(WMT_PIN_EXTGPIO1, "extgpio1"),
	PINCTRL_PIN(WMT_PIN_EXTGPIO2, "extgpio2"),
	PINCTRL_PIN(WMT_PIN_EXTGPIO3, "extgpio3"),
	PINCTRL_PIN(WMT_PIN_EXTGPIO4, "extgpio4"),
	PINCTRL_PIN(WMT_PIN_EXTGPIO5, "extgpio5"),
	PINCTRL_PIN(WMT_PIN_EXTGPIO6, "extgpio6"),
	PINCTRL_PIN(WMT_PIN_EXTGPIO7, "extgpio7"),
	PINCTRL_PIN(WMT_PIN_WAKEUP0, "wakeup0"),
	PINCTRL_PIN(WMT_PIN_WAKEUP1, "wakeup1"),
	PINCTRL_PIN(WMT_PIN_SD0CD, "sd0_cd"),
	PINCTRL_PIN(WMT_PIN_VDOUT0, "vdout0"),
	PINCTRL_PIN(WMT_PIN_VDOUT1, "vdout1"),
	PINCTRL_PIN(WMT_PIN_VDOUT2, "vdout2"),
	PINCTRL_PIN(WMT_PIN_VDOUT3, "vdout3"),
	PINCTRL_PIN(WMT_PIN_VDOUT4, "vdout4"),
Ejemplo n.º 24
0
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 */

#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/pinctrl.h>

#include "pinctrl-msm.h"

static const struct pinctrl_pin_desc ipq8064_pins[] = {
	PINCTRL_PIN(0, "GPIO_0"),
	PINCTRL_PIN(1, "GPIO_1"),
	PINCTRL_PIN(2, "GPIO_2"),
	PINCTRL_PIN(3, "GPIO_3"),
	PINCTRL_PIN(4, "GPIO_4"),
	PINCTRL_PIN(5, "GPIO_5"),
	PINCTRL_PIN(6, "GPIO_6"),
	PINCTRL_PIN(7, "GPIO_7"),
	PINCTRL_PIN(8, "GPIO_8"),
	PINCTRL_PIN(9, "GPIO_9"),
	PINCTRL_PIN(10, "GPIO_10"),
	PINCTRL_PIN(11, "GPIO_11"),
	PINCTRL_PIN(12, "GPIO_12"),
	PINCTRL_PIN(13, "GPIO_13"),
	PINCTRL_PIN(14, "GPIO_14"),
	PINCTRL_PIN(15, "GPIO_15"),
Ejemplo n.º 25
0
#define WMT_PIN_UART2_TXD	WMT_PIN(9, 9)
#define WMT_PIN_UART2_CTS	WMT_PIN(9, 10)
#define WMT_PIN_UART2_RXD	WMT_PIN(9, 11)
#define WMT_PIN_UART3_RTS	WMT_PIN(9, 12)
#define WMT_PIN_UART3_TXD	WMT_PIN(9, 13)
#define WMT_PIN_UART3_CTS	WMT_PIN(9, 14)
#define WMT_PIN_UART3_RXD	WMT_PIN(9, 15)
#define WMT_PIN_I2C0SCL		WMT_PIN(10, 0)
#define WMT_PIN_I2C0SDA		WMT_PIN(10, 1)
#define WMT_PIN_I2C1SCL		WMT_PIN(10, 2)
#define WMT_PIN_I2C1SDA		WMT_PIN(10, 3)
#define WMT_PIN_I2C2SCL		WMT_PIN(10, 4)
#define WMT_PIN_I2C2SDA		WMT_PIN(10, 5)

static const struct pinctrl_pin_desc wm8505_pins[] = {
	PINCTRL_PIN(WMT_PIN_EXTGPIO0, "extgpio0"),
	PINCTRL_PIN(WMT_PIN_EXTGPIO1, "extgpio1"),
	PINCTRL_PIN(WMT_PIN_EXTGPIO2, "extgpio2"),
	PINCTRL_PIN(WMT_PIN_EXTGPIO3, "extgpio3"),
	PINCTRL_PIN(WMT_PIN_EXTGPIO4, "extgpio4"),
	PINCTRL_PIN(WMT_PIN_EXTGPIO5, "extgpio5"),
	PINCTRL_PIN(WMT_PIN_EXTGPIO6, "extgpio6"),
	PINCTRL_PIN(WMT_PIN_EXTGPIO7, "extgpio7"),
	PINCTRL_PIN(WMT_PIN_WAKEUP0, "wakeup0"),
	PINCTRL_PIN(WMT_PIN_WAKEUP1, "wakeup1"),
	PINCTRL_PIN(WMT_PIN_WAKEUP2, "wakeup2"),
	PINCTRL_PIN(WMT_PIN_WAKEUP3, "wakeup3"),
	PINCTRL_PIN(WMT_PIN_SUSGPIO0, "susgpio0"),
	PINCTRL_PIN(WMT_PIN_SDDATA0, "sd_data0"),
	PINCTRL_PIN(WMT_PIN_SDDATA1, "sd_data1"),
	PINCTRL_PIN(WMT_PIN_SDDATA2, "sd_data2"),
Ejemplo n.º 26
0
#define SPT_COMMUNITY(b, s, e)				\
	{						\
		.barno = (b),				\
		.padown_offset = SPT_PAD_OWN,		\
		.padcfglock_offset = SPT_PADCFGLOCK,	\
		.hostown_offset = SPT_HOSTSW_OWN,	\
		.ie_offset = SPT_GPI_IE,		\
		.gpp_size = 24,				\
		.pin_base = (s),			\
		.npins = ((e) - (s) + 1),		\
	}

/* Sunrisepoint-LP */
static const struct pinctrl_pin_desc sptlp_pins[] = {
	/* GPP_A */
	PINCTRL_PIN(0, "RCINB"),
	PINCTRL_PIN(1, "LAD_0"),
	PINCTRL_PIN(2, "LAD_1"),
	PINCTRL_PIN(3, "LAD_2"),
	PINCTRL_PIN(4, "LAD_3"),
	PINCTRL_PIN(5, "LFRAMEB"),
	PINCTRL_PIN(6, "SERIQ"),
	PINCTRL_PIN(7, "PIRQAB"),
	PINCTRL_PIN(8, "CLKRUNB"),
	PINCTRL_PIN(9, "CLKOUT_LPC_0"),
	PINCTRL_PIN(10, "CLKOUT_LPC_1"),
	PINCTRL_PIN(11, "PMEB"),
	PINCTRL_PIN(12, "BM_BUSYB"),
	PINCTRL_PIN(13, "SUSWARNB_SUS_PWRDNACK"),
	PINCTRL_PIN(14, "SUS_STATB"),
	PINCTRL_PIN(15, "SUSACKB"),
Ejemplo n.º 27
0
#define STN8815_PIN_G22		_GPIO(118)
#define STN8815_PIN_U19		_GPIO(119)
#define STN8815_PIN_G19		_GPIO(120)
#define STN8815_PIN_M22		_GPIO(121)
#define STN8815_PIN_M19		_GPIO(122)
#define STN8815_PIN_J22		_GPIO(123)
/* GPIOs 124-127 not routed to pins */

/*
 * The names of the pins are denoted by GPIO number and ball name, even
 * though they can be used for other things than GPIO, this is the first
 * column in the table of the data sheet and often used on schematics and
 * such.
 */
static const struct pinctrl_pin_desc nmk_stn8815_pins[] = {
	PINCTRL_PIN(STN8815_PIN_B4, "GPIO0_B4"),
	PINCTRL_PIN(STN8815_PIN_D5, "GPIO1_D5"),
	PINCTRL_PIN(STN8815_PIN_C5, "GPIO2_C5"),
	PINCTRL_PIN(STN8815_PIN_A4, "GPIO3_A4"),
	PINCTRL_PIN(STN8815_PIN_B5, "GPIO4_B5"),
	PINCTRL_PIN(STN8815_PIN_D6, "GPIO5_D6"),
	PINCTRL_PIN(STN8815_PIN_C6, "GPIO6_C6"),
	PINCTRL_PIN(STN8815_PIN_B6, "GPIO7_B6"),
	PINCTRL_PIN(STN8815_PIN_B10, "GPIO8_B10"),
	PINCTRL_PIN(STN8815_PIN_A10, "GPIO9_A10"),
	PINCTRL_PIN(STN8815_PIN_C11, "GPIO10_C11"),
	PINCTRL_PIN(STN8815_PIN_B11, "GPIO11_B11"),
	PINCTRL_PIN(STN8815_PIN_A11, "GPIO12_A11"),
	PINCTRL_PIN(STN8815_PIN_C12, "GPIO13_C12"),
	PINCTRL_PIN(STN8815_PIN_B12, "GPIO14_B12"),
	PINCTRL_PIN(STN8815_PIN_A12, "GPIO15_A12"),
Ejemplo n.º 28
0
	struct device *dev;
	struct pinctrl_dev *pctl;
	struct as3722 *as3722;
	struct gpio_chip gpio_chip;
	int pins_current_opt[AS3722_PIN_NUM];
	const struct as3722_pin_function *functions;
	unsigned num_functions;
	const struct as3722_pingroup *pin_groups;
	int num_pin_groups;
	const struct pinctrl_pin_desc *pins;
	unsigned num_pins;
	struct as3722_gpio_pin_control gpio_control[AS3722_PIN_NUM];
};

static const struct pinctrl_pin_desc as3722_pins_desc[] = {
	PINCTRL_PIN(AS3722_PIN_GPIO0, "gpio0"),
	PINCTRL_PIN(AS3722_PIN_GPIO1, "gpio1"),
	PINCTRL_PIN(AS3722_PIN_GPIO2, "gpio2"),
	PINCTRL_PIN(AS3722_PIN_GPIO3, "gpio3"),
	PINCTRL_PIN(AS3722_PIN_GPIO4, "gpio4"),
	PINCTRL_PIN(AS3722_PIN_GPIO5, "gpio5"),
	PINCTRL_PIN(AS3722_PIN_GPIO6, "gpio6"),
	PINCTRL_PIN(AS3722_PIN_GPIO7, "gpio7"),
};

static const char * const gpio_groups[] = {
	"gpio0",
	"gpio1",
	"gpio2",
	"gpio3",
	"gpio4",
Ejemplo n.º 29
0
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/pinctrl.h>

#include "pinctrl-msm.h"

static const struct pinctrl_pin_desc msm8660_pins[] = {
	PINCTRL_PIN(0, "GPIO_0"),
	PINCTRL_PIN(1, "GPIO_1"),
	PINCTRL_PIN(2, "GPIO_2"),
	PINCTRL_PIN(3, "GPIO_3"),
	PINCTRL_PIN(4, "GPIO_4"),
	PINCTRL_PIN(5, "GPIO_5"),
	PINCTRL_PIN(6, "GPIO_6"),
	PINCTRL_PIN(7, "GPIO_7"),
	PINCTRL_PIN(8, "GPIO_8"),
	PINCTRL_PIN(9, "GPIO_9"),
	PINCTRL_PIN(10, "GPIO_10"),
	PINCTRL_PIN(11, "GPIO_11"),
	PINCTRL_PIN(12, "GPIO_12"),
	PINCTRL_PIN(13, "GPIO_13"),
	PINCTRL_PIN(14, "GPIO_14"),
	PINCTRL_PIN(15, "GPIO_15"),
Ejemplo n.º 30
0
#define AB8540_PIN_K8		ABX500_GPIO(53)
#define AB8540_PIN_J11		ABX500_GPIO(54)
#define AB8540_PIN_AC2		ABX500_GPIO(55)
#define AB8540_PIN_AB2		ABX500_GPIO(56)

/* indicates the highest GPIO number */
#define AB8540_GPIO_MAX_NUMBER	56

/*
 * The names of the pins are denoted by GPIO number and ball name, even
 * though they can be used for other things than GPIO, this is the first
 * column in the table of the data sheet and often used on schematics and
 * such.
 */
static const struct pinctrl_pin_desc ab8540_pins[] = {
	PINCTRL_PIN(AB8540_PIN_J16, "GPIO1_J16"),
	PINCTRL_PIN(AB8540_PIN_D17, "GPIO2_D17"),
	PINCTRL_PIN(AB8540_PIN_C12, "GPIO3_C12"),
	PINCTRL_PIN(AB8540_PIN_G12, "GPIO4_G12"),
	/* hole */
	PINCTRL_PIN(AB8540_PIN_D16, "GPIO14_D16"),
	PINCTRL_PIN(AB8540_PIN_F15, "GPIO15_F15"),
	PINCTRL_PIN(AB8540_PIN_J8, "GPIO16_J8"),
	PINCTRL_PIN(AB8540_PIN_K16, "GPIO17_K16"),
	PINCTRL_PIN(AB8540_PIN_G15, "GPIO18_G15"),
	PINCTRL_PIN(AB8540_PIN_F17, "GPIO19_F17"),
	PINCTRL_PIN(AB8540_PIN_E17, "GPIO20_E17"),
	/* hole */
	PINCTRL_PIN(AB8540_PIN_AA16, "GPIO27_AA16"),
	PINCTRL_PIN(AB8540_PIN_W18, "GPIO28_W18"),
	PINCTRL_PIN(AB8540_PIN_Y15, "GPIO29_Y15"),