u_int32_t
bmac_mbo_read(struct device *dev)
{
struct bmac_softc *sc = (void *)dev;
return bmac_read_reg(sc, MIFCSR);
}
int
bmac_intr(void *v)
{
struct bmac_softc *sc = v;
struct ifnet *ifp = &sc->arpcom.ac_if;
int stat;
#ifdef BMAC_DEBUG
printf("bmac_intr called\n");
#endif
stat = bmac_read_reg(sc, STATUS);
if (stat == 0)
return (0);
#ifdef BMAC_DEBUG
printf("bmac_intr status = 0x%x\n", stat);
#endif
if (stat & IntFrameSent) {
ifp->if_flags &= ~IFF_OACTIVE;
ifp->if_timer = 0;
ifp->if_opackets++;
bmac_start(ifp);
}
/* XXX should do more! */
return (1);
}
/*
* Set up the logical address filter.
*/
void
bmac_setladrf(struct bmac_softc *sc)
{
struct arpcom *ac = &sc->arpcom;
struct ifnet *ifp = &sc->arpcom.ac_if;
struct ether_multi *enm;
struct ether_multistep step;
u_int32_t crc;
u_int16_t hash[4];
int x;
/*
* Set up multicast address filter by passing all multicast addresses
* through a crc generator, and then using the high order 6 bits as an
* index into the 64 bit logical address filter. The high order bit
* selects the word, while the rest of the bits select the bit within
* the word.
*/
if (ifp->if_flags & IFF_PROMISC) {
bmac_set_bits(sc, RXCFG, RxPromiscEnable);
return;
}
if (ac->ac_multirangecnt > 0)
ifp->if_flags |= IFF_ALLMULTI;
if (ifp->if_flags & IFF_ALLMULTI) {
hash[3] = hash[2] = hash[1] = hash[0] = 0xffff;
goto chipit;
}
hash[3] = hash[2] = hash[1] = hash[0] = 0;
ETHER_FIRST_MULTI(step, ac, enm);
while (enm != NULL) {
crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN);
/* Just want the 6 most significant bits. */
crc >>= 26;
/* Set the corresponding bit in the filter. */
hash[crc >> 4] |= 1 << (crc & 0xf);
ETHER_NEXT_MULTI(step, enm);
}
ifp->if_flags &= ~IFF_ALLMULTI;
chipit:
bmac_write_reg(sc, HASH0, hash[0]);
bmac_write_reg(sc, HASH1, hash[1]);
bmac_write_reg(sc, HASH2, hash[2]);
bmac_write_reg(sc, HASH3, hash[3]);
x = bmac_read_reg(sc, RXCFG);
x &= ~RxPromiscEnable;
x |= RxHashFilterEnable;
bmac_write_reg(sc, RXCFG, x);
}
void
bmac_mii_statchg(struct device *dev)
{
struct bmac_softc *sc = (void *)dev;
int x;
/* Update duplex mode in TX configuration */
x = bmac_read_reg(sc, TXCFG);
if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0)
x |= TxFullDuplex;
else
x &= ~TxFullDuplex;
bmac_write_reg(sc, TXCFG, x);
#ifdef BMAC_DEBUG
printf("bmac_mii_statchg 0x%x\n",
IFM_OPTIONS(sc->sc_mii.mii_media_active));
#endif
}
/*
* Set up the logical address filter.
*/
void
bmac_setladrf(struct bmac_softc *sc)
{
struct ifnet *ifp = &sc->arpcom.ac_if;
struct ether_multi *enm;
struct ether_multistep step;
u_int32_t crc;
u_int16_t hash[4];
int x;
/*
* Set up multicast address filter by passing all multicast addresses
* through a crc generator, and then using the high order 6 bits as an
* index into the 64 bit logical address filter. The high order bit
* selects the word, while the rest of the bits select the bit within
* the word.
*/
if (ifp->if_flags & IFF_PROMISC) {
bmac_set_bits(sc, RXCFG, RxPromiscEnable);
return;
}
if (ifp->if_flags & IFF_ALLMULTI) {
hash[3] = hash[2] = hash[1] = hash[0] = 0xffff;
goto chipit;
}
hash[3] = hash[2] = hash[1] = hash[0] = 0;
ETHER_FIRST_MULTI(step, &sc->arpcom, enm);
while (enm != NULL) {
if (bcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) {
/*
* We must listen to a range of multicast addresses.
* For now, just accept all multicasts, rather than
* trying to set only those filter bits needed to match
* the range. (At this time, the only use of address
* ranges is for IP multicast routing, for which the
* range is big enough to require all bits set.)
*/
hash[3] = hash[2] = hash[1] = hash[0] = 0xffff;
ifp->if_flags |= IFF_ALLMULTI;
goto chipit;
}
crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN);
/* Just want the 6 most significant bits. */
crc >>= 26;
/* Set the corresponding bit in the filter. */
hash[crc >> 4] |= 1 << (crc & 0xf);
ETHER_NEXT_MULTI(step, enm);
}
ifp->if_flags &= ~IFF_ALLMULTI;
chipit:
bmac_write_reg(sc, HASH0, hash[0]);
bmac_write_reg(sc, HASH1, hash[1]);
bmac_write_reg(sc, HASH2, hash[2]);
bmac_write_reg(sc, HASH3, hash[3]);
x = bmac_read_reg(sc, RXCFG);
x &= ~RxPromiscEnable;
x |= RxHashFilterEnable;
bmac_write_reg(sc, RXCFG, x);
}
void
bmac_init(struct bmac_softc *sc)
{
struct ifnet *ifp = &sc->arpcom.ac_if;
struct ether_header *eh;
caddr_t data;
int tb;
int i, bmcr;
u_short *p;
bmac_reset_chip(sc);
/* XXX */
bmcr = bmac_mii_readreg((struct device *)sc, 0, MII_BMCR);
bmcr &= ~BMCR_ISO;
bmac_mii_writereg((struct device *)sc, 0, MII_BMCR, bmcr);
bmac_write_reg(sc, RXRST, RxResetValue);
bmac_write_reg(sc, TXRST, TxResetBit);
/* Wait for reset completion. */
for (i = 1000; i > 0; i -= 10) {
if ((bmac_read_reg(sc, TXRST) & TxResetBit) == 0)
break;
delay(10);
}
if (i <= 0)
printf("%s: reset timeout\n", ifp->if_xname);
if (! (sc->sc_flags & BMAC_BMACPLUS))
bmac_set_bits(sc, XCVRIF, ClkBit|SerialMode|COLActiveLow);
tb = ppc_mftbl();
bmac_write_reg(sc, RSEED, tb);
bmac_set_bits(sc, XIFC, TxOutputEnable);
bmac_read_reg(sc, PAREG);
/* Reset various counters. */
bmac_write_reg(sc, NCCNT, 0);
bmac_write_reg(sc, NTCNT, 0);
bmac_write_reg(sc, EXCNT, 0);
bmac_write_reg(sc, LTCNT, 0);
bmac_write_reg(sc, FRCNT, 0);
bmac_write_reg(sc, LECNT, 0);
bmac_write_reg(sc, AECNT, 0);
bmac_write_reg(sc, FECNT, 0);
bmac_write_reg(sc, RXCV, 0);
/* Set tx fifo information. */
bmac_write_reg(sc, TXTH, 4); /* 4 octets before tx starts */
bmac_write_reg(sc, TXFIFOCSR, 0);
bmac_write_reg(sc, TXFIFOCSR, TxFIFOEnable);
/* Set rx fifo information. */
bmac_write_reg(sc, RXFIFOCSR, 0);
bmac_write_reg(sc, RXFIFOCSR, RxFIFOEnable);
/* Clear status register. */
bmac_read_reg(sc, STATUS);
bmac_write_reg(sc, HASH3, 0);
bmac_write_reg(sc, HASH2, 0);
bmac_write_reg(sc, HASH1, 0);
bmac_write_reg(sc, HASH0, 0);
/* Set MAC address. */
p = (u_short *)sc->arpcom.ac_enaddr;
bmac_write_reg(sc, MADD0, *p++);
bmac_write_reg(sc, MADD1, *p++);
bmac_write_reg(sc, MADD2, *p);
bmac_write_reg(sc, RXCFG,
RxCRCEnable | RxHashFilterEnable | RxRejectOwnPackets);
if (ifp->if_flags & IFF_PROMISC)
bmac_set_bits(sc, RXCFG, RxPromiscEnable);
bmac_init_dma(sc);
/* Configure Media. */
mii_mediachg(&sc->sc_mii);
/* Enable TX/RX */
bmac_set_bits(sc, RXCFG, RxMACEnable);
bmac_set_bits(sc, TXCFG, TxMACEnable);
bmac_write_reg(sc, INTDISABLE, NormalIntEvents);
ifp->if_flags |= IFF_RUNNING;
ifp->if_flags &= ~IFF_OACTIVE;
ifp->if_timer = 0;
data = sc->sc_txbuf;
eh = (struct ether_header *)data;
bzero(data, sizeof(*eh) + ETHERMIN);
bcopy(sc->arpcom.ac_enaddr, eh->ether_dhost, ETHER_ADDR_LEN);
bcopy(sc->arpcom.ac_enaddr, eh->ether_shost, ETHER_ADDR_LEN);
bmac_transmit_packet(sc, sc->sc_txbuf_pa, sizeof(*eh) + ETHERMIN);
bmac_start(ifp);
timeout_add_sec(&sc->sc_tick_ch, 1);
}
void
bmac_reset_bits(struct bmac_softc *sc, int off, int val)
{
bmac_write_reg(sc, off, bmac_read_reg(sc, off) & ~val);
}
void
bmac_set_bits(struct bmac_softc *sc, int off, int val)
{
val |= bmac_read_reg(sc, off);
bmac_write_reg(sc, off, val);
}
static inline void
bmac_reset_bits(struct bmac_softc *sc, bus_size_t off, uint16_t val)
{
bmac_write_reg(sc, off, bmac_read_reg(sc, off) & ~val);
}