/*-----------------------------------------------------------------------
* Send a reset sequence consisting of 9 clocks with the data signal high
* to clock any confused device back into an idle state. Also send a
* <stop> at the end of the sequence for belts & suspenders.
*/
static void send_reset(void)
{
#ifdef CONFIG_MPC8260
volatile ioport_t *iop = ioport_addr((immap_t *)CFG_IMMR, I2C_PORT);
#endif
#ifdef CONFIG_8xx
volatile immap_t *immr = (immap_t *)CFG_IMMR;
#endif
int j;
I2C_SCL(1);
I2C_SDA(1);
#ifdef I2C_INIT
I2C_INIT;
#endif
I2C_TRISTATE;
for(j = 0; j < 9; j++) {
I2C_SCL(0);
I2C_DELAY;
I2C_DELAY;
I2C_SCL(1);
I2C_DELAY;
I2C_DELAY;
}
send_stop();
I2C_TRISTATE;
}
void reset_phy (void)
{
volatile ioport_t *iop;
#if defined(CONFIG_CMD_NET)
int i;
unsigned short val;
#endif
iop = ioport_addr((immap_t *)CONFIG_SYS_IMMR, 0);
/* Reset the PHY */
iop->pdat &= 0xfff7ffff; /* PA12 = |SWITCH_RESET */
#if defined(CONFIG_CMD_NET)
udelay(20000);
iop->pdat |= 0x00080000;
for (i=0; i<100; i++) {
udelay(20000);
if (bb_miiphy_read("FCC1", CONFIG_SYS_PHY_ADDR,2,&val ) == 0) {
break;
}
}
/* initialize switch */
m88e6060_initialize( CONFIG_SYS_PHY_ADDR );
#endif
}
static int get_pin(unsigned long mask, int port)
{
ioport_t *iop = ioport_addr((immap_t *)CONFIG_SYS_IMMR, port);
clrbits_be32(&iop->pdir, mask);
return 0 != (in_be32(&iop->pdat) & mask);
}
/*-----------------------------------------------------------------------
* if ack == I2C_ACK, ACK the byte so can continue reading, else
* send I2C_NOACK to end the read.
*/
static uchar read_byte(int ack)
{
#ifdef CONFIG_MPC8260
volatile ioport_t *iop = ioport_addr((immap_t *)CFG_IMMR, I2C_PORT);
#endif
#ifdef CONFIG_8xx
volatile immap_t *immr = (immap_t *)CFG_IMMR;
#endif
int data;
int j;
/*
* Read 8 bits, MSB first.
*/
I2C_TRISTATE;
data = 0;
for(j = 0; j < 8; j++) {
I2C_SCL(0);
I2C_DELAY;
I2C_SCL(1);
I2C_DELAY;
data <<= 1;
data |= I2C_READ;
I2C_DELAY;
}
send_ack(ack);
return(data);
}
int
do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
volatile ioport_t *iop;
iop = ioport_addr((immap_t *)CONFIG_SYS_IMMR, 2);
iop->pdat |= 0x00002000; /* PC18 = HW_RESET */
return 1;
}
int
do_reset (void *cmdtp, int flag, int argc, char *argv[])
{
volatile ioport_t *iop;
iop = ioport_addr((immap_t *)CFG_IMMR, 2);
iop->pdat |= 0x00002000; /* PC18 = HW_RESET */
return 1;
}
static void set_pin(int state, unsigned long mask, int port)
{
ioport_t *iop = ioport_addr((immap_t *)CONFIG_SYS_IMMR, port);
if (state)
setbits_be32(&iop->pdat, mask);
else
clrbits_be32(&iop->pdat, mask);
setbits_be32(&iop->pdir, mask);
}
static void setports(int gpio)
{
ioport_t *iop = ioport_addr((immap_t *)CONFIG_SYS_IMMR, 3);
if (gpio) {
clrbits_be32(&iop->ppar, (SDA_MASK | SCL_MASK));
clrbits_be32(&iop->podr, (SDA_MASK | SCL_MASK));
} else {
setbits_be32(&iop->ppar, (SDA_MASK | SCL_MASK));
clrbits_be32(&iop->pdir, (SDA_MASK | SCL_MASK));
setbits_be32(&iop->podr, (SDA_MASK | SCL_MASK));
}
}
/*-----------------------------------------------------------------------
* START: High -> Low on SDA while SCL is High
*/
static void send_start(void)
{
#ifdef CONFIG_MPC8260
volatile ioport_t *iop = ioport_addr((immap_t *)CFG_IMMR, I2C_PORT);
#endif
#ifdef CONFIG_8xx
volatile immap_t *immr = (immap_t *)CFG_IMMR;
#endif
I2C_DELAY;
I2C_SDA(1);
I2C_ACTIVE;
I2C_DELAY;
I2C_SCL(1);
I2C_DELAY;
I2C_SDA(0);
I2C_DELAY;
}
int misc_init_r (void)
{
volatile ioport_t *iop;
unsigned char temp;
#if 0
/* DUMP UPMA RAM */
volatile immap_t *immap;
volatile memctl8260_t *memctl;
volatile unsigned char *dummy;
unsigned char c;
int i;
immap = (immap_t *) CONFIG_SYS_IMMR;
memctl = &immap->im_memctl;
dummy = (volatile unsigned char *) (memctl->memc_br7 & BRx_BA_MSK);
memctl->memc_mar = 0;
memctl->memc_mamr = MxMR_OP_RARR;
for (i = 0; i < 64; i++) {
c = *dummy;
printf( "UPMA[%02d]: 0x%08lx,0x%08lx: 0x%08lx\n",i,
memctl->memc_mamr,
memctl->memc_mar,
memctl->memc_mdr );
}
memctl->memc_mamr = 0x00044440;
#endif
/* enable buffers (DSP, DPRAM) */
iop = ioport_addr((immap_t *)CONFIG_SYS_IMMR, 0);
iop->pdat &= 0xfffbffff; /* PA13 = |EN_M_BCTL1 */
/* destroy DPRAM magic */
*(volatile unsigned char *)0xf0500000 = 0x00;
/* clear any pending DPRAM irq */
temp = *(volatile unsigned char *)0xf05003ff;
/* write module-id into DPRAM */
*(volatile unsigned char *)0xf0500201 = 0x50;
return 0;
}
/*-----------------------------------------------------------------------
* Send 8 bits and look for an acknowledgement.
*/
static int write_byte(uchar data)
{
#ifdef CONFIG_MPC8260
volatile ioport_t *iop = ioport_addr((immap_t *)CFG_IMMR, I2C_PORT);
#endif
#ifdef CONFIG_8xx
volatile immap_t *immr = (immap_t *)CFG_IMMR;
#endif
int j;
int nack;
I2C_ACTIVE;
for(j = 0; j < 8; j++) {
I2C_SCL(0);
I2C_DELAY;
I2C_SDA(data & 0x80);
I2C_DELAY;
I2C_SCL(1);
I2C_DELAY;
I2C_DELAY;
data <<= 1;
}
/*
* Look for an <ACK>(negative logic) and return it.
*/
I2C_SCL(0);
I2C_DELAY;
I2C_SDA(1);
I2C_TRISTATE;
I2C_DELAY;
I2C_SCL(1);
I2C_DELAY;
I2C_DELAY;
nack = I2C_READ;
I2C_SCL(0);
I2C_DELAY;
I2C_ACTIVE;
return(nack); /* not a nack is an ack */
}
void spi_cs_deactivate(struct spi_slave *slave)
{
volatile ioport_t *iopd = ioport_addr((immap_t *)CONFIG_SYS_IMMR, 3 /* port D */);
iopd->pdat |= cs_mask[slave->cs];
}
/* ------------------------------------------------------------------------- */
int misc_init_r(void)
{
/*
* Note: iop is used by the I2C macros, and iopa by the ADC/DAC initialization.
*/
volatile ioport_t *iopa = ioport_addr((immap_t *)CONFIG_SYS_IMMR, 0 /* port A */);
volatile ioport_t *iop = ioport_addr((immap_t *)CONFIG_SYS_IMMR, I2C_PORT);
int reg; /* I2C register value */
char *ep; /* Environment pointer */
char str_buf[12] ; /* sprintf output buffer */
int sample_rate; /* ADC/DAC sample rate */
int sample_64x; /* Use 64/4 clocking for the ADC/DAC */
int sample_128x; /* Use 128/4 clocking for the ADC/DAC */
int right_just; /* Is the data to the DAC right justified? */
int mclk_divide; /* MCLK Divide */
int quiet; /* Quiet or minimal output mode */
quiet = 0;
if ((ep = getenv("quiet")) != NULL) {
quiet = simple_strtol(ep, NULL, 10);
}
else {
setenv("quiet", "0");
}
/*
* SACSng custom initialization:
* Start the ADC and DAC clocks, since the Crystal parts do not
* work on the I2C bus until the clocks are running.
*/
sample_rate = INITIAL_SAMPLE_RATE;
if ((ep = getenv("DaqSampleRate")) != NULL) {
sample_rate = simple_strtol(ep, NULL, 10);
}
sample_64x = INITIAL_SAMPLE_64X;
sample_128x = INITIAL_SAMPLE_128X;
if ((ep = getenv("Daq64xSampling")) != NULL) {
sample_64x = simple_strtol(ep, NULL, 10);
if (sample_64x) {
sample_128x = 0;
}
else {
sample_128x = 1;
}
}
else {
if ((ep = getenv("Daq128xSampling")) != NULL) {
sample_128x = simple_strtol(ep, NULL, 10);
if (sample_128x) {
sample_64x = 0;
}
else {
sample_64x = 1;
}
}
}
/*
* Stop the clocks and wait for at least 1 LRCLK period
* to make sure the clocking has really stopped.
*/
Daq_Stop_Clocks();
udelay((1000000 / sample_rate) * NUM_LRCLKS_TO_STABILIZE);
/*
* Initialize the clocks with the new rates
*/
Daq_Init_Clocks(sample_rate, sample_64x);
sample_rate = Daq_Get_SampleRate();
/*
* Start the clocks and wait for at least 1 LRCLK period
* to make sure the clocking has become stable.
*/
Daq_Start_Clocks(sample_rate);
udelay((1000000 / sample_rate) * NUM_LRCLKS_TO_STABILIZE);
sprintf(str_buf, "%d", sample_rate);
setenv("DaqSampleRate", str_buf);
if (sample_64x) {
setenv("Daq64xSampling", "1");
setenv("Daq128xSampling", NULL);
}
else {
setenv("Daq64xSampling", NULL);
setenv("Daq128xSampling", "1");
}
/*
* Display the ADC/DAC clocking information
*/
if (!quiet) {
Daq_Display_Clocks();
}
/*
* Determine the DAC data justification
*/
right_just = INITIAL_RIGHT_JUST;
if ((ep = getenv("DaqDACRightJustified")) != NULL) {
right_just = simple_strtol(ep, NULL, 10);
}
sprintf(str_buf, "%d", right_just);
setenv("DaqDACRightJustified", str_buf);
/*
* Determine the DAC MCLK Divide
*/
mclk_divide = INITIAL_MCLK_DIVIDE;
if ((ep = getenv("DaqDACMClockDivide")) != NULL) {
mclk_divide = simple_strtol(ep, NULL, 10);
}
sprintf(str_buf, "%d", mclk_divide);
setenv("DaqDACMClockDivide", str_buf);
/*
* Initializing the I2C address in the Crystal A/Ds:
*
* 1) Wait for VREF cap to settle (10uSec per uF)
* 2) Release pullup on SDATA
* 3) Write the I2C address to register 6
* 4) Enable address matching by setting the MSB in register 7
*/
if (!quiet) {
printf("Initializing the ADC...\n");
}
udelay(ADC_INITIAL_DELAY); /* 10uSec per uF of VREF cap */
iopa->pdat &= ~ADC_SDATA1_MASK; /* release SDATA1 */
udelay(ADC_SDATA_DELAY); /* arbitrary settling time */
i2c_reg_write(0x00, 0x06, I2C_ADC_1_ADDR); /* set address */
i2c_reg_write(I2C_ADC_1_ADDR, 0x07, /* turn on ADDREN */
ADC_REG7_ADDR_ENABLE);
i2c_reg_write(I2C_ADC_1_ADDR, 0x02, /* 128x, slave mode, !HPEN */
(sample_64x ? 0 : ADC_REG2_128x) |
ADC_REG2_HIGH_PASS_DIS |
ADC_REG2_SLAVE_MODE);
reg = i2c_reg_read(I2C_ADC_1_ADDR, 0x06) & 0x7F;
if(reg != I2C_ADC_1_ADDR)
printf("Init of ADC U10 failed: address is 0x%02X should be 0x%02X\n",
reg, I2C_ADC_1_ADDR);
iopa->pdat &= ~ADC_SDATA2_MASK; /* release SDATA2 */
udelay(ADC_SDATA_DELAY); /* arbitrary settling time */
i2c_reg_write(0x00, 0x06, I2C_ADC_2_ADDR); /* set address (do not set ADDREN yet) */
i2c_reg_write(I2C_ADC_2_ADDR, 0x02, /* 64x, slave mode, !HPEN */
(sample_64x ? 0 : ADC_REG2_128x) |
ADC_REG2_HIGH_PASS_DIS |
ADC_REG2_SLAVE_MODE);
reg = i2c_reg_read(I2C_ADC_2_ADDR, 0x06) & 0x7F;
if(reg != I2C_ADC_2_ADDR)
printf("Init of ADC U15 failed: address is 0x%02X should be 0x%02X\n",
reg, I2C_ADC_2_ADDR);
i2c_reg_write(I2C_ADC_1_ADDR, 0x01, /* set FSTART and GNDCAL */
ADC_REG1_FRAME_START |
ADC_REG1_GROUND_CAL);
i2c_reg_write(I2C_ADC_1_ADDR, 0x02, /* Start calibration */
(sample_64x ? 0 : ADC_REG2_128x) |
ADC_REG2_CAL |
ADC_REG2_HIGH_PASS_DIS |
ADC_REG2_SLAVE_MODE);
udelay(ADC_CAL_DELAY); /* a minimum of 4100 LRCLKs */
i2c_reg_write(I2C_ADC_1_ADDR, 0x01, 0x00); /* remove GNDCAL */
/*
* Now that we have synchronized the ADC's, enable address
* selection on the second ADC as well as the first.
*/
i2c_reg_write(I2C_ADC_2_ADDR, 0x07, ADC_REG7_ADDR_ENABLE);
/*
* Initialize the Crystal DAC
*
* Two of the config lines are used for I2C so we have to set them
* to the proper initialization state without inadvertantly
* sending an I2C "start" sequence. When we bring the I2C back to
* the normal state, we send an I2C "stop" sequence.
*/
if (!quiet) {
printf("Initializing the DAC...\n");
}
/*
* Bring the I2C clock and data lines low for initialization
*/
I2C_SCL(0);
I2C_DELAY;
I2C_SDA(0);
I2C_ACTIVE;
I2C_DELAY;
/* Reset the DAC */
iopa->pdat &= ~DAC_RST_MASK;
udelay(DAC_RESET_DELAY);
/* Release the DAC reset */
iopa->pdat |= DAC_RST_MASK;
udelay(DAC_INITIAL_DELAY);
/*
* Cause the DAC to:
* Enable control port (I2C mode)
* Going into power down
*/
i2c_reg_write(I2C_DAC_ADDR, 0x05,
DAC_REG5_I2C_MODE |
DAC_REG5_POWER_DOWN);
/*
* Cause the DAC to:
* Enable control port (I2C mode)
* Going into power down
* . MCLK divide by 1
* . MCLK divide by 2
*/
i2c_reg_write(I2C_DAC_ADDR, 0x05,
DAC_REG5_I2C_MODE |
DAC_REG5_POWER_DOWN |
(mclk_divide ? DAC_REG5_MCLK_DIV : 0));
/*
* Cause the DAC to:
* Auto-mute disabled
* . Format 0, left justified 24 bits
* . Format 3, right justified 24 bits
* No de-emphasis
* . Single speed mode
* . Double speed mode
*/
i2c_reg_write(I2C_DAC_ADDR, 0x01,
(right_just ? DAC_REG1_RIGHT_JUST_24BIT :
DAC_REG1_LEFT_JUST_24_BIT) |
DAC_REG1_DEM_NO |
(sample_rate >= 50000 ? DAC_REG1_DOUBLE : DAC_REG1_SINGLE));
sprintf(str_buf, "%d",
sample_rate >= 50000 ? DAC_REG1_DOUBLE : DAC_REG1_SINGLE);
setenv("DaqDACFunctionalMode", str_buf);
/*
* Cause the DAC to:
* Enable control port (I2C mode)
* Remove power down
* . MCLK divide by 1
* . MCLK divide by 2
*/
i2c_reg_write(I2C_DAC_ADDR, 0x05,
DAC_REG5_I2C_MODE |
(mclk_divide ? DAC_REG5_MCLK_DIV : 0));
/*
* Create a I2C stop condition:
* low->high on data while clock is high.
*/
I2C_SCL(1);
I2C_DELAY;
I2C_SDA(1);
I2C_DELAY;
I2C_TRISTATE;
if (!quiet) {
printf("\n");
}
#ifdef CONFIG_ETHER_LOOPBACK_TEST
/*
* Run the Ethernet loopback test
*/
eth_loopback_test ();
#endif /* CONFIG_ETHER_LOOPBACK_TEST */
#ifdef CONFIG_SHOW_BOOT_PROGRESS
/*
* Turn off the RED fail LED now that we are up and running.
*/
status_led_set(STATUS_LED_RED, STATUS_LED_OFF);
#endif
return 0;
}
static void config_8260_ioports (volatile immap_t * immr)
{
int portnum;
for (portnum = 0; portnum < 4; portnum++) {
uint pmsk = 0,
ppar = 0,
psor = 0,
pdir = 0,
podr = 0,
pdat = 0;
iop_conf_t *iopc = (iop_conf_t *) & iop_conf_tab[portnum][0];
iop_conf_t *eiopc = iopc + 32;
uint msk = 1;
/*
* NOTE:
* index 0 refers to pin 31,
* index 31 refers to pin 0
*/
while (iopc < eiopc) {
if (iopc->conf) {
pmsk |= msk;
if (iopc->ppar)
ppar |= msk;
if (iopc->psor)
psor |= msk;
if (iopc->pdir)
pdir |= msk;
if (iopc->podr)
podr |= msk;
if (iopc->pdat)
pdat |= msk;
}
msk <<= 1;
iopc++;
}
if (pmsk != 0) {
volatile ioport_t *iop = ioport_addr (immr, portnum);
uint tpmsk = ~pmsk;
/*
* the (somewhat confused) paragraph at the
* bottom of page 35-5 warns that there might
* be "unknown behaviour" when programming
* PSORx and PDIRx, if PPARx = 1, so I
* decided this meant I had to disable the
* dedicated function first, and enable it
* last.
*/
iop->ppar &= tpmsk;
iop->psor = (iop->psor & tpmsk) | psor;
iop->podr = (iop->podr & tpmsk) | podr;
iop->pdat = (iop->pdat & tpmsk) | pdat;
iop->pdir = (iop->pdir & tpmsk) | pdir;
iop->ppar |= ppar;
}
}
}
void spi_cs_activate(struct spi_slave *slave)
{
volatile ioport_t *iopd = ioport_addr((immap_t *)CFG_IMMR, 3 /* port D */);
iopd->pdat &= ~cs_mask[slave->cs];
}