/**
* ti_gpio_detach - detach function for the driver
* @dev: scm device handle
*
* Allocates and sets up the driver context, this simply entails creating a
* bus mappings for the SCM register set.
*
* LOCKING:
* None
*
* RETURNS:
* Always returns 0
*/
static int
ti_gpio_detach(device_t dev)
{
struct ti_gpio_softc *sc = device_get_softc(dev);
unsigned int i;
KASSERT(mtx_initialized(&sc->sc_mtx), ("gpio mutex not initialized"));
/* Disable all interrupts */
for (i = 0; i < MAX_GPIO_BANKS; i++) {
if (sc->sc_mem_res[i] != NULL)
ti_gpio_intr_clr(sc, i, 0xffffffff);
}
bus_generic_detach(dev);
/* Release the memory and IRQ resources. */
ti_gpio_detach_intr(dev);
bus_release_resources(dev, ti_gpio_irq_spec, sc->sc_irq_res);
bus_release_resources(dev, ti_gpio_mem_spec, sc->sc_mem_res);
TI_GPIO_LOCK_DESTROY(sc);
return (0);
}
static inline void
ti_gpio_isrc_mask(struct ti_gpio_softc *sc, struct ti_gpio_irqsrc *tgi)
{
/* Writing a 0 has no effect. */
ti_gpio_intr_clr(sc, tgi->tgi_mask);
}
/**
* ti_gpio_detach - detach function for the driver
* @dev: scm device handle
*
* Allocates and sets up the driver context, this simply entails creating a
* bus mappings for the SCM register set.
*
* LOCKING:
* None
*
* RETURNS:
* Always returns 0
*/
static int
ti_gpio_detach(device_t dev)
{
struct ti_gpio_softc *sc = device_get_softc(dev);
KASSERT(mtx_initialized(&sc->sc_mtx), ("gpio mutex not initialized"));
/* Disable all interrupts */
if (sc->sc_mem_res != NULL)
ti_gpio_intr_clr(sc, 0xffffffff);
gpiobus_detach_bus(dev);
if (sc->sc_isrcs != NULL)
ti_gpio_pic_detach(sc);
/* Release the memory and IRQ resources. */
if (sc->sc_irq_hdl) {
bus_teardown_intr(dev, sc->sc_irq_res,
sc->sc_irq_hdl);
}
bus_release_resource(dev, SYS_RES_IRQ, sc->sc_irq_rid,
sc->sc_irq_res);
bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_mem_rid,
sc->sc_mem_res);
TI_GPIO_LOCK_DESTROY(sc);
return (0);
}
static int
ti_gpio_bank_init(device_t dev)
{
int pin;
struct ti_gpio_softc *sc;
uint32_t flags, reg_oe, reg_set, rev;
clk_ident_t clk;
sc = device_get_softc(dev);
/* Enable the interface and functional clocks for the module. */
clk = ti_hwmods_get_clock(dev);
if (clk == INVALID_CLK_IDENT) {
device_printf(dev, "failed to get device id based on ti,hwmods\n");
return (EINVAL);
}
sc->sc_bank = clk - GPIO1_CLK + ti_first_gpio_bank();
ti_prcm_clk_enable(clk);
/*
* Read the revision number of the module. TI don't publish the
* actual revision numbers, so instead the values have been
* determined by experimentation.
*/
rev = ti_gpio_read_4(sc, TI_GPIO_REVISION);
/* Check the revision. */
if (rev != ti_gpio_rev()) {
device_printf(dev, "Warning: could not determine the revision "
"of GPIO module (revision:0x%08x)\n", rev);
return (EINVAL);
}
/* Disable interrupts for all pins. */
ti_gpio_intr_clr(sc, 0xffffffff);
/* Init OE register based on pads configuration. */
reg_oe = 0xffffffff;
reg_set = 0;
for (pin = 0; pin < PINS_PER_BANK; pin++) {
TI_GPIO_GET_FLAGS(dev, pin, &flags);
if (flags & GPIO_PIN_OUTPUT) {
reg_oe &= ~(1UL << pin);
if (flags & GPIO_PIN_PULLUP)
reg_set |= (1UL << pin);
}
}
ti_gpio_write_4(sc, TI_GPIO_OE, reg_oe);
if (reg_set)
ti_gpio_write_4(sc, TI_GPIO_SETDATAOUT, reg_set);
return (0);
}
static void
ti_gpio_mask_irq_internal(struct ti_gpio_softc *sc, int irq)
{
uint32_t reg, val;
if (ti_gpio_valid_pin(sc, irq) != 0)
return;
TI_GPIO_LOCK(sc);
ti_gpio_intr_clr(sc, TI_GPIO_MASK(irq));
reg = ti_gpio_intr_reg(sc, irq);
if (reg != 0) {
val = ti_gpio_read_4(sc, reg);
val &= ~TI_GPIO_MASK(irq);
ti_gpio_write_4(sc, reg, val);
}
TI_GPIO_UNLOCK(sc);
}
static int
ti_gpio_bank_init(device_t dev, int bank)
{
int pin;
struct ti_gpio_softc *sc;
uint32_t flags, reg_oe;
sc = device_get_softc(dev);
/* Enable the interface and functional clocks for the module. */
ti_prcm_clk_enable(GPIO0_CLK + FIRST_GPIO_BANK + bank);
/*
* Read the revision number of the module. TI don't publish the
* actual revision numbers, so instead the values have been
* determined by experimentation.
*/
sc->sc_revision[bank] = ti_gpio_read_4(sc, bank, TI_GPIO_REVISION);
/* Check the revision. */
if (sc->sc_revision[bank] != TI_GPIO_REV) {
device_printf(dev, "Warning: could not determine the revision "
"of %u GPIO module (revision:0x%08x)\n",
bank, sc->sc_revision[bank]);
return (EINVAL);
}
/* Disable interrupts for all pins. */
ti_gpio_intr_clr(sc, bank, 0xffffffff);
/* Init OE register based on pads configuration. */
reg_oe = 0xffffffff;
for (pin = 0; pin < PINS_PER_BANK; pin++) {
ti_scm_padconf_get_gpioflags(PINS_PER_BANK * bank + pin,
&flags);
if (flags & GPIO_PIN_OUTPUT)
reg_oe &= ~(1UL << pin);
}
ti_gpio_write_4(sc, bank, TI_GPIO_OE, reg_oe);
return (0);
}
