void DEX_PASS_MGR::perform_scalar_opt(OPT_CTX & oc)
{
LIST<IR_OPT*> opt_list; //A list of optimization.
IR_SSA_MGR * ssamgr = (IR_SSA_MGR*)register_opt(OPT_SSA_MGR);
bool is_ssa_avail = false;
if (ssamgr != NULL) {
is_ssa_avail = ssamgr->is_ssa_construct();
}
opt_list.append_tail(register_opt(OPT_CP));
opt_list.append_tail(register_opt(OPT_DCE));
opt_list.append_tail(register_opt(OPT_RP));
opt_list.append_tail(register_opt(OPT_CP));
opt_list.append_tail(register_opt(OPT_DCE));
opt_list.append_tail(register_opt(OPT_RP));
opt_list.append_tail(register_opt(OPT_CP));
opt_list.append_tail(register_opt(OPT_DCE));
opt_list.append_tail(register_opt(OPT_LOOP_CVT));
opt_list.append_tail(register_opt(OPT_LICM));
opt_list.append_tail(register_opt(OPT_GCSE));
((IR_DCE*)register_opt(OPT_DCE))->set_elim_cfs(false);
((IR_DCE*)register_opt(OPT_DCE))->set_ssa_available(is_ssa_avail);
if (opt_list.get_elem_count() != 0) {
LOG("\tScalar optimizations for '%s'", m_ru->get_ru_name());
}
bool change;
UINT count = 0;
//do {
change = false;
for (IR_OPT * opt = opt_list.get_head();
opt != NULL; opt = opt_list.get_next()) {
CHAR const* optn = opt->get_opt_name();
LOG("\t\tpass %s", optn);
IS_TRUE0(verify_ir_and_bb(m_ru->get_bb_list(), m_dm));
ULONGLONG t = getusec();
//dump_bbs(m_ru->get_bb_list(), "before");
//m_ru->get_cfg()->dump_vcg("before.vcg");
bool doit = opt->perform(oc);
//dump_bbs(m_ru->get_bb_list(), "after");
//m_ru->get_cfg()->dump_vcg("after.vcg");
append_ti(opt->get_opt_name(), getusec() - t);
if (doit) {
LOG("\t\t\tchanged");
change = true;
IS_TRUE0(verify_ir_and_bb(m_ru->get_bb_list(), m_dm));
IS_TRUE0(m_ru->get_cfg()->verify());
}
}
count++;
//} while (change && count < 20);
//IS_TRUE0(!change);
}
void DEX_REGION::process_simply(OUT PRNO2UINT & prno2v, UINT param_num,
UINT vregnum, DEX2IR & d2ir, UINT2PR * v2pr,
IN PRNO2UINT * pr2v, TYIDR * tr)
{
LOG("\t\t Invoke DEX_REGION::process_simply '%s'", get_ru_name());
if (get_ir_list() == NULL) { return ; }
OPT_CTX oc;
OPTC_show_comp_time(oc) = g_show_comp_time;
CHAR const* ru_name = get_ru_name();
construct_ir_bb_list();
IS_TRUE0(verify_ir_and_bb(get_bb_list(), get_dm()));
RU_ana(this)->m_ir_list = NULL; //All IRs have been moved to each IR_BB.
IR_CFG * cfg = init_cfg(oc);
cfg->loop_analysis(oc);
PASS_MGR * pm = new_pass_mgr();
OPTC_pass_mgr(oc) = pm; //record pass manager.
if (g_do_ssa && OPTC_pass_mgr(oc) != NULL) {
//Convert program to ssa form.
IR_SSA_MGR * ssamgr = (IR_SSA_MGR*)OPTC_pass_mgr(oc)->
register_opt(OPT_SSA_MGR);
IS_TRUE0(ssamgr);
ssamgr->construction(oc, this);
}
init_aa(oc);
init_du(oc);
IR_SSA_MGR * ssamgr = (IR_SSA_MGR*)pm->query_opt(OPT_SSA_MGR);
if (ssamgr != NULL && ssamgr->is_ssa_construct()) {
//Destruct ssa form.
ssamgr->destruction_in_bblist_order();
}
delete pm;
OPTC_pass_mgr(oc) = NULL;
#if 1
//Do not allocate register.
prno2v.clean();
prno2v.copy(*d2ir.get_pr2v_map());
return;
#else
//Allocate register.
RA ra(this, tr, param_num, vregnum, v2pr, pr2v, &m_var2pr);
LOG("\t\tdo DEX Register Allcation for '%s'", ru_name);
ra.perform(oc);
update_ra_res(ra, prno2v);
#endif
}
void DEX_REGION::process(OUT PRNO2UINT & prno2v, UINT param_num, UINT vregnum,
UINT2PR * v2pr, IN PRNO2UINT * pr2v, TYIDR * tr)
{
if (get_ir_list() == NULL) { return; }
OPT_CTX oc;
OPTC_show_comp_time(oc) = g_show_comp_time;
g_indent = 0;
note("\n==---- REGION_NAME:%s ----==", get_ru_name());
prescan(get_ir_list());
RU_is_pr_unique_for_same_no(this) = true;
//g_do_ssa = true;
PASS_MGR * pm = new_pass_mgr();
OPTC_pass_mgr(oc) = pm;
high_process(oc);
middle_process(oc);
IR_SSA_MGR * ssamgr = (IR_SSA_MGR*)pm->query_opt(OPT_SSA_MGR);
if (ssamgr != NULL && ssamgr->is_ssa_construct()) {
ssamgr->destruction_in_bblist_order();
}
delete pm;
OPTC_pass_mgr(oc) = NULL;
if (RU_type(this) != RU_FUNC) { return; }
IR_BB_LIST * bbl = get_bb_list();
if (bbl->get_elem_count() == 0) { return; }
IS_TRUE0(verify_ir_and_bb(bbl, get_dm()));
RF_CTX rf;
RC_insert_cvt(rf) = false; //Do not insert cvt for DEX code.
refine_ir_bb_list(bbl, rf);
IS_TRUE0(verify_ir_and_bb(bbl, get_dm()));
RA ra(this, tr, param_num, vregnum, v2pr, pr2v, &m_var2pr);
LOG("\t\tdo DEX Register Allcation for '%s'", get_ru_name());
ra.perform(oc);
update_ra_res(ra, prno2v);
}
/*
Perform general optimizaitions.
Basis step to do:
1. Build control flow.
2. Compute data flow dependence.
3. Compute live expression info.
Optimizations to be performed:
1. GCSE
2. DCE
3. RVI(register variable recog)
4. IVR(induction variable elimination)
5. CP(constant propagation)
6. CP(copy propagation)
7. SCCP (Sparse Conditional Constant Propagation).
8. PRE (Partial Redundancy Elimination) with strength reduction.
9. Dominator-based optimizations such as copy propagation,
constant propagation and redundancy elimination using
value numbering.
10. Must-alias analysis, to convert pointer de-references
into regular variable references whenever possible.
11. Scalar Replacement of Aggregates, to convert structure
references into scalar references that can be optimized
using the standard scalar passes.
*/
bool REGION::middle_process(OPT_CTX & oc)
{
if (g_opt_level == NO_OPT) { return false; }
g_indent = 0;
CHAR const* runame = get_ru_name();
PASS_MGR * passmgr = OPTC_pass_mgr(oc);
IS_TRUE0(passmgr);
IR_SSA_MGR * ssamgr = (IR_SSA_MGR*)passmgr->query_opt(OPT_SSA_MGR);
if (ssamgr == NULL || !ssamgr->is_ssa_construct()) {
lower_to_do_scalar_opt(*this, oc);
}
//Perform scalar optimizations.
OPTC_pass_mgr(oc)->perform_scalar_opt(oc);
return true;
}
