void Mips16DAGToDAGISel::getMips16SPRefReg(SDNode *Parent, SDValue &AliasReg) {
SDValue AliasFPReg = CurDAG->getRegister(Mips::S0,
getTargetLowering()->getPointerTy());
if (Parent) {
switch (Parent->getOpcode()) {
case ISD::LOAD: {
LoadSDNode *SD = dyn_cast<LoadSDNode>(Parent);
switch (SD->getMemoryVT().getSizeInBits()) {
case 8:
case 16:
AliasReg = TM.getFrameLowering()->hasFP(*MF)?
AliasFPReg: getMips16SPAliasReg();
return;
}
break;
}
case ISD::STORE: {
StoreSDNode *SD = dyn_cast<StoreSDNode>(Parent);
switch (SD->getMemoryVT().getSizeInBits()) {
case 8:
case 16:
AliasReg = TM.getFrameLowering()->hasFP(*MF)?
AliasFPReg: getMips16SPAliasReg();
return;
}
break;
}
}
}
AliasReg = CurDAG->getRegister(Mips::SP, getTargetLowering()->getPointerTy());
return;
}
/// getPostIndexedAddressParts - returns true by value, base pointer and
/// offset pointer and addressing mode by reference if this node can be
/// combined with a load / store to form a post-indexed load / store.
bool MSP430TargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
SDValue &Base,
SDValue &Offset,
ISD::MemIndexedMode &AM,
SelectionDAG &DAG) const {
LoadSDNode *LD = cast<LoadSDNode>(N);
if (LD->getExtensionType() != ISD::NON_EXTLOAD)
return false;
EVT VT = LD->getMemoryVT();
if (VT != MVT::i8 && VT != MVT::i16)
return false;
if (Op->getOpcode() != ISD::ADD)
return false;
if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Op->getOperand(1))) {
uint64_t RHSC = RHS->getZExtValue();
if ((VT == MVT::i16 && RHSC != 2) ||
(VT == MVT::i8 && RHSC != 1))
return false;
Base = Op->getOperand(0);
Offset = DAG.getConstant(RHSC, VT);
AM = ISD::POST_INC;
return true;
}
return false;
}
void DAGTypeLegalizer::ExpandRes_NormalLoad(SDNode *N, SDValue &Lo,
SDValue &Hi) {
assert(ISD::isNormalLoad(N) && "This routine only for normal loads!");
SDLoc dl(N);
LoadSDNode *LD = cast<LoadSDNode>(N);
EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), LD->getValueType(0));
SDValue Chain = LD->getChain();
SDValue Ptr = LD->getBasePtr();
unsigned Alignment = LD->getAlignment();
bool isVolatile = LD->isVolatile();
bool isNonTemporal = LD->isNonTemporal();
bool isInvariant = LD->isInvariant();
assert(NVT.isByteSized() && "Expanded type not byte sized!");
Lo = DAG.getLoad(NVT, dl, Chain, Ptr, LD->getPointerInfo(),
isVolatile, isNonTemporal, isInvariant, Alignment);
// Increment the pointer to the other half.
unsigned IncrementSize = NVT.getSizeInBits() / 8;
Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
DAG.getIntPtrConstant(IncrementSize));
Hi = DAG.getLoad(NVT, dl, Chain, Ptr,
LD->getPointerInfo().getWithOffset(IncrementSize),
isVolatile, isNonTemporal, isInvariant,
MinAlign(Alignment, IncrementSize));
// Build a factor node to remember that this load is independent of the
// other one.
Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
Hi.getValue(1));
// Handle endianness of the load.
if (TLI.isBigEndian())
std::swap(Lo, Hi);
// Modified the chain - switch anything that used the old chain to use
// the new one.
ReplaceValueWith(SDValue(N, 1), Chain);
}
// Select - Convert the specified operand from a target-independent to a
// target-specific node if it hasn't already been changed.
SDNode *IA64DAGToDAGISel::Select(SDValue Op) {
SDNode *N = Op.getNode();
if (N->isMachineOpcode())
return NULL; // Already selected.
DebugLoc dl = Op.getDebugLoc();
switch (N->getOpcode()) {
default:
break;
case IA64ISD::BRCALL: { // XXX: this is also a hack!
SDValue Chain = N->getOperand(0);
SDValue InFlag; // Null incoming flag value.
if(N->getNumOperands()==3) { // we have an incoming chain, callee and flag
InFlag = N->getOperand(2);
}
unsigned CallOpcode;
SDValue CallOperand;
// if we can call directly, do so
if (GlobalAddressSDNode *GASD =
dyn_cast<GlobalAddressSDNode>(N->getOperand(1))) {
CallOpcode = IA64::BRCALL_IPREL_GA;
CallOperand = CurDAG->getTargetGlobalAddress(GASD->getGlobal(), MVT::i64);
} else if (isa<ExternalSymbolSDNode>(N->getOperand(1))) {
// FIXME: we currently NEED this case for correctness, to avoid
// "non-pic code with imm reloc.n against dynamic symbol" errors
CallOpcode = IA64::BRCALL_IPREL_ES;
CallOperand = N->getOperand(1);
} else {
// otherwise we need to load the function descriptor,
// load the branch target (function)'s entry point and GP,
// branch (call) then restore the GP
SDValue FnDescriptor = N->getOperand(1);
// load the branch target's entry point [mem] and
// GP value [mem+8]
SDValue targetEntryPoint=
SDValue(CurDAG->getTargetNode(IA64::LD8, dl, MVT::i64, MVT::Other,
FnDescriptor, CurDAG->getEntryNode()), 0);
Chain = targetEntryPoint.getValue(1);
SDValue targetGPAddr=
SDValue(CurDAG->getTargetNode(IA64::ADDS, dl, MVT::i64,
FnDescriptor,
CurDAG->getConstant(8, MVT::i64)), 0);
Chain = targetGPAddr.getValue(1);
SDValue targetGP =
SDValue(CurDAG->getTargetNode(IA64::LD8, dl, MVT::i64,MVT::Other,
targetGPAddr, CurDAG->getEntryNode()), 0);
Chain = targetGP.getValue(1);
Chain = CurDAG->getCopyToReg(Chain, dl, IA64::r1, targetGP, InFlag);
InFlag = Chain.getValue(1);
Chain = CurDAG->getCopyToReg(Chain, dl, IA64::B6,
targetEntryPoint, InFlag); // FLAG these?
InFlag = Chain.getValue(1);
CallOperand = CurDAG->getRegister(IA64::B6, MVT::i64);
CallOpcode = IA64::BRCALL_INDIRECT;
}
// Finally, once everything is setup, emit the call itself
if (InFlag.getNode())
Chain = SDValue(CurDAG->getTargetNode(CallOpcode, dl, MVT::Other,
MVT::Flag, CallOperand, InFlag), 0);
else // there might be no arguments
Chain = SDValue(CurDAG->getTargetNode(CallOpcode, dl, MVT::Other,
MVT::Flag, CallOperand, Chain), 0);
InFlag = Chain.getValue(1);
std::vector<SDValue> CallResults;
CallResults.push_back(Chain);
CallResults.push_back(InFlag);
for (unsigned i = 0, e = CallResults.size(); i != e; ++i)
ReplaceUses(Op.getValue(i), CallResults[i]);
return NULL;
}
case IA64ISD::GETFD: {
SDValue Input = N->getOperand(0);
return CurDAG->getTargetNode(IA64::GETFD, dl, MVT::i64, Input);
}
case ISD::FDIV:
case ISD::SDIV:
case ISD::UDIV:
case ISD::SREM:
case ISD::UREM:
return SelectDIV(Op);
case ISD::TargetConstantFP: {
SDValue Chain = CurDAG->getEntryNode(); // this is a constant, so..
SDValue V;
ConstantFPSDNode* N2 = cast<ConstantFPSDNode>(N);
if (N2->getValueAPF().isPosZero()) {
V = CurDAG->getCopyFromReg(Chain, dl, IA64::F0, MVT::f64);
} else if (N2->isExactlyValue(N2->getValueType(0) == MVT::f32 ?
APFloat(+1.0f) : APFloat(+1.0))) {
V = CurDAG->getCopyFromReg(Chain, dl, IA64::F1, MVT::f64);
} else
assert(0 && "Unexpected FP constant!");
ReplaceUses(SDValue(N, 0), V);
return 0;
}
case ISD::FrameIndex: { // TODO: reduce creepyness
int FI = cast<FrameIndexSDNode>(N)->getIndex();
if (N->hasOneUse())
return CurDAG->SelectNodeTo(N, IA64::MOV, MVT::i64,
CurDAG->getTargetFrameIndex(FI, MVT::i64));
else
return CurDAG->getTargetNode(IA64::MOV, dl, MVT::i64,
CurDAG->getTargetFrameIndex(FI, MVT::i64));
}
case ISD::ConstantPool: { // TODO: nuke the constant pool
// (ia64 doesn't need one)
ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(N);
Constant *C = CP->getConstVal();
SDValue CPI = CurDAG->getTargetConstantPool(C, MVT::i64,
CP->getAlignment());
return CurDAG->getTargetNode(IA64::ADDL_GA, dl, MVT::i64, // ?
CurDAG->getRegister(IA64::r1, MVT::i64), CPI);
}
case ISD::GlobalAddress: {
GlobalValue *GV = cast<GlobalAddressSDNode>(N)->getGlobal();
SDValue GA = CurDAG->getTargetGlobalAddress(GV, MVT::i64);
SDValue Tmp =
SDValue(CurDAG->getTargetNode(IA64::ADDL_GA, dl, MVT::i64,
CurDAG->getRegister(IA64::r1,
MVT::i64), GA), 0);
return CurDAG->getTargetNode(IA64::LD8, dl, MVT::i64, MVT::Other, Tmp,
CurDAG->getEntryNode());
}
/* XXX
case ISD::ExternalSymbol: {
SDValue EA = CurDAG->getTargetExternalSymbol(
cast<ExternalSymbolSDNode>(N)->getSymbol(),
MVT::i64);
SDValue Tmp = CurDAG->getTargetNode(IA64::ADDL_EA, dl, MVT::i64,
CurDAG->getRegister(IA64::r1,
MVT::i64),
EA);
return CurDAG->getTargetNode(IA64::LD8, dl, MVT::i64, Tmp);
}
*/
case ISD::LOAD: { // FIXME: load -1, not 1, for bools?
LoadSDNode *LD = cast<LoadSDNode>(N);
SDValue Chain = LD->getChain();
SDValue Address = LD->getBasePtr();
MVT TypeBeingLoaded = LD->getMemoryVT();
unsigned Opc;
switch (TypeBeingLoaded.getSimpleVT()) {
default:
#ifndef NDEBUG
N->dump(CurDAG);
#endif
assert(0 && "Cannot load this type!");
case MVT::i1: { // this is a bool
Opc = IA64::LD1; // first we load a byte, then compare for != 0
if(N->getValueType(0) == MVT::i1) { // XXX: early exit!
return CurDAG->SelectNodeTo(N, IA64::CMPNE, MVT::i1, MVT::Other,
SDValue(CurDAG->getTargetNode(Opc, dl,
MVT::i64,
Address), 0),
CurDAG->getRegister(IA64::r0, MVT::i64),
Chain);
}
/* otherwise, we want to load a bool into something bigger: LD1
will do that for us, so we just fall through */
}
case MVT::i8:
Opc = IA64::LD1;
break;
case MVT::i16:
Opc = IA64::LD2;
break;
case MVT::i32:
Opc = IA64::LD4;
break;
case MVT::i64:
Opc = IA64::LD8;
break;
case MVT::f32:
Opc = IA64::LDF4;
break;
case MVT::f64:
Opc = IA64::LDF8;
break;
}
// TODO: comment this
return CurDAG->SelectNodeTo(N, Opc, N->getValueType(0), MVT::Other,
Address, Chain);
}
case ISD::STORE: {
StoreSDNode *ST = cast<StoreSDNode>(N);
SDValue Address = ST->getBasePtr();
SDValue Chain = ST->getChain();
unsigned Opc;
if (ISD::isNON_TRUNCStore(N)) {
switch (N->getOperand(1).getValueType().getSimpleVT()) {
default:
assert(0 && "unknown type in store");
case MVT::i1: { // this is a bool
Opc = IA64::ST1; // we store either 0 or 1 as a byte
// first load zero!
SDValue Initial = CurDAG->getCopyFromReg(Chain, dl, IA64::r0, MVT::i64);
Chain = Initial.getValue(1);
// then load 1 into the same reg iff the predicate to store is 1
SDValue Tmp = ST->getValue();
Tmp =
SDValue(CurDAG->getTargetNode(IA64::TPCADDS, dl, MVT::i64, Initial,
CurDAG->getTargetConstant(1,
MVT::i64),
Tmp), 0);
return CurDAG->SelectNodeTo(N, Opc, MVT::Other, Address, Tmp, Chain);
}
case MVT::i64:
Opc = IA64::ST8;
break;
case MVT::f64:
Opc = IA64::STF8;
break;
}
} else { // Truncating store
switch(ST->getMemoryVT().getSimpleVT()) {
default:
assert(0 && "unknown type in truncstore");
case MVT::i8:
Opc = IA64::ST1;
break;
case MVT::i16:
Opc = IA64::ST2;
break;
case MVT::i32:
Opc = IA64::ST4;
break;
case MVT::f32:
Opc = IA64::STF4;
break;
}
}
SDValue N1 = N->getOperand(1);
SDValue N2 = N->getOperand(2);
return CurDAG->SelectNodeTo(N, Opc, MVT::Other, N2, N1, Chain);
}
case ISD::BRCOND: {
SDValue Chain = N->getOperand(0);
SDValue CC = N->getOperand(1);
MachineBasicBlock *Dest =
cast<BasicBlockSDNode>(N->getOperand(2))->getBasicBlock();
//FIXME - we do NOT need long branches all the time
return CurDAG->SelectNodeTo(N, IA64::BRLCOND_NOTCALL, MVT::Other, CC,
CurDAG->getBasicBlock(Dest), Chain);
}
case ISD::CALLSEQ_START:
case ISD::CALLSEQ_END: {
int64_t Amt = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
unsigned Opc = N->getOpcode() == ISD::CALLSEQ_START ?
IA64::ADJUSTCALLSTACKDOWN : IA64::ADJUSTCALLSTACKUP;
SDValue N0 = N->getOperand(0);
return CurDAG->SelectNodeTo(N, Opc, MVT::Other, getI64Imm(Amt), N0);
}
case ISD::BR:
// FIXME: we don't need long branches all the time!
SDValue N0 = N->getOperand(0);
return CurDAG->SelectNodeTo(N, IA64::BRL_NOTCALL, MVT::Other,
N->getOperand(1), N0);
}
return SelectCode(Op);
}
SDNode *NVPTXDAGToDAGISel::SelectLoad(SDNode *N) {
DebugLoc dl = N->getDebugLoc();
LoadSDNode *LD = cast<LoadSDNode>(N);
EVT LoadedVT = LD->getMemoryVT();
SDNode *NVPTXLD = NULL;
// do not support pre/post inc/dec
if (LD->isIndexed())
return NULL;
if (!LoadedVT.isSimple())
return NULL;
// Address Space Setting
unsigned int codeAddrSpace = getCodeAddrSpace(LD, Subtarget);
// Volatile Setting
// - .volatile is only availalble for .global and .shared
bool isVolatile = LD->isVolatile();
if (codeAddrSpace != NVPTX::PTXLdStInstCode::GLOBAL &&
codeAddrSpace != NVPTX::PTXLdStInstCode::SHARED &&
codeAddrSpace != NVPTX::PTXLdStInstCode::GENERIC)
isVolatile = false;
// Vector Setting
MVT SimpleVT = LoadedVT.getSimpleVT();
unsigned vecType = NVPTX::PTXLdStInstCode::Scalar;
if (SimpleVT.isVector()) {
unsigned num = SimpleVT.getVectorNumElements();
if (num == 2)
vecType = NVPTX::PTXLdStInstCode::V2;
else if (num == 4)
vecType = NVPTX::PTXLdStInstCode::V4;
else
return NULL;
}
// Type Setting: fromType + fromTypeWidth
//
// Sign : ISD::SEXTLOAD
// Unsign : ISD::ZEXTLOAD, ISD::NON_EXTLOAD or ISD::EXTLOAD and the
// type is integer
// Float : ISD::NON_EXTLOAD or ISD::EXTLOAD and the type is float
MVT ScalarVT = SimpleVT.getScalarType();
unsigned fromTypeWidth = ScalarVT.getSizeInBits();
unsigned int fromType;
if ((LD->getExtensionType() == ISD::SEXTLOAD))
fromType = NVPTX::PTXLdStInstCode::Signed;
else if (ScalarVT.isFloatingPoint())
fromType = NVPTX::PTXLdStInstCode::Float;
else
fromType = NVPTX::PTXLdStInstCode::Unsigned;
// Create the machine instruction DAG
SDValue Chain = N->getOperand(0);
SDValue N1 = N->getOperand(1);
SDValue Addr;
SDValue Offset, Base;
unsigned Opcode;
MVT::SimpleValueType TargetVT = LD->getValueType(0).getSimpleVT().SimpleTy;
if (SelectDirectAddr(N1, Addr)) {
switch (TargetVT) {
case MVT::i8:
Opcode = NVPTX::LD_i8_avar;
break;
case MVT::i16:
Opcode = NVPTX::LD_i16_avar;
break;
case MVT::i32:
Opcode = NVPTX::LD_i32_avar;
break;
case MVT::i64:
Opcode = NVPTX::LD_i64_avar;
break;
case MVT::f32:
Opcode = NVPTX::LD_f32_avar;
break;
case MVT::f64:
Opcode = NVPTX::LD_f64_avar;
break;
default:
return NULL;
}
SDValue Ops[] = { getI32Imm(isVolatile), getI32Imm(codeAddrSpace),
getI32Imm(vecType), getI32Imm(fromType),
getI32Imm(fromTypeWidth), Addr, Chain };
NVPTXLD = CurDAG->getMachineNode(Opcode, dl, TargetVT, MVT::Other, Ops, 7);
} else if (Subtarget.is64Bit()
? SelectADDRsi64(N1.getNode(), N1, Base, Offset)
: SelectADDRsi(N1.getNode(), N1, Base, Offset)) {
switch (TargetVT) {
case MVT::i8:
Opcode = NVPTX::LD_i8_asi;
break;
case MVT::i16:
Opcode = NVPTX::LD_i16_asi;
break;
case MVT::i32:
Opcode = NVPTX::LD_i32_asi;
break;
case MVT::i64:
Opcode = NVPTX::LD_i64_asi;
break;
case MVT::f32:
Opcode = NVPTX::LD_f32_asi;
break;
case MVT::f64:
Opcode = NVPTX::LD_f64_asi;
break;
default:
return NULL;
}
SDValue Ops[] = { getI32Imm(isVolatile), getI32Imm(codeAddrSpace),
getI32Imm(vecType), getI32Imm(fromType),
getI32Imm(fromTypeWidth), Base, Offset, Chain };
NVPTXLD = CurDAG->getMachineNode(Opcode, dl, TargetVT, MVT::Other, Ops, 8);
} else if (Subtarget.is64Bit()
? SelectADDRri64(N1.getNode(), N1, Base, Offset)
: SelectADDRri(N1.getNode(), N1, Base, Offset)) {
if (Subtarget.is64Bit()) {
switch (TargetVT) {
case MVT::i8:
Opcode = NVPTX::LD_i8_ari_64;
break;
case MVT::i16:
Opcode = NVPTX::LD_i16_ari_64;
break;
case MVT::i32:
Opcode = NVPTX::LD_i32_ari_64;
break;
case MVT::i64:
Opcode = NVPTX::LD_i64_ari_64;
break;
case MVT::f32:
Opcode = NVPTX::LD_f32_ari_64;
break;
case MVT::f64:
Opcode = NVPTX::LD_f64_ari_64;
break;
default:
return NULL;
}
} else {
switch (TargetVT) {
case MVT::i8:
Opcode = NVPTX::LD_i8_ari;
break;
case MVT::i16:
Opcode = NVPTX::LD_i16_ari;
break;
case MVT::i32:
Opcode = NVPTX::LD_i32_ari;
break;
case MVT::i64:
Opcode = NVPTX::LD_i64_ari;
break;
case MVT::f32:
Opcode = NVPTX::LD_f32_ari;
break;
case MVT::f64:
Opcode = NVPTX::LD_f64_ari;
break;
default:
return NULL;
}
}
SDValue Ops[] = { getI32Imm(isVolatile), getI32Imm(codeAddrSpace),
getI32Imm(vecType), getI32Imm(fromType),
getI32Imm(fromTypeWidth), Base, Offset, Chain };
NVPTXLD = CurDAG->getMachineNode(Opcode, dl, TargetVT, MVT::Other, Ops, 8);
} else {
if (Subtarget.is64Bit()) {
switch (TargetVT) {
case MVT::i8:
Opcode = NVPTX::LD_i8_areg_64;
break;
case MVT::i16:
Opcode = NVPTX::LD_i16_areg_64;
break;
case MVT::i32:
Opcode = NVPTX::LD_i32_areg_64;
break;
case MVT::i64:
Opcode = NVPTX::LD_i64_areg_64;
break;
case MVT::f32:
Opcode = NVPTX::LD_f32_areg_64;
break;
case MVT::f64:
Opcode = NVPTX::LD_f64_areg_64;
break;
default:
return NULL;
}
} else {
switch (TargetVT) {
case MVT::i8:
Opcode = NVPTX::LD_i8_areg;
break;
case MVT::i16:
Opcode = NVPTX::LD_i16_areg;
break;
case MVT::i32:
Opcode = NVPTX::LD_i32_areg;
break;
case MVT::i64:
Opcode = NVPTX::LD_i64_areg;
break;
case MVT::f32:
Opcode = NVPTX::LD_f32_areg;
break;
case MVT::f64:
Opcode = NVPTX::LD_f64_areg;
break;
default:
return NULL;
}
}
SDValue Ops[] = { getI32Imm(isVolatile), getI32Imm(codeAddrSpace),
getI32Imm(vecType), getI32Imm(fromType),
getI32Imm(fromTypeWidth), N1, Chain };
NVPTXLD = CurDAG->getMachineNode(Opcode, dl, TargetVT, MVT::Other, Ops, 7);
}
if (NVPTXLD != NULL) {
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
cast<MachineSDNode>(NVPTXLD)->setMemRefs(MemRefs0, MemRefs0 + 1);
}
return NVPTXLD;
}
SDNode *MipsDAGToDAGISel::SelectLoadFp64(SDNode *N) {
MVT::SimpleValueType NVT =
N->getValueType(0).getSimpleVT().SimpleTy;
if (!Subtarget.isMips1() || NVT != MVT::f64)
return NULL;
LoadSDNode *LN = cast<LoadSDNode>(N);
if (LN->getExtensionType() != ISD::NON_EXTLOAD ||
LN->getAddressingMode() != ISD::UNINDEXED)
return NULL;
SDValue Chain = N->getOperand(0);
SDValue N1 = N->getOperand(1);
SDValue Offset0, Offset1, Base;
if (!SelectAddr(N1, Base, Offset0) ||
N1.getValueType() != MVT::i32)
return NULL;
MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
DebugLoc dl = N->getDebugLoc();
// The second load should start after for 4 bytes.
if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Offset0))
Offset1 = CurDAG->getTargetConstant(C->getSExtValue()+4, MVT::i32);
else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Offset0))
Offset1 = CurDAG->getTargetConstantPool(CP->getConstVal(),
MVT::i32,
CP->getAlignment(),
CP->getOffset()+4,
CP->getTargetFlags());
else
return NULL;
// Choose the offsets depending on the endianess
if (TM.getTargetData()->isBigEndian())
std::swap(Offset0, Offset1);
// Instead of:
// ldc $f0, X($3)
// Generate:
// lwc $f0, X($3)
// lwc $f1, X+4($3)
SDNode *LD0 = CurDAG->getMachineNode(Mips::LWC1, dl, MVT::f32,
MVT::Other, Base, Offset0, Chain);
SDValue Undef = SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,
dl, NVT), 0);
SDValue I0 = CurDAG->getTargetInsertSubreg(Mips::sub_fpeven, dl,
MVT::f64, Undef, SDValue(LD0, 0));
SDNode *LD1 = CurDAG->getMachineNode(Mips::LWC1, dl, MVT::f32,
MVT::Other, Base, Offset1, SDValue(LD0, 1));
SDValue I1 = CurDAG->getTargetInsertSubreg(Mips::sub_fpodd, dl,
MVT::f64, I0, SDValue(LD1, 0));
ReplaceUses(SDValue(N, 0), I1);
ReplaceUses(SDValue(N, 1), Chain);
cast<MachineSDNode>(LD0)->setMemRefs(MemRefs0, MemRefs0 + 1);
cast<MachineSDNode>(LD1)->setMemRefs(MemRefs0, MemRefs0 + 1);
return I1.getNode();
}
void VDAGToDAGISel::LowerMemAccessISel(SDNode *N, SelectionDAG &DAG,
bool isStore) {
LSBaseSDNode *LSNode = cast<LSBaseSDNode>(N);
// FIXME: Handle the index.
assert(LSNode->isUnindexed() && "Indexed load/store is not supported!");
EVT VT = LSNode->getMemoryVT();
unsigned VTSize = VT.getSizeInBits();
SDValue StoreVal = isStore ? cast<StoreSDNode>(LSNode)->getValue()
: DAG.getUNDEF(VT);
LLVMContext *Cntx = DAG.getContext();
EVT CmdVT = EVT::getIntegerVT(*Cntx, VFUMemBus::CMDWidth);
SDValue SDOps[] = {// The chain.
LSNode->getChain(),
// The Value to store (if any), and the address.
LSNode->getBasePtr(), StoreVal,
// Is load?
DAG.getTargetConstant(isStore, CmdVT),
// Byte enable.
DAG.getTargetConstant(getByteEnable(VT.getStoreSize()),
MVT::i8)
};
unsigned DataBusWidth = getFUDesc<VFUMemBus>()->getDataWidth();
MachineMemOperand *MemOp = LSNode->getMemOperand();
if (unsigned AS = MemOp->getPointerInfo().getAddrSpace()) {
VFInfo *VFI = DAG.getMachineFunction().getInfo<VFInfo>();
DataBusWidth = VFI->getBRamInfo(AS).ElemSizeInBytes * 8;
}
assert(DataBusWidth >= VTSize && "Unexpected large data!");
MVT DataBusVT =
EVT::getIntegerVT(*DAG.getContext(), DataBusWidth).getSimpleVT();
DebugLoc dl = N->getDebugLoc();
SDValue Result =
DAG.getMemIntrinsicNode(VTMISD::MemAccess, dl,
// Result and the chain.
DAG.getVTList(DataBusVT, MVT::Other),
// SDValue operands
SDOps, array_lengthof(SDOps),
// Memory operands.
LSNode->getMemoryVT(), MemOp);
if (isStore) {
DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1));
return;
}
SDValue Val = Result;
// Truncate the data bus, the system bus should place the valid data start
// from LSM.
if (DataBusWidth > VTSize)
Val = VTargetLowering::getTruncate(DAG, dl, Result, VTSize);
// Check if this an extend load.
LoadSDNode *LD = cast<LoadSDNode>(LSNode);
ISD::LoadExtType ExtType = LD->getExtensionType();
if (ExtType != ISD::NON_EXTLOAD) {
unsigned DstSize = LD->getValueSizeInBits(0);
Val = VTargetLowering::getExtend(DAG, dl, Val, DstSize,
ExtType == ISD::SEXTLOAD);
}
// Do we need to replace the result of the load operation?
SDValue NewValues[] = { Val, Result.getValue(1) };
DAG.ReplaceAllUsesWith(N, NewValues);
}
