libusb::device_handle::sptr libusb::device_handle::get_cached_handle(device::sptr dev){
static uhd::dict<libusb_device *, boost::weak_ptr<device_handle> > handles;
//lock for atomic access to static table above
static boost::mutex mutex;
boost::mutex::scoped_lock lock(mutex);
//not expired -> get existing handle
if (handles.has_key(dev->get()) and not handles[dev->get()].expired()){
return handles[dev->get()].lock();
}
//create a new cached handle
try{
sptr new_handle(new libusb_device_handle_impl(dev));
handles[dev->get()] = new_handle;
return new_handle;
}
catch(const uhd::exception &){
#ifdef UHD_PLATFORM_LINUX
UHD_MSG(error) <<
"USB open failed: insufficient permissions.\n"
"See the application notes for your device.\n"
<< std::endl;
#else
UHD_LOG << "USB open failed: device already claimed." << std::endl;
#endif
throw;
}
}
static void apply_fe_corrections(
uhd::property_tree::sptr sub_tree,
const uhd::fs_path &db_path,
const uhd::fs_path &fe_path,
const std::string &file_prefix,
const double lo_freq
){
//extract eeprom serial
const uhd::usrp::dboard_eeprom_t db_eeprom = sub_tree->access<uhd::usrp::dboard_eeprom_t>(db_path).get();
//make the calibration file path
const fs::path cal_data_path = fs::path(uhd::get_app_path()) / ".uhd" / "cal" / (file_prefix + db_eeprom.serial + ".csv");
UHD_MSG(status) << "Looking for FE correction at: " << cal_data_path.c_str() << "... ";
if (not fs::exists(cal_data_path)) {
UHD_MSG(status) << "Not found" << std::endl;
return;
}
UHD_MSG(status) << "Found, loading... ";
//parse csv file or get from cache
if (not fe_cal_cache.has_key(cal_data_path.string())){
std::ifstream cal_data(cal_data_path.string().c_str());
const uhd::csv::rows_type rows = uhd::csv::to_rows(cal_data);
bool read_data = false, skip_next = false;;
std::vector<fe_cal_t> datas;
BOOST_FOREACH(const uhd::csv::row_type &row, rows){
if (not read_data and not row.empty() and row[0] == "DATA STARTS HERE"){
read_data = true;
skip_next = true;
continue;
}
if (not read_data) continue;
if (skip_next){
skip_next = false;
continue;
}
fe_cal_t data;
std::sscanf(row[0].c_str(), "%lf" , &data.lo_freq);
std::sscanf(row[1].c_str(), "%lf" , &data.iq_corr_real);
std::sscanf(row[2].c_str(), "%lf" , &data.iq_corr_imag);
datas.push_back(data);
}
std::sort(datas.begin(), datas.end(), fe_cal_comp);
fe_cal_cache[cal_data_path.string()] = datas;
UHD_MSG(status) << "Loaded" << std::endl;
} else {
/***********************************************************************
* Find USRP N2XX with specified IP address and return type
**********************************************************************/
boost::uint32_t find_usrp(udp_simple::sptr udp_transport, bool check_rev) {
boost::uint32_t hw_rev;
bool found_it = false;
// If the user chooses to not care about the rev, simply check
// for the presence of a USRP N2XX.
boost::uint32_t cmd_id = (check_rev) ? GET_HW_REV_CMD
: USRP2_QUERY;
boost::uint32_t ack_id = (check_rev) ? GET_HW_REV_ACK
: USRP2_ACK;
const usrp2_fw_update_data_t *update_data_in = reinterpret_cast<const usrp2_fw_update_data_t *>(usrp2_update_data_in_mem);
usrp2_fw_update_data_t hw_info_pkt = usrp2_fw_update_data_t();
hw_info_pkt.proto_ver = htonx<boost::uint32_t>(USRP2_FW_PROTO_VERSION);
hw_info_pkt.id = htonx<boost::uint32_t>(cmd_id);
udp_transport->send(boost::asio::buffer(&hw_info_pkt, sizeof(hw_info_pkt)));
//Loop and receive until the timeout
size_t len = udp_transport->recv(boost::asio::buffer(usrp2_update_data_in_mem), UDP_TIMEOUT);
if(len > offsetof(usrp2_fw_update_data_t, data) and ntohl(update_data_in->id) == ack_id) {
hw_rev = ntohl(update_data_in->data.hw_rev);
if(filename_map.has_key(hw_rev)) {
std::cout << boost::format("Found %s.\n\n") % filename_map[hw_rev];
found_it = true;
}
else {
if(check_rev) throw std::runtime_error("Invalid revision found.");
else {
hw_rev = 0;
std::cout << "Found USRP N2XX." << std::endl;
found_it = true;
}
}
}
if(not found_it) throw std::runtime_error("No USRP N2XX found.");
return hw_rev;
}
/***********************************************************************
* Find USRP N2XX with specified IP address and return type
**********************************************************************/
boost::uint32_t find_usrp(udp_simple::sptr udp_transport){
boost::uint32_t hw_rev;
bool found_it = false;
const usrp2_fw_update_data_t *update_data_in = reinterpret_cast<const usrp2_fw_update_data_t *>(usrp2_update_data_in_mem);
usrp2_fw_update_data_t hw_info_pkt = usrp2_fw_update_data_t();
hw_info_pkt.proto_ver = htonx<boost::uint32_t>(USRP2_FW_PROTO_VERSION);
hw_info_pkt.id = htonx<boost::uint32_t>(GET_HW_REV_CMD);
udp_transport->send(boost::asio::buffer(&hw_info_pkt, sizeof(hw_info_pkt)));
//Loop and receive until the timeout
size_t len = udp_transport->recv(boost::asio::buffer(usrp2_update_data_in_mem), UDP_TIMEOUT);
if(len > offsetof(usrp2_fw_update_data_t, data) and ntohl(update_data_in->id) == GET_HW_REV_ACK){
hw_rev = ntohl(update_data_in->data.hw_rev);
if(filename_map.has_key(hw_rev)){
std::cout << boost::format("Found %s.\n\n") % filename_map[hw_rev];
found_it = true;
}
else throw std::runtime_error("Invalid revision found.");
}
if(not found_it) throw std::runtime_error("No USRP N2XX found.");
return hw_rev;
}
/***********************************************************************
* Tuning
**********************************************************************/
double sbx_xcvr::sbx_version3::set_lo_freq(dboard_iface::unit_t unit, double target_freq) {
UHD_LOGV(often) << boost::format(
"SBX tune: target frequency %f Mhz"
) % (target_freq/1e6) << std::endl;
//clip the input
target_freq = sbx_freq_range.clip(target_freq);
//map prescaler setting to mininmum integer divider (N) values (pg.18 prescaler)
static const uhd::dict<int, int> prescaler_to_min_int_div = map_list_of
(0,23) //adf4350_regs_t::PRESCALER_4_5
(1,75) //adf4350_regs_t::PRESCALER_8_9
;
//map rf divider select output dividers to enums
static const uhd::dict<int, adf4350_regs_t::rf_divider_select_t> rfdivsel_to_enum = map_list_of
(1, adf4350_regs_t::RF_DIVIDER_SELECT_DIV1)
(2, adf4350_regs_t::RF_DIVIDER_SELECT_DIV2)
(4, adf4350_regs_t::RF_DIVIDER_SELECT_DIV4)
(8, adf4350_regs_t::RF_DIVIDER_SELECT_DIV8)
(16, adf4350_regs_t::RF_DIVIDER_SELECT_DIV16)
;
double actual_freq, pfd_freq;
double ref_freq = self_base->get_iface()->get_clock_rate(unit);
int R=0, BS=0, N=0, FRAC=0, MOD=0;
int RFdiv = 1;
adf4350_regs_t::reference_divide_by_2_t T = adf4350_regs_t::REFERENCE_DIVIDE_BY_2_DISABLED;
adf4350_regs_t::reference_doubler_t D = adf4350_regs_t::REFERENCE_DOUBLER_DISABLED;
//Reference doubler for 50% duty cycle
// if ref_freq < 12.5MHz enable regs.reference_divide_by_2
if(ref_freq <= 12.5e6) D = adf4350_regs_t::REFERENCE_DOUBLER_ENABLED;
//increase RF divider until acceptable VCO frequency
double vco_freq = target_freq;
while (vco_freq < 2.2e9) {
vco_freq *= 2;
RFdiv *= 2;
}
//use 8/9 prescaler for vco_freq > 3 GHz (pg.18 prescaler)
adf4350_regs_t::prescaler_t prescaler = target_freq > 3e9 ? adf4350_regs_t::PRESCALER_8_9 : adf4350_regs_t::PRESCALER_4_5;
/*
* The goal here is to loop though possible R dividers,
* band select clock dividers, N (int) dividers, and FRAC
* (frac) dividers.
*
* Calculate the N and F dividers for each set of values.
* The loop exits when it meets all of the constraints.
* The resulting loop values are loaded into the registers.
*
* from pg.21
*
* f_pfd = f_ref*(1+D)/(R*(1+T))
* f_vco = (N + (FRAC/MOD))*f_pfd
* N = f_vco/f_pfd - FRAC/MOD = f_vco*((R*(T+1))/(f_ref*(1+D))) - FRAC/MOD
* f_rf = f_vco/RFdiv)
* f_actual = f_rf/2
*/
for(R = 1; R <= 1023; R+=1){
//PFD input frequency = f_ref/R ... ignoring Reference doubler/divide-by-2 (D & T)
pfd_freq = ref_freq*(1+D)/(R*(1+T));
//keep the PFD frequency at or below 25MHz (Loop Filter Bandwidth)
if (pfd_freq > 25e6) continue;
//ignore fractional part of tuning
N = int(std::floor(target_freq/pfd_freq));
//keep N > minimum int divider requirement
if (N < prescaler_to_min_int_div[prescaler]) continue;
for(BS=1; BS <= 255; BS+=1){
//keep the band select frequency at or below 100KHz
//constraint on band select clock
if (pfd_freq/BS > 100e3) continue;
goto done_loop;
}
} done_loop:
//Fractional-N calculation
MOD = 4095; //max fractional accuracy
FRAC = int((target_freq/pfd_freq - N)*MOD);
//Reference divide-by-2 for 50% duty cycle
// if R even, move one divide by 2 to to regs.reference_divide_by_2
if(R % 2 == 0){
T = adf4350_regs_t::REFERENCE_DIVIDE_BY_2_ENABLED;
R /= 2;
}
//actual frequency calculation
actual_freq = double((N + (double(FRAC)/double(MOD)))*ref_freq*(1+int(D))/(R*(1+int(T))));
UHD_LOGV(often)
<< boost::format("SBX Intermediates: ref=%0.2f, outdiv=%f, fbdiv=%f") % (ref_freq*(1+int(D))/(R*(1+int(T)))) % double(RFdiv*2) % double(N + double(FRAC)/double(MOD)) << std::endl
<< boost::format("SBX tune: R=%d, BS=%d, N=%d, FRAC=%d, MOD=%d, T=%d, D=%d, RFdiv=%d"
) % R % BS % N % FRAC % MOD % T % D % RFdiv << std::endl
<< boost::format("SBX Frequencies (MHz): REQ=%0.2f, ACT=%0.2f, VCO=%0.2f, PFD=%0.2f, BAND=%0.2f"
) % (target_freq/1e6) % (actual_freq/1e6) % (vco_freq/1e6) % (pfd_freq/1e6) % (pfd_freq/BS/1e6) << std::endl;
//load the register values
adf4350_regs_t regs;
if ((unit == dboard_iface::UNIT_TX) and (actual_freq == sbx_tx_lo_2dbm.clip(actual_freq)))
regs.output_power = adf4350_regs_t::OUTPUT_POWER_2DBM;
else
regs.output_power = adf4350_regs_t::OUTPUT_POWER_5DBM;
regs.frac_12_bit = FRAC;
regs.int_16_bit = N;
regs.mod_12_bit = MOD;
regs.clock_divider_12_bit = std::max(1, int(std::ceil(400e-6*pfd_freq/MOD)));
regs.feedback_select = adf4350_regs_t::FEEDBACK_SELECT_DIVIDED;
regs.clock_div_mode = adf4350_regs_t::CLOCK_DIV_MODE_RESYNC_ENABLE;
regs.prescaler = prescaler;
regs.r_counter_10_bit = R;
regs.reference_divide_by_2 = T;
regs.reference_doubler = D;
regs.band_select_clock_div = BS;
UHD_ASSERT_THROW(rfdivsel_to_enum.has_key(RFdiv));
regs.rf_divider_select = rfdivsel_to_enum[RFdiv];
//write the registers
//correct power-up sequence to write registers (5, 4, 3, 2, 1, 0)
int addr;
for(addr=5; addr>=0; addr--){
UHD_LOGV(often) << boost::format(
"SBX SPI Reg (0x%02x): 0x%08x"
) % addr % regs.get_reg(addr) << std::endl;
self_base->get_iface()->write_spi(
unit, spi_config_t::EDGE_RISE,
regs.get_reg(addr), 32
);
}
//return the actual frequency
UHD_LOGV(often) << boost::format(
"SBX tune: actual frequency %f Mhz"
) % (actual_freq/1e6) << std::endl;
return actual_freq;
}
/***********************************************************************
* Tuning
**********************************************************************/
double wbx_base::wbx_version4::set_lo_freq(dboard_iface::unit_t unit, double target_freq) {
//clip to tuning range
target_freq = wbx_v4_freq_range.clip(target_freq);
UHD_LOGV(often) << boost::format(
"WBX tune: target frequency %f Mhz"
) % (target_freq/1e6) << std::endl;
/*
* If the user sets 'mode_n=integer' in the tuning args, the user wishes to
* tune in Integer-N mode, which can result in better spur
* performance on some mixers. The default is fractional tuning.
*/
property_tree::sptr subtree = (unit == dboard_iface::UNIT_RX) ? self_base->get_rx_subtree()
: self_base->get_tx_subtree();
device_addr_t tune_args = subtree->access<device_addr_t>("tune_args").get();
bool is_int_n = boost::iequals(tune_args.get("mode_n",""), "integer");
//map prescaler setting to mininmum integer divider (N) values (pg.18 prescaler)
static const uhd::dict<int, int> prescaler_to_min_int_div = map_list_of
(0,23) //adf4351_regs_t::PRESCALER_4_5
(1,75) //adf4351_regs_t::PRESCALER_8_9
;
//map rf divider select output dividers to enums
static const uhd::dict<int, adf4351_regs_t::rf_divider_select_t> rfdivsel_to_enum = map_list_of
(1, adf4351_regs_t::RF_DIVIDER_SELECT_DIV1)
(2, adf4351_regs_t::RF_DIVIDER_SELECT_DIV2)
(4, adf4351_regs_t::RF_DIVIDER_SELECT_DIV4)
(8, adf4351_regs_t::RF_DIVIDER_SELECT_DIV8)
(16, adf4351_regs_t::RF_DIVIDER_SELECT_DIV16)
(32, adf4351_regs_t::RF_DIVIDER_SELECT_DIV32)
(64, adf4351_regs_t::RF_DIVIDER_SELECT_DIV64)
;
double reference_freq = self_base->get_iface()->get_clock_rate(unit);
//The mixer has a divide-by-2 stage on the LO port so the synthesizer
//frequency must 2x the target frequency
double synth_target_freq = target_freq * 2;
//TODO: Document why the following has to be true
bool div_resync_enabled = (target_freq > reference_freq);
adf4351_regs_t::prescaler_t prescaler =
synth_target_freq > 3e9 ? adf4351_regs_t::PRESCALER_8_9 : adf4351_regs_t::PRESCALER_4_5;
adf435x_tuning_constraints tuning_constraints;
tuning_constraints.force_frac0 = is_int_n;
tuning_constraints.band_sel_freq_max = 100e3;
tuning_constraints.ref_doubler_threshold = 12.5e6;
tuning_constraints.int_range = uhd::range_t(prescaler_to_min_int_div[prescaler], 4095);
tuning_constraints.pfd_freq_max = 25e6;
tuning_constraints.rf_divider_range = uhd::range_t(1, 64);
//When divider resync is enabled, a 180 deg phase error is introduced when syncing
//multiple WBX boards. Switching to fundamental mode works arounds this issue.
tuning_constraints.feedback_after_divider = div_resync_enabled;
double synth_actual_freq = 0;
adf435x_tuning_settings tuning_settings = tune_adf435x_synth(
synth_target_freq, reference_freq, tuning_constraints, synth_actual_freq);
//The mixer has a divide-by-2 stage on the LO port so the synthesizer
//actual_freq must /2 the synth_actual_freq
double actual_freq = synth_actual_freq / 2;
//load the register values
adf4351_regs_t regs;
if (unit == dboard_iface::UNIT_RX)
regs.output_power = (actual_freq == wbx_rx_lo_5dbm.clip(actual_freq)) ? adf4351_regs_t::OUTPUT_POWER_5DBM
: adf4351_regs_t::OUTPUT_POWER_2DBM;
else
regs.output_power = (actual_freq == wbx_tx_lo_5dbm.clip(actual_freq)) ? adf4351_regs_t::OUTPUT_POWER_5DBM
: adf4351_regs_t::OUTPUT_POWER_M1DBM;
regs.frac_12_bit = tuning_settings.frac_12_bit;
regs.int_16_bit = tuning_settings.int_16_bit;
regs.mod_12_bit = tuning_settings.mod_12_bit;
regs.clock_divider_12_bit = tuning_settings.clock_divider_12_bit;
regs.feedback_select = tuning_constraints.feedback_after_divider ?
adf4351_regs_t::FEEDBACK_SELECT_DIVIDED :
adf4351_regs_t::FEEDBACK_SELECT_FUNDAMENTAL;
regs.clock_div_mode = div_resync_enabled ?
adf4351_regs_t::CLOCK_DIV_MODE_RESYNC_ENABLE :
adf4351_regs_t::CLOCK_DIV_MODE_FAST_LOCK;
regs.prescaler = prescaler;
regs.r_counter_10_bit = tuning_settings.r_counter_10_bit;
regs.reference_divide_by_2 = tuning_settings.r_divide_by_2_en ?
adf4351_regs_t::REFERENCE_DIVIDE_BY_2_ENABLED :
adf4351_regs_t::REFERENCE_DIVIDE_BY_2_DISABLED;
regs.reference_doubler = tuning_settings.r_doubler_en ?
adf4351_regs_t::REFERENCE_DOUBLER_ENABLED :
adf4351_regs_t::REFERENCE_DOUBLER_DISABLED;
regs.band_select_clock_div = tuning_settings.band_select_clock_div;
UHD_ASSERT_THROW(rfdivsel_to_enum.has_key(tuning_settings.rf_divider));
regs.rf_divider_select = rfdivsel_to_enum[tuning_settings.rf_divider];
regs.ldf = is_int_n ?
adf4351_regs_t::LDF_INT_N :
adf4351_regs_t::LDF_FRAC_N;
//reset the N and R counter
regs.counter_reset = adf4351_regs_t::COUNTER_RESET_ENABLED;
self_base->get_iface()->write_spi(unit, spi_config_t::EDGE_RISE, regs.get_reg(2), 32);
regs.counter_reset = adf4351_regs_t::COUNTER_RESET_DISABLED;
//write the registers
//correct power-up sequence to write registers (5, 4, 3, 2, 1, 0)
int addr;
boost::uint16_t rx_id = self_base->get_rx_id().to_uint16();
std::string board_name = (rx_id == 0x0081) ? "WBX-120" : "WBX";
for(addr=5; addr>=0; addr--){
UHD_LOGV(often) << boost::format(
"%s SPI Reg (0x%02x): 0x%08x"
) % board_name.c_str() % addr % regs.get_reg(addr) << std::endl;
self_base->get_iface()->write_spi(
unit, spi_config_t::EDGE_RISE,
regs.get_reg(addr), 32
);
}
//return the actual frequency
UHD_LOGV(often) << boost::format(
"%s tune: actual frequency %f Mhz"
) % board_name.c_str() % (actual_freq/1e6) << std::endl;
return actual_freq;
}
/***********************************************************************
* Structors
**********************************************************************/
e100_impl::e100_impl(const uhd::device_addr_t &device_addr){
_tree = property_tree::make();
//setup the main interface into fpga
const std::string node = device_addr["node"];
_fpga_ctrl = e100_ctrl::make(node);
//read the eeprom so we can determine the hardware
_dev_i2c_iface = e100_ctrl::make_dev_i2c_iface(E100_I2C_DEV_NODE);
const mboard_eeprom_t mb_eeprom(*_dev_i2c_iface, mboard_eeprom_t::MAP_E100);
//determine the model string for this device
const std::string model = device_addr.get("model", mb_eeprom.get("model", ""));
if (not model_to_fpga_file_name.has_key(model)) throw uhd::runtime_error(str(boost::format(
"\n"
" The specified model string \"%s\" is not recognized.\n"
" Perhaps the EEPROM is uninitialized, missing, or damaged.\n"
" Or, a monitor is pirating the I2C address of the EEPROM.\n"
) % model));
//extract the fpga path and compute hash
const std::string default_fpga_file_name = model_to_fpga_file_name[model];
const std::string e100_fpga_image = find_image_path(device_addr.get("fpga", default_fpga_file_name));
const boost::uint32_t file_hash = boost::uint32_t(hash_fpga_file(e100_fpga_image));
//When the hash does not match:
// - close the device node
// - load the fpga bin file
// - re-open the device node
if (_fpga_ctrl->peek32(E100_REG_RB_MISC_TEST32) != file_hash){
_fpga_ctrl.reset();
e100_load_fpga(e100_fpga_image);
_fpga_ctrl = e100_ctrl::make(node);
}
//setup clock control here to ensure that the FPGA has a good clock before we continue
bool dboard_clocks_diff = true;
if (mb_eeprom.get("revision", "0") == "3") dboard_clocks_diff = false;
else if (mb_eeprom.get("revision", "0") == "4") dboard_clocks_diff = true;
else UHD_MSG(warning)
<< "Unknown E1XX revision number!\n"
<< "defaulting to differential dboard clocks to be safe.\n"
<< std::endl;
const double master_clock_rate = device_addr.cast<double>("master_clock_rate", E100_DEFAULT_CLOCK_RATE);
_aux_spi_iface = e100_ctrl::make_aux_spi_iface();
_clock_ctrl = e100_clock_ctrl::make(_aux_spi_iface, master_clock_rate, dboard_clocks_diff);
//Perform wishbone readback tests, these tests also write the hash
bool test_fail = false;
UHD_MSG(status) << "Performing wishbone readback test... " << std::flush;
for (size_t i = 0; i < 100; i++){
_fpga_ctrl->poke32(E100_REG_SR_MISC_TEST32, file_hash);
test_fail = _fpga_ctrl->peek32(E100_REG_RB_MISC_TEST32) != file_hash;
if (test_fail) break; //exit loop on any failure
}
UHD_MSG(status) << ((test_fail)? " fail" : "pass") << std::endl;
if (test_fail) UHD_MSG(error) << boost::format(
"The FPGA is either clocked improperly\n"
"or the FPGA build is not compatible.\n"
"Subsequent errors may follow...\n"
);
//check that the compatibility is correct
this->check_fpga_compat();
////////////////////////////////////////////////////////////////////
// Create controller objects
////////////////////////////////////////////////////////////////////
_fpga_i2c_ctrl = i2c_core_100::make(_fpga_ctrl, E100_REG_SLAVE(3));
_fpga_spi_ctrl = spi_core_100::make(_fpga_ctrl, E100_REG_SLAVE(2));
_data_transport = e100_make_mmap_zero_copy(_fpga_ctrl);
////////////////////////////////////////////////////////////////////
// Initialize the properties tree
////////////////////////////////////////////////////////////////////
_tree->create<std::string>("/name").set("E-Series Device");
const fs_path mb_path = "/mboards/0";
_tree->create<std::string>(mb_path / "name").set(str(boost::format("%s (euewanee)") % model));
////////////////////////////////////////////////////////////////////
// setup the mboard eeprom
////////////////////////////////////////////////////////////////////
_tree->create<mboard_eeprom_t>(mb_path / "eeprom")
.set(mb_eeprom)
.subscribe(boost::bind(&e100_impl::set_mb_eeprom, this, _1));
////////////////////////////////////////////////////////////////////
// create clock control objects
////////////////////////////////////////////////////////////////////
//^^^ clock created up top, just reg props here... ^^^
_tree->create<double>(mb_path / "tick_rate")
.publish(boost::bind(&e100_clock_ctrl::get_fpga_clock_rate, _clock_ctrl))
.subscribe(boost::bind(&e100_impl::update_tick_rate, this, _1));
////////////////////////////////////////////////////////////////////
// create codec control objects
////////////////////////////////////////////////////////////////////
_codec_ctrl = e100_codec_ctrl::make(_fpga_spi_ctrl);
const fs_path rx_codec_path = mb_path / "rx_codecs/A";
const fs_path tx_codec_path = mb_path / "tx_codecs/A";
_tree->create<std::string>(rx_codec_path / "name").set("ad9522");
_tree->create<meta_range_t>(rx_codec_path / "gains/pga/range").set(e100_codec_ctrl::rx_pga_gain_range);
_tree->create<double>(rx_codec_path / "gains/pga/value")
.coerce(boost::bind(&e100_impl::update_rx_codec_gain, this, _1));
_tree->create<std::string>(tx_codec_path / "name").set("ad9522");
_tree->create<meta_range_t>(tx_codec_path / "gains/pga/range").set(e100_codec_ctrl::tx_pga_gain_range);
_tree->create<double>(tx_codec_path / "gains/pga/value")
.subscribe(boost::bind(&e100_codec_ctrl::set_tx_pga_gain, _codec_ctrl, _1))
.publish(boost::bind(&e100_codec_ctrl::get_tx_pga_gain, _codec_ctrl));
////////////////////////////////////////////////////////////////////
// and do the misc mboard sensors
////////////////////////////////////////////////////////////////////
_tree->create<sensor_value_t>(mb_path / "sensors/ref_locked")
.publish(boost::bind(&e100_impl::get_ref_locked, this));
////////////////////////////////////////////////////////////////////
// Create the GPSDO control
////////////////////////////////////////////////////////////////////
try{
_gps = gps_ctrl::make(e100_ctrl::make_gps_uart_iface(E100_UART_DEV_NODE));
}
catch(std::exception &e){
UHD_MSG(error) << "An error occurred making GPSDO control: " << e.what() << std::endl;
}
if (_gps.get() != NULL and _gps->gps_detected()){
BOOST_FOREACH(const std::string &name, _gps->get_sensors()){
_tree->create<sensor_value_t>(mb_path / "sensors" / name)
.publish(boost::bind(&gps_ctrl::get_sensor, _gps, name));
}
}
/***********************************************************************
* Structors
**********************************************************************/
e100_impl::e100_impl(const uhd::device_addr_t &device_addr){
_tree = property_tree::make();
_type = device::USRP;
_ignore_cal_file = device_addr.has_key("ignore-cal-file");
//read the eeprom so we can determine the hardware
_dev_i2c_iface = e100_ctrl::make_dev_i2c_iface(E100_I2C_DEV_NODE);
const mboard_eeprom_t mb_eeprom(*_dev_i2c_iface, E100_EEPROM_MAP_KEY);
//determine the model string for this device
const std::string model = device_addr.get("model", mb_eeprom.get("model", ""));
if (not model_to_fpga_file_name.has_key(model)) throw uhd::runtime_error(str(boost::format(
"\n"
" The specified model string \"%s\" is not recognized.\n"
" Perhaps the EEPROM is uninitialized, missing, or damaged.\n"
" Or, a monitor is pirating the I2C address of the EEPROM.\n"
) % model));
//extract the fpga path and compute hash
const std::string default_fpga_file_name = model_to_fpga_file_name[model];
std::string e100_fpga_image;
try{
e100_fpga_image = find_image_path(device_addr.get("fpga", default_fpga_file_name));
}
catch(...){
UHD_MSG(error) << boost::format("Could not find FPGA image. %s\n") % print_utility_error("uhd_images_downloader.py");
throw;
}
e100_load_fpga(e100_fpga_image);
////////////////////////////////////////////////////////////////////
// Setup the FPGA clock over AUX SPI
////////////////////////////////////////////////////////////////////
bool dboard_clocks_diff = true;
if (mb_eeprom.get("revision", "0") == "3") dboard_clocks_diff = false;
else if (mb_eeprom.get("revision", "0") == "4") dboard_clocks_diff = true;
else UHD_MSG(warning)
<< "Unknown E1XX revision number!\n"
<< "defaulting to differential dboard clocks to be safe.\n"
<< std::endl;
const double master_clock_rate = device_addr.cast<double>("master_clock_rate", E100_DEFAULT_CLOCK_RATE);
_aux_spi_iface = e100_ctrl::make_aux_spi_iface();
_clock_ctrl = e100_clock_ctrl::make(_aux_spi_iface, master_clock_rate, dboard_clocks_diff);
////////////////////////////////////////////////////////////////////
// setup the main interface into fpga
// - do this after aux spi, because we share gpio147
////////////////////////////////////////////////////////////////////
const std::string node = device_addr["node"];
_fpga_ctrl = e100_ctrl::make(node);
////////////////////////////////////////////////////////////////////
// Initialize FPGA control communication
////////////////////////////////////////////////////////////////////
fifo_ctrl_excelsior_config fifo_ctrl_config;
fifo_ctrl_config.async_sid_base = E100_TX_ASYNC_SID;
fifo_ctrl_config.num_async_chan = 1;
fifo_ctrl_config.ctrl_sid_base = E100_CTRL_MSG_SID;
fifo_ctrl_config.spi_base = TOREG(SR_SPI);
fifo_ctrl_config.spi_rb = REG_RB_SPI;
_fifo_ctrl = fifo_ctrl_excelsior::make(_fpga_ctrl, fifo_ctrl_config);
//Perform wishbone readback tests, these tests also write the hash
bool test_fail = false;
UHD_MSG(status) << "Performing control readback test... " << std::flush;
size_t hash = time(NULL);
for (size_t i = 0; i < 100; i++){
boost::hash_combine(hash, i);
_fifo_ctrl->poke32(TOREG(SR_MISC+0), boost::uint32_t(hash));
test_fail = _fifo_ctrl->peek32(REG_RB_CONFIG0) != boost::uint32_t(hash);
if (test_fail) break; //exit loop on any failure
}
UHD_MSG(status) << ((test_fail)? " fail" : "pass") << std::endl;
if (test_fail) UHD_MSG(error) << boost::format(
"The FPGA is either clocked improperly\n"
"or the FPGA build is not compatible.\n"
"Subsequent errors may follow...\n"
);
//check that the compatibility is correct
this->check_fpga_compat();
////////////////////////////////////////////////////////////////////
// Create controller objects
////////////////////////////////////////////////////////////////////
_fpga_i2c_ctrl = i2c_core_200::make(_fifo_ctrl, TOREG(SR_I2C), REG_RB_I2C);
_data_transport = e100_make_mmap_zero_copy(_fpga_ctrl);
////////////////////////////////////////////////////////////////////
// Initialize the properties tree
////////////////////////////////////////////////////////////////////
_tree->create<std::string>("/name").set("E-Series Device");
const fs_path mb_path = "/mboards/0";
_tree->create<std::string>(mb_path / "name").set(model);
_tree->create<std::string>(mb_path / "codename").set("Euwanee");
////////////////////////////////////////////////////////////////////
// setup the mboard eeprom
////////////////////////////////////////////////////////////////////
_tree->create<mboard_eeprom_t>(mb_path / "eeprom")
.set(mb_eeprom)
.subscribe(boost::bind(&e100_impl::set_mb_eeprom, this, _1));
////////////////////////////////////////////////////////////////////
// create clock control objects
////////////////////////////////////////////////////////////////////
//^^^ clock created up top, just reg props here... ^^^
_tree->create<double>(mb_path / "tick_rate")
.publish(boost::bind(&e100_clock_ctrl::get_fpga_clock_rate, _clock_ctrl))
.subscribe(boost::bind(&fifo_ctrl_excelsior::set_tick_rate, _fifo_ctrl, _1))
.subscribe(boost::bind(&e100_impl::update_tick_rate, this, _1));
//subscribe the command time while we are at it
_tree->create<time_spec_t>(mb_path / "time/cmd")
.subscribe(boost::bind(&fifo_ctrl_excelsior::set_time, _fifo_ctrl, _1));
////////////////////////////////////////////////////////////////////
// create codec control objects
////////////////////////////////////////////////////////////////////
_codec_ctrl = e100_codec_ctrl::make(_fifo_ctrl/*spi*/);
const fs_path rx_codec_path = mb_path / "rx_codecs/A";
const fs_path tx_codec_path = mb_path / "tx_codecs/A";
_tree->create<std::string>(rx_codec_path / "name").set("ad9522");
_tree->create<meta_range_t>(rx_codec_path / "gains/pga/range").set(e100_codec_ctrl::rx_pga_gain_range);
_tree->create<double>(rx_codec_path / "gains/pga/value")
.coerce(boost::bind(&e100_impl::update_rx_codec_gain, this, _1));
_tree->create<std::string>(tx_codec_path / "name").set("ad9522");
_tree->create<meta_range_t>(tx_codec_path / "gains/pga/range").set(e100_codec_ctrl::tx_pga_gain_range);
_tree->create<double>(tx_codec_path / "gains/pga/value")
.subscribe(boost::bind(&e100_codec_ctrl::set_tx_pga_gain, _codec_ctrl, _1))
.publish(boost::bind(&e100_codec_ctrl::get_tx_pga_gain, _codec_ctrl));
////////////////////////////////////////////////////////////////////
// and do the misc mboard sensors
////////////////////////////////////////////////////////////////////
_tree->create<sensor_value_t>(mb_path / "sensors/ref_locked")
.publish(boost::bind(&e100_impl::get_ref_locked, this));
////////////////////////////////////////////////////////////////////
// Create the GPSDO control
////////////////////////////////////////////////////////////////////
static const fs::path GPSDO_VOLATILE_PATH("/media/ram/e100_internal_gpsdo.cache");
if (not fs::exists(GPSDO_VOLATILE_PATH))
{
UHD_MSG(status) << "Detecting internal GPSDO.... " << std::flush;
try{
_gps = gps_ctrl::make(e100_ctrl::make_gps_uart_iface(E100_UART_DEV_NODE));
}
catch(std::exception &e){
UHD_MSG(error) << "An error occurred making GPSDO control: " << e.what() << std::endl;
}
if (_gps and _gps->gps_detected())
{
BOOST_FOREACH(const std::string &name, _gps->get_sensors())
{
_tree->create<sensor_value_t>(mb_path / "sensors" / name)
.publish(boost::bind(&gps_ctrl::get_sensor, _gps, name));
}
}
/***********************************************************************
* Tuning
**********************************************************************/
double sbx_xcvr::sbx_version3::set_lo_freq(dboard_iface::unit_t unit, double target_freq) {
UHD_LOGV(often) << boost::format(
"SBX tune: target frequency %f Mhz"
) % (target_freq/1e6) << std::endl;
//clip the input
target_freq = sbx_freq_range.clip(target_freq);
//map prescaler setting to mininmum integer divider (N) values (pg.18 prescaler)
static const uhd::dict<int, int> prescaler_to_min_int_div = map_list_of
(0,23) //adf4350_regs_t::PRESCALER_4_5
(1,75) //adf4350_regs_t::PRESCALER_8_9
;
//map rf divider select output dividers to enums
static const uhd::dict<int, adf4350_regs_t::rf_divider_select_t> rfdivsel_to_enum = map_list_of
(1, adf4350_regs_t::RF_DIVIDER_SELECT_DIV1)
(2, adf4350_regs_t::RF_DIVIDER_SELECT_DIV2)
(4, adf4350_regs_t::RF_DIVIDER_SELECT_DIV4)
(8, adf4350_regs_t::RF_DIVIDER_SELECT_DIV8)
(16, adf4350_regs_t::RF_DIVIDER_SELECT_DIV16)
;
//use 8/9 prescaler for vco_freq > 3 GHz (pg.18 prescaler)
adf4350_regs_t::prescaler_t prescaler = target_freq > 3e9 ? adf4350_regs_t::PRESCALER_8_9 : adf4350_regs_t::PRESCALER_4_5;
adf435x_tuning_constraints tuning_constraints;
tuning_constraints.force_frac0 = false;
tuning_constraints.band_sel_freq_max = 100e3;
tuning_constraints.ref_doubler_threshold = 12.5e6;
tuning_constraints.int_range = uhd::range_t(prescaler_to_min_int_div[prescaler], 4095); //INT is a 12-bit field
tuning_constraints.pfd_freq_max = 25e6;
tuning_constraints.rf_divider_range = uhd::range_t(1, 16);
double actual_freq;
adf435x_tuning_settings tuning_settings = _tune_adf435x_synth(
target_freq, self_base->get_iface()->get_clock_rate(unit),
tuning_constraints, actual_freq);
//load the register values
adf4350_regs_t regs;
if ((unit == dboard_iface::UNIT_TX) and (actual_freq == sbx_tx_lo_2dbm.clip(actual_freq)))
regs.output_power = adf4350_regs_t::OUTPUT_POWER_2DBM;
else
regs.output_power = adf4350_regs_t::OUTPUT_POWER_5DBM;
regs.frac_12_bit = tuning_settings.frac_12_bit;
regs.int_16_bit = tuning_settings.int_16_bit;
regs.mod_12_bit = tuning_settings.mod_12_bit;
regs.clock_divider_12_bit = tuning_settings.clock_divider_12_bit;
regs.feedback_select = tuning_settings.feedback_after_divider ?
adf4350_regs_t::FEEDBACK_SELECT_DIVIDED :
adf4350_regs_t::FEEDBACK_SELECT_FUNDAMENTAL;
regs.clock_div_mode = adf4350_regs_t::CLOCK_DIV_MODE_RESYNC_ENABLE;
regs.prescaler = prescaler;
regs.r_counter_10_bit = tuning_settings.r_counter_10_bit;
regs.reference_divide_by_2 = tuning_settings.r_divide_by_2_en ?
adf4350_regs_t::REFERENCE_DIVIDE_BY_2_ENABLED :
adf4350_regs_t::REFERENCE_DIVIDE_BY_2_DISABLED;
regs.reference_doubler = tuning_settings.r_doubler_en ?
adf4350_regs_t::REFERENCE_DOUBLER_ENABLED :
adf4350_regs_t::REFERENCE_DOUBLER_DISABLED;
regs.band_select_clock_div = tuning_settings.band_select_clock_div;
UHD_ASSERT_THROW(rfdivsel_to_enum.has_key(tuning_settings.rf_divider));
regs.rf_divider_select = rfdivsel_to_enum[tuning_settings.rf_divider];
//reset the N and R counter
regs.counter_reset = adf4350_regs_t::COUNTER_RESET_ENABLED;
self_base->get_iface()->write_spi(unit, spi_config_t::EDGE_RISE, regs.get_reg(2), 32);
regs.counter_reset = adf4350_regs_t::COUNTER_RESET_DISABLED;
//write the registers
//correct power-up sequence to write registers (5, 4, 3, 2, 1, 0)
int addr;
for(addr=5; addr>=0; addr--){
UHD_LOGV(often) << boost::format(
"SBX SPI Reg (0x%02x): 0x%08x"
) % addr % regs.get_reg(addr) << std::endl;
self_base->get_iface()->write_spi(
unit, spi_config_t::EDGE_RISE,
regs.get_reg(addr), 32
);
}
//return the actual frequency
UHD_LOGV(often) << boost::format(
"SBX tune: actual frequency %f Mhz"
) % (actual_freq/1e6) << std::endl;
return actual_freq;
}
