static void InitCBusRegs( void ) { SiiRegWrite(REG_CBUS_CFG, 0xF2); SiiRegWrite(REG_CBUS_CTRL1, 0x01); SiiRegWrite(REG_CBUS_CTRL2, 0x2D); SiiRegWrite(REG_CBUS_CTRL7, 0x0a); SiiRegWrite(REG_CBUS_DRV_STR0, 0x03); SiiRegWrite(REG_MSC_COMP_CTRL , 0x11); SiiRegWrite(REG_MSC_TIMEOUT_LIMIT, 0x0F); #define DEVCAP_REG(x) (REG_CBUS_DEVICE_CAP_0 | DEVCAP_OFFSET_##x) SiiRegWrite(DEVCAP_REG(DEV_STATE ) ,DEVCAP_VAL_DEV_STATE ); SiiRegWrite(DEVCAP_REG(MHL_VERSION ) ,DEVCAP_VAL_MHL_VERSION ); SiiRegWrite(DEVCAP_REG(DEV_CAT ) ,DEVCAP_VAL_DEV_CAT ); SiiRegWrite(DEVCAP_REG(ADOPTER_ID_H ) ,DEVCAP_VAL_ADOPTER_ID_H ); SiiRegWrite(DEVCAP_REG(ADOPTER_ID_L ) ,DEVCAP_VAL_ADOPTER_ID_L ); SiiRegWrite(DEVCAP_REG(VID_LINK_MODE ) ,DEVCAP_VAL_VID_LINK_MODE ); SiiRegWrite(DEVCAP_REG(AUD_LINK_MODE ) ,DEVCAP_VAL_AUD_LINK_MODE ); SiiRegWrite(DEVCAP_REG(VIDEO_TYPE ) ,DEVCAP_VAL_VIDEO_TYPE ); SiiRegWrite(DEVCAP_REG(LOG_DEV_MAP ) ,DEVCAP_VAL_LOG_DEV_MAP ); SiiRegWrite(DEVCAP_REG(BANDWIDTH ) ,DEVCAP_VAL_BANDWIDTH ); SiiRegWrite(DEVCAP_REG(FEATURE_FLAG ) ,DEVCAP_VAL_FEATURE_FLAG ); SiiRegWrite(DEVCAP_REG(DEVICE_ID_H ) ,DEVCAP_VAL_DEVICE_ID_H ); SiiRegWrite(DEVCAP_REG(DEVICE_ID_L ) ,DEVCAP_VAL_DEVICE_ID_L ); SiiRegWrite(DEVCAP_REG(SCRATCHPAD_SIZE) ,DEVCAP_VAL_SCRATCHPAD_SIZE ); SiiRegWrite(DEVCAP_REG(INT_STAT_SIZE ) ,DEVCAP_VAL_INT_STAT_SIZE ); SiiRegWrite(DEVCAP_REG(RESERVED ) ,DEVCAP_VAL_RESERVED ); }
/////////////////////////////////////////////////////////////////////////// // InitCBusRegs // /////////////////////////////////////////////////////////////////////////// static void InitCBusRegs (void) { TX_DEBUG_PRINT(("Drv: InitCBusRegs\n")); SiiRegWrite(REG_CBUS_COMMON_CONFIG, 0xF2); // Increase DDC translation layer timer SiiRegWrite(REG_CBUS_LINK_CONTROL_7, 0x0B); // Drive High Time. -- changed from 0x03 on 2011-11-21 -- changed from 0x0C on 2011-10-03 - 17:00 SiiRegWrite(REG_CBUS_LINK_CONTROL_8, 0x30); // Use programmed timing. SiiRegWrite(REG_CBUS_DRV_STRENGTH_0, 0x03); // CBUS Drive Strength #define DEVCAP_REG(x) (REG_CBUS_DEVICE_CAP_0 | DEVCAP_OFFSET_##x) // Setup our devcap SiiRegWrite(DEVCAP_REG(DEV_STATE ) ,DEVCAP_VAL_DEV_STATE ); SiiRegWrite(DEVCAP_REG(MHL_VERSION ) ,DEVCAP_VAL_MHL_VERSION ); SiiRegWrite(DEVCAP_REG(DEV_CAT ) ,DEVCAP_VAL_DEV_CAT ); SiiRegWrite(DEVCAP_REG(ADOPTER_ID_H ) ,DEVCAP_VAL_ADOPTER_ID_H ); SiiRegWrite(DEVCAP_REG(ADOPTER_ID_L ) ,DEVCAP_VAL_ADOPTER_ID_L ); SiiRegWrite(DEVCAP_REG(VID_LINK_MODE ) ,DEVCAP_VAL_VID_LINK_MODE ); SiiRegWrite(DEVCAP_REG(AUD_LINK_MODE ) ,DEVCAP_VAL_AUD_LINK_MODE ); SiiRegWrite(DEVCAP_REG(VIDEO_TYPE ) ,DEVCAP_VAL_VIDEO_TYPE ); SiiRegWrite(DEVCAP_REG(LOG_DEV_MAP ) ,DEVCAP_VAL_LOG_DEV_MAP ); SiiRegWrite(DEVCAP_REG(BANDWIDTH ) ,DEVCAP_VAL_BANDWIDTH ); SiiRegWrite(DEVCAP_REG(FEATURE_FLAG ) ,DEVCAP_VAL_FEATURE_FLAG ); SiiRegWrite(DEVCAP_REG(DEVICE_ID_H ) ,DEVCAP_VAL_DEVICE_ID_H ); SiiRegWrite(DEVCAP_REG(DEVICE_ID_L ) ,DEVCAP_VAL_DEVICE_ID_L ); SiiRegWrite(DEVCAP_REG(SCRATCHPAD_SIZE) ,DEVCAP_VAL_SCRATCHPAD_SIZE ); SiiRegWrite(DEVCAP_REG(INT_STAT_SIZE ) ,DEVCAP_VAL_INT_STAT_SIZE ); SiiRegWrite(DEVCAP_REG(RESERVED ) ,DEVCAP_VAL_RESERVED ); // Make bits 2,3 (initiator timeout) to 1,1 for register CBUS_LINK_CONTROL_2 SiiRegModify(REG_CBUS_LINK_CONTROL_2,BIT_CBUS_INITIATOR_TIMEOUT_MASK,BIT_CBUS_INITIATOR_TIMEOUT_MASK); // Clear legacy bit on Wolverine TX. and set timeout to 0xF SiiRegWrite(REG_MSC_TIMEOUT_LIMIT, 0x0F); // Set NMax to 1 SiiRegWrite(REG_CBUS_LINK_CONTROL_1, 0x01); SiiRegModify(REG_CBUS_MSC_COMPATIBILITY_CTRL, BIT_CBUS_CEC_DISABLE,BIT_CBUS_CEC_DISABLE); // disallow vendor specific commands }