void tapdev_init(void)
{
ENET_TxDscrInit();
ENET_RxDscrInit();
ETH_Start();
}
/*******************************************************************************
* Function Name : ENET_Init
* Description : ENET MAC, PHY and DMA initializations
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void ENET_Init ()
{
vu32 regValue;
ENET_MACConfig *MAC_Config;
ENET_MACConfig config;
u32 macAddrLow, macAddrHigh;
/* De-assert the SRESET bit of ENET + MAC devices */
ENET_DMA->SCR &=~DMA_SCR_SRESET;
MAC_Config =&config;
/* Initialize MAC control register with common values */
MAC_Config->ReceiveALL = DISABLE;
if (SCU_GetHCLKFreqValue() > 50000)
MAC_Config->MIIPrescaler = MIIPrescaler_2;
MAC_Config->LoopbackMode = DISABLE;
MAC_Config->AddressFilteringMode = MAC_Perfect_Multicast_Perfect;
MAC_Config->PassWrongFrame = DISABLE;
MAC_Config->LateCollision = DISABLE;
MAC_Config->BroadcastFrameReception = ENABLE;
MAC_Config->PacketRetry = ENABLE;
MAC_Config->RxFrameFiltering = ENABLE;
MAC_Config->AutomaticPadRemoval = ENABLE;
MAC_Config->DeferralCheck = ENABLE;
/* Configure MAC control register */
ENET_MACControlConfig(MAC_Config);
/* DMA initialization */
/* Read the ENET DMA Status and Control Register */
regValue = ENET_DMA->SCR;
/* Setup Tx Max burst size */
regValue &= ~(u32)DMA_SCR_TX_MAX_BURST_SZ;
regValue |= (u32)DMA_SCR_TX_MAX_BURST_SZ_VAL;
/* Setup Rx Max Burst size */
regValue &= ~(u32)DMA_SCR_RX_MAX_BURST_SZ;
regValue |= (u32)DMA_SCR_RX_MAX_BURST_SZ_VAL;
/* Write Tx & Rx burst size to the ENET status and control register */
ENET_DMA->SCR = regValue;
/* Put the PHY in reset mode */
ENET_MIIWriteReg(0x0,MAC_MII_REG_XCR, 0x8000);
/* Delay to assure PHY reset */
vTaskDelay( 3000 );
/* initialize the opearting mode */
while( ENET_SetOperatingMode() == pdFAIL )
{
vTaskDelay( 3000 );
}
/*set MAC physical*/
macAddrLow = (MAC_ADDR3<<24) + (MAC_ADDR2<<16) + \
(MAC_ADDR1<<8) + MAC_ADDR0;
// Higher MAC address
macAddrHigh = (MAC_ADDR5<<8) + MAC_ADDR4;
/* Initialize Rx and Tx descriptors in memory */
ENET_TxDscrInit();
ENET_RxDscrInit();
}
/*******************************************************************************
* Function Name : ENET_Init
* Description : ENET MAC, DMA and PHY device initializations
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void ENET_Init (ENET_MACConfig *MAC_Config)
{
u32 i;
u32 regValue;
u32 macAddrLow, macAddrHigh;
/* MAC initialization ------------------------------------------------------*/
/* De-assert the SRESET bit of ENET + MAC devices */
ENET_DMA->SCR &= ~ENET_SCR_SRESET;
/* Configure MAC control register */
ENET_MACControlConfig(MAC_Config);
/* MAC address low setting */
macAddrLow = (MAC_ADDR3 << 24) + (MAC_ADDR2 << 16) + \
(MAC_ADDR1 << 8) + MAC_ADDR0;
/* MAC address high setting */
macAddrHigh = (MAC_ADDR5 << 8) + MAC_ADDR4;
/* Write the MAC address Low Register */
ENET_MAC->MAH = macAddrHigh;
/* Write the MAC address High Register */
ENET_MAC->MAL = macAddrLow;
/* Multicast address low setting */
macAddrLow = (MCAST_ADDR3 << 24) + (MCAST_ADDR2 << 16) + \
(MCAST_ADDR1 << 8) + MCAST_ADDR0;
/* Multicast address high setting */
macAddrHigh = (MCAST_ADDR5 << 8) + MCAST_ADDR4;
/* Write the Multicast address Low Register */
ENET_MAC->MCHA = macAddrHigh;
/* Write the Multicast address High Register */
ENET_MAC->MCLA = macAddrLow;
/* VLAN initialization */
ENET_MAC->VL1 = (VLANID1 << 16) | VLANTAG1;
ENET_MAC->VL2 = (VLANID2 << 16) | VLANTAG2;
/* ENET DMA initialisation -------------------------------------------------*/
/* Read the ENET DMA Status and Control Register */
regValue = ENET_DMA->SCR;
/* Setup Tx Max burst size */
regValue &= ~(u32)ENET_SCR_TX_MAX_BURST_SZ;
regValue |= (u32)ENET_SCR_TX_MAX_BURST_SZ_VAL;
/* Setup Rx Max Burst size */
regValue &= ~(u32)ENET_SCR_RX_MAX_BURST_SZ;
regValue |= (u32)ENET_SCR_RX_MAX_BURST_SZ_VAL;
/* Write Tx & Rx burst size to the ENET status and control register */
ENET_DMA->SCR = regValue;
/* Initialize Rx and Tx descriptors in memory */
ENET_TxDscrInit();
ENET_RxDscrInit();
/* PHY DEVICE initialization and OPERATING MODE setting --------------------*/
/* Put the PHY in reset mode */
ENET_MIIWriteReg(PHY_ADDRESS,PHY_XCR, PHY_Reset_Control);
/* Delay to assure PHY reset */
for(i=PHY_ResetDelay; i!=0; i--)
{
regValue = (u32) i;
}
}
