/* * Routine: get_board_mem_timings * Description: If we use SPL then there is no x-loader nor config header * so we have to setup the DDR timings ourself on the first bank. This * provides the timing values back to the function that configures * the memory. */ void get_board_mem_timings(struct board_sdrc_timings *timings) { int pop_mfr, pop_id; /* * We need to identify what PoP memory is on the board so that * we know what timings to use. To map the ID values please see * nand_ids.c */ identify_nand_chip(&pop_mfr, &pop_id); if (pop_mfr == NAND_MFR_HYNIX && pop_id == 0xbc) { /* 256MB DDR */ timings->mcfg = HYNIX_V_MCFG_200(256 << 20); timings->ctrla = HYNIX_V_ACTIMA_200; timings->ctrlb = HYNIX_V_ACTIMB_200; } else { /* 128MB DDR */ timings->mcfg = MICRON_V_MCFG_165(128 << 20); timings->ctrla = MICRON_V_ACTIMA_165; timings->ctrlb = MICRON_V_ACTIMB_165; } timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; timings->mr = MICRON_V_MR_165; }
void get_board_mem_timings(struct board_sdrc_timings *timings) { timings->mcfg = HYNIX_V_MCFG_200(256 << 20); timings->ctrla = HYNIX_V_ACTIMA_200; timings->ctrlb = HYNIX_V_ACTIMB_200; timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; timings->mr = MICRON_V_MR_165; }
/* * Routine: get_board_mem_timings * Description: If we use SPL then there is no x-loader nor config header * so we have to setup the DDR timings ourself on both banks. */ void get_board_mem_timings(struct board_sdrc_timings *timings) { int mfr, id, err = identify_nand_chip(&mfr, &id); timings->mr = MICRON_V_MR_165; if (!err) { switch (mfr) { case NAND_MFR_HYNIX: timings->mcfg = HYNIX_V_MCFG_200(256 << 20); timings->ctrla = HYNIX_V_ACTIMA_200; timings->ctrlb = HYNIX_V_ACTIMB_200; break; case NAND_MFR_MICRON: timings->mcfg = MICRON_V_MCFG_200(256 << 20); timings->ctrla = MICRON_V_ACTIMA_200; timings->ctrlb = MICRON_V_ACTIMB_200; break; default: /* Should not happen... */ break; } timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; gpmc_cs0_flash = MTD_DEV_TYPE_NAND; } else { if (get_cpu_family() == CPU_OMAP34XX) { timings->mcfg = NUMONYX_V_MCFG_165(256 << 20); timings->ctrla = NUMONYX_V_ACTIMA_165; timings->ctrlb = NUMONYX_V_ACTIMB_165; timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; } else { timings->mcfg = NUMONYX_V_MCFG_200(256 << 20); timings->ctrla = NUMONYX_V_ACTIMA_200; timings->ctrlb = NUMONYX_V_ACTIMB_200; timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; } gpmc_cs0_flash = MTD_DEV_TYPE_ONENAND; } }
/* * Routine: get_board_mem_timings * Description: If we use SPL then there is no x-loader nor config header * so we have to setup the DDR timings ourself on both banks. */ void get_board_mem_timings(struct board_sdrc_timings *timings) { timings->mr = MICRON_V_MR_165; switch (get_board_revision()) { case REVISION_0: /* Micron 1286MB/256MB, 1/2 banks of 128MB */ timings->mcfg = MICRON_V_MCFG_165(256 << 20); timings->ctrla = MICRON_V_ACTIMA_165; timings->ctrlb = MICRON_V_ACTIMB_165; timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; break; case REVISION_1: /* Micron 256MB/512MB, 1/2 banks of 256MB */ case REVISION_4: timings->mcfg = MICRON_V_MCFG_200(256 << 20); timings->ctrla = MICRON_V_ACTIMA_200; timings->ctrlb = MICRON_V_ACTIMB_200; timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; break; case REVISION_2: /* Hynix 256MB/512MB, 1/2 banks of 256MB */ timings->mcfg = HYNIX_V_MCFG_200(256 << 20); timings->ctrla = HYNIX_V_ACTIMA_200; timings->ctrlb = HYNIX_V_ACTIMB_200; timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; break; case REVISION_3: /* Micron 512MB/1024MB, 1/2 banks of 512MB */ timings->mcfg = MCFG(512 << 20, 15); timings->ctrla = MICRON_V_ACTIMA_200; timings->ctrlb = MICRON_V_ACTIMB_200; timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; break; default: timings->mcfg = MICRON_V_MCFG_165(128 << 20); timings->ctrla = MICRON_V_ACTIMA_165; timings->ctrlb = MICRON_V_ACTIMB_165; timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; } }