/**
* Multisocket BSC call to start all system core 0s to perform a standard AP_TASK.
*
* This function loops through all possible socket locations, starting core 0 of
* each populated socket to perform the passed in AP_TASK. After starting all
* other core 0s, the BSC will perform the AP_TASK as well. This must be run by
* the system BSC only.
*
* @param[in] TaskPtr Function descriptor
* @param[in] StdHeader Config handle for library and services
* @param[in] ConfigParams AMD entry point's CPU parameter structure
*
*/
VOID
RunCodeOnAllSystemCore0sMulti (
IN AP_TASK *TaskPtr,
IN AMD_CONFIG_PARAMS *StdHeader,
IN VOID *ConfigParams
)
{
UINT32 BscSocket;
UINT32 BscModule;
UINT32 BscCoreNum;
UINT8 Socket;
UINT32 NumberOfSockets;
AGESA_STATUS DummyStatus;
ASSERT (IsBsp (StdHeader, &DummyStatus));
NumberOfSockets = GetPlatformNumberOfSockets ();
IdentifyCore (StdHeader, &BscSocket, &BscModule, &BscCoreNum, &DummyStatus);
for (Socket = 0; Socket < NumberOfSockets; Socket++) {
if (Socket != BscSocket) {
if (IsProcessorPresent (Socket, StdHeader)) {
ApUtilRunCodeOnSocketCore (Socket, 0, TaskPtr, StdHeader);
}
}
}
ApUtilTaskOnExecutingCore (TaskPtr, StdHeader, ConfigParams);
}
/**
* Runs the given task on all cores (including self) on the socket of the executing
* core 0.
*
* This function is used to invoke all APs on the socket of the executing core 0 to
* run a specified AGESA procedure.
*
* @param[in] TaskPtr Function descriptor
* @param[in] StdHeader Config handle for library and services
*
*/
VOID
IdsApRunCodeOnAllLocalCores (
IN AP_TASK *TaskPtr,
IN OUT AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 Core;
UINT32 BscCoreNum;
UINT32 Socket;
UINT32 BscSocket;
UINT32 IgnoredModule;
UINT32 NumberOfCores;
UINT32 NumberOfSockets;
AGESA_STATUS IgnoredSts;
IdentifyCore (StdHeader, &BscSocket, &IgnoredModule, &BscCoreNum, &IgnoredSts);
NumberOfSockets = GetPlatformNumberOfSockets ();
for (Socket = 0; Socket < NumberOfSockets; Socket++) {
if (GetActiveCoresInGivenSocket (Socket, &NumberOfCores, StdHeader)) {
for (Core = 0; Core < NumberOfCores; Core++) {
if ((Socket != (UINT32) BscSocket) || (Core != (UINT32) BscCoreNum)) {
ApUtilRunCodeOnSocketCore ((UINT8) Socket, (UINT8) Core, TaskPtr, StdHeader);
}
}
}
}
// BSP codes
ApUtilTaskOnExecutingCore (TaskPtr, StdHeader, NULL);
}
/**
* Main entry point for initializing the Thermal Control
* safety net feature.
*
* This must be run by all Family 10h core 0s in the system.
*
* @param[in] FamilySpecificServices The current Family Specific Services.
* @param[in] CpuEarlyParamsPtr Service parameters.
* @param[in] StdHeader Config handle for library and services.
*/
VOID
F10PmThermalInit (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 Core;
UINT32 Module;
UINT32 LocalPciRegister;
UINT32 Socket;
PCI_ADDR PciAddress;
AGESA_STATUS IgnoredSts;
IdentifyCore (StdHeader, &Socket, &Module, &Core, &IgnoredSts);
ASSERT (Core == 0);
if (GetPciAddress (StdHeader, Socket, 0, &PciAddress, &IgnoredSts)) {
PciAddress.Address.Function = FUNC_3;
PciAddress.Address.Register = NB_CAPS_REG;
LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
if (((NB_CAPS_REGISTER *) &LocalPciRegister)->HtcCapable == 1) {
// Enable HTC
PciAddress.Address.Register = HTC_REG;
LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
((HTC_REGISTER *) &LocalPciRegister)->HtcSlewSel = 0;
((HTC_REGISTER *) &LocalPciRegister)->HtcEn = 1;
LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
}
}
}
/**
*
* FeatureLeveling
*
* CPU feature leveling. Set least common features set of all CPUs
*
* @param[in,out] StdHeader - Pointer to AMD_CONFIG_PARAMS struct.
*
*/
VOID
FeatureLeveling (
IN OUT AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 BscSocket;
UINT32 Ignored;
UINT32 BscCoreNum;
UINT32 Socket;
UINT32 Core;
UINT32 NumberOfSockets;
UINT32 NumberOfCores;
BOOLEAN *FirstTime;
BOOLEAN *NeedLeveling;
AGESA_STATUS IgnoredSts;
CPU_FEATURES_LIST *globalCpuFeatureList;
AP_TASK TaskPtr;
ASSERT (IsBsp (StdHeader, &IgnoredSts));
GetGlobalCpuFeatureListAddress ((UINT64 **) &globalCpuFeatureList, StdHeader);
FirstTime = (BOOLEAN *) ((UINT8 *) globalCpuFeatureList + sizeof (CPU_FEATURES_LIST));
NeedLeveling = (BOOLEAN *) ((UINT8 *) globalCpuFeatureList + sizeof (CPU_FEATURES_LIST) + sizeof (BOOLEAN));
*FirstTime = TRUE;
*NeedLeveling = FALSE;
LibAmdMemFill (globalCpuFeatureList, 0xFF, sizeof (CPU_FEATURES_LIST), StdHeader);
IdentifyCore (StdHeader, &BscSocket, &Ignored, &BscCoreNum, &IgnoredSts);
NumberOfSockets = GetPlatformNumberOfSockets ();
TaskPtr.FuncAddress.PfApTaskI = SaveFeatures;
TaskPtr.DataTransfer.DataSizeInDwords = SIZE_IN_DWORDS (CPU_FEATURES_LIST);
TaskPtr.ExeFlags = WAIT_FOR_CORE;
TaskPtr.DataTransfer.DataPtr = globalCpuFeatureList;
TaskPtr.DataTransfer.DataTransferFlags = DATA_IN_MEMORY;
for (Socket = 0; Socket < NumberOfSockets; Socket++) {
if (IsProcessorPresent (Socket, StdHeader)) {
if (Socket != BscSocket) {
ApUtilRunCodeOnSocketCore ((UINT8)Socket, 0, &TaskPtr, StdHeader);
}
}
}
ApUtilTaskOnExecutingCore (&TaskPtr, StdHeader, NULL);
if (*NeedLeveling) {
TaskPtr.FuncAddress.PfApTaskI = WriteFeatures;
for (Socket = 0; Socket < NumberOfSockets; Socket++) {
if (GetActiveCoresInGivenSocket (Socket, &NumberOfCores, StdHeader)) {
for (Core = 0; Core < NumberOfCores; Core++) {
if ((Socket != BscSocket) || (Core != BscCoreNum)) {
ApUtilRunCodeOnSocketCore ((UINT8)Socket, (UINT8)Core, &TaskPtr, StdHeader);
}
}
}
}
ApUtilTaskOnExecutingCore (&TaskPtr, StdHeader, NULL);
}
}
/**
* Get PCI Config Space Address for the current running core.
*
* @param[out] PciAddress The Processor's PCI Config Space address (Function 0, Register 0)
* @param[in] StdHeader Header for library and services.
*
* @retval TRUE The core is present, PCI Address valid
* @retval FALSE The core is not present, PCI Address not valid.
*/
BOOLEAN
GetCurrPciAddrMulti (
OUT PCI_ADDR *PciAddress,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT8 Node;
UINT32 Socket;
UINT32 Module;
UINT32 Core;
BOOLEAN Result;
AGESA_STATUS IgnoredSts;
Result = TRUE;
IdentifyCore (StdHeader, &Socket, &Module, &Core, &IgnoredSts);
ASSERT (Socket < MAX_SOCKETS);
ASSERT (Module < MAX_DIES);
if (GetNodeId (Socket, Module, &Node, StdHeader)) {
// Socket is populated
PciAddress->AddressValue = MAKE_SBDFO (0, 0, 24, 0, 0);
PciAddress->Address.Device = PciAddress->Address.Device + Node;
} else {
// Socket is not populated
PciAddress->AddressValue = ILLEGAL_SBDFO;
Result = FALSE;
}
return Result;
}
/**
* Writes to all nodes on the executing core's socket.
*
* @param[in] PciAddress The Function and Register to update
* @param[in] Mask The bitwise AND mask to apply to the current register value
* @param[in] Data The bitwise OR mask to apply to the current register value
* @param[in] StdHeader Header for library and services.
*
*/
VOID
ModifyCurrSocketPciMulti (
IN PCI_ADDR *PciAddress,
IN UINT32 Mask,
IN UINT32 Data,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 Socket;
UINT32 Module;
UINT32 Core;
UINT32 LocalPciRegister;
AGESA_STATUS AgesaStatus;
PCI_ADDR Reg;
IdentifyCore (StdHeader, &Socket, &Module, &Core, &AgesaStatus);
for (Module = 0; Module < (UINT8)GetPlatformNumberOfModules (); Module++) {
if (GetPciAddress (StdHeader, Socket, Module, &Reg, &AgesaStatus)) {
Reg.Address.Function = PciAddress->Address.Function;
Reg.Address.Register = PciAddress->Address.Register;
LibAmdPciRead (AccessWidth32, Reg, &LocalPciRegister, StdHeader);
LocalPciRegister &= Mask;
LocalPciRegister |= Data;
LibAmdPciWrite (AccessWidth32, Reg, &LocalPciRegister, StdHeader);
}
}
}
/**
* Family 15h Kaveri core 0 entry point for performing the necessary steps after
* a warm reset has occurred.
*
* The steps are as follows:
*
* 1. Temp1=D18F5x170[SwNbPstateLoDis].
* 2. Temp2=D18F5x170[NbPstateDisOnP0].
* 3. Temp3=D18F5x170[NbPstateThreshold].
* 4. Temp4=D18F5x170[NbPstateGnbSlowDis].
* 5. If MSRC001_0070[NbPstate]=0, go to step 6. If MSRC001_0070[NbPstate]=1, go to step 11.
* 6. Write 1 to D18F5x170[NbPstateGnbSlowDis].
* 7. Write 0 to D18F5x170[SwNbPstateLoDis, NbPstateDisOnP0, NbPstateThreshold].
* 8. Wait for D18F5x174[CurNbPstate] = D18F5x170[NbPstateLo] and D18F5x174[CurNbFid, CurNb-
* Did]=[NbFid, NbDid] from D18F5x1[6C:60] indexed by D18F5x170[NbPstateLo].
* 9. Set D18F5x170[SwNbPstateLoDis]=1.
* 10. Wait for D18F5x174[CurNbPstate] = D18F5x170[NbPstateHi] and D18F5x174[CurNbFid, CurNb-
* Did]=[NbFid, NbDid] from D18F5x1[6C:60] indexed by D18F5x170[NbPstateHi]. Go to step 15.
* 11. Write 1 to D18F5x170[SwNbPstateLoDis].
* 12. Wait for D18F5x174[CurNbPstate] = D18F5x170[NbPstateHi] and D18F5x174[CurNbFid, CurNb-
* Did]=[NbFid, NbDid] from D18F5x1[6C:60] indexed by D18F5x170[NbPstateHi].
* 13. Write 0 to D18F5x170[SwNbPstateLoDis, NbPstateDisOnP0, NbPstateThreshold].
* 14. Wait for D18F5x174[CurNbPstate] = D18F5x170[NbPstateLo] and D18F5x174[CurNbFid, CurNb-
* Did]=[NbFid, NbDid] from D18F5x1[6C:60] indexed by D18F5x170[NbPstateLo].
* 15. Set D18F5x170[SwNbPstateLoDis]=Temp1, D18F5x170[NbPstateDisOnP0]=Temp2, D18F5x170[NbP-
* stateThreshold]=Temp3, and D18F5x170[NbPstateGnbSlowDis]=Temp4.
*
* @param[in] FamilySpecificServices The current Family Specific Services.
* @param[in] CpuEarlyParamsPtr Service parameters
* @param[in] StdHeader Config handle for library and services.
*
*/
VOID
F15KvPmNbAfterReset (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 Socket;
UINT32 Module;
UINT32 Core;
UINT32 TaskedCore;
UINT32 Ignored;
AP_TASK TaskPtr;
AGESA_STATUS IgnoredSts;
IDS_HDT_CONSOLE (CPU_TRACE, " F15KvPmNbAfterReset\n");
IdentifyCore (StdHeader, &Socket, &Module, &Core, &IgnoredSts);
ASSERT (Core == 0);
// Launch one core per node.
TaskPtr.FuncAddress.PfApTask = F15KvPmNbAfterResetOnCore;
TaskPtr.DataTransfer.DataSizeInDwords = 0;
TaskPtr.ExeFlags = WAIT_FOR_CORE;
for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) {
if (GetGivenModuleCoreRange (Socket, Module, &TaskedCore, &Ignored, StdHeader)) {
if (TaskedCore != 0) {
ApUtilRunCodeOnSocketCore ((UINT8) Socket, (UINT8) TaskedCore, &TaskPtr, StdHeader);
}
}
}
ApUtilTaskOnExecutingCore (&TaskPtr, StdHeader, (VOID *) CpuEarlyParamsPtr);
}
/**
* Enable Application Power Management (APM)
*
* @param[in] EntryPoint Timepoint designator.
* @param[in] PlatformConfig Contains the runtime modifiable feature input data.
* @param[in] StdHeader Config Handle for library, services.
*
* @retval AGESA_SUCCESS Always succeeds.
*
*/
STATIC AGESA_STATUS
InitializeApmFeature (
IN UINT64 EntryPoint,
IN PLATFORM_CONFIGURATION *PlatformConfig,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 BscSocket;
UINT32 Ignored;
UINT32 Socket;
UINT32 NumberOfSockets;
AP_TASK TaskPtr;
AGESA_STATUS IgnoredSts;
IDS_HDT_CONSOLE (CPU_TRACE, " APM mode is enabled\n");
IdentifyCore (StdHeader, &BscSocket, &Ignored, &Ignored, &IgnoredSts);
NumberOfSockets = GetPlatformNumberOfSockets ();
TaskPtr.FuncAddress.PfApTask = EnableApmOnSocket;
TaskPtr.DataTransfer.DataSizeInDwords = 0;
TaskPtr.ExeFlags = WAIT_FOR_CORE;
for (Socket = 0; Socket < NumberOfSockets; Socket++) {
if (IsProcessorPresent (Socket, StdHeader)) {
if (Socket != BscSocket) {
ApUtilRunCodeOnSocketCore ((UINT8) Socket, 0, &TaskPtr, StdHeader);
}
}
}
EnableApmOnSocket (StdHeader);
return AGESA_SUCCESS;
}
/**
*
* This function checks the status of BIST and places the error status in the event log
* if there are any errors
*
* @param[in] StdHeader Header for library and services
*
* @retval AGESA_SUCCESS No BIST errors have been logged.
* @retval AGESA_ALERT BIST errors have been detected and added to the
* event log.
*/
AGESA_STATUS
CheckBistStatus (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 Socket;
UINT32 Core;
UINT32 BscSocket;
UINT32 BscCoreNum;
UINT32 NumberOfSockets;
UINT32 NumberOfCores;
UINT32 Ignored;
UINT32 ReturnCode;
AGESA_STATUS IgnoredSts;
AGESA_STATUS AgesaStatus;
AP_TASK TaskPtr;
// Make sure that Standard Header is valid
ASSERT (StdHeader != NULL);
ASSERT (IsBsp (StdHeader, &IgnoredSts));
AgesaStatus = AGESA_SUCCESS;
// Get the BscSocket, BscCoreNum and NumberOfSockets in the system
IdentifyCore (StdHeader, &BscSocket, &Ignored, &BscCoreNum, &IgnoredSts);
NumberOfSockets = GetPlatformNumberOfSockets ();
// Setup TaskPtr struct to execute routine on APs
TaskPtr.FuncAddress.PfApTaskO = GetBistResults;
TaskPtr.DataTransfer.DataSizeInDwords = 0;
TaskPtr.ExeFlags = TASK_HAS_OUTPUT | WAIT_FOR_CORE;
for (Socket = 0; Socket < NumberOfSockets; Socket++) {
if (GetActiveCoresInGivenSocket (Socket, &NumberOfCores, StdHeader)) {
for (Core = 0; Core < NumberOfCores; Core++) {
if ((Socket != BscSocket) || (Core != BscCoreNum)) {
ReturnCode = ApUtilRunCodeOnSocketCore ((UINT8)Socket, (UINT8)Core, &TaskPtr, StdHeader);
} else {
ReturnCode = TaskPtr.FuncAddress.PfApTaskO (StdHeader);
}
// If BIST value is non-zero, add to BSP's event log
if (ReturnCode != 0) {
IDS_HDT_CONSOLE (CPU_TRACE, " BIST failure: socket %d core %d, status = 0x%x\n", Socket, Core, ReturnCode);
AgesaStatus = AGESA_ALERT;
PutEventLog (AGESA_ALERT,
CPU_EVENT_BIST_ERROR,
ReturnCode, Socket, Core, 0, StdHeader);
}
}
}
}
return AgesaStatus;
}
/**
* Family 10h core 0 entry point for performing the necessary steps after
* a warm reset has occurred.
*
* The steps are as follows:
* 1. Modify F3xDC[PstateMaxVal] to reflect the lowest performance P-state
* supported, as indicated in MSRC001_00[68:64][PstateEn]
* 2. If MSRC001_0071[CurNbDid] = 0, set MSRC001_001F[GfxNbPstateDis]
* 3. If MSRC001_0071[CurPstate] != F3xDC[PstateMaxVal], go to step 20
* 4. If F3xDC[PstateMaxVal] = 0 or F3xDC[PstateMaxVal] != 4, go to step 7
* 5. If MSRC001_0061[CurPstateLimit] <= F3xDC[PstateMaxVal]-1, go to step 17
* 6. Exit the sequence
* 7. Copy the P-state register pointed to by F3xDC[PstateMaxVal] to the P-state
* register pointed to by F3xDC[PstateMaxVal]+1
* 8. Write F3xDC[PstateMaxVal]+1 to F3xDC[PstateMaxVal]
* 9. Write (the new) F3xDC[PstateMaxVal] to MSRC001_0062[PstateCmd]
* 10. Wait for MSRC001_0071[CurCpuFid/CurCpuDid] = CpuFid/CpuDid from the P-state
* register pointed to by (the new) F3xDC[PstateMaxVal]
* 11. Copy (the new) F3xDC[PstateMaxVal]-1 to MSRC001_0062[PstateCmd]
* 12. Wait for MSRC001_0071[CurCpuFid/CurCpuDid] = CpuFid/CpuDid from the P-state
* register pointed to by (the new) F3xDC[PstateMaxVal]-1
* 13. If MSRC001_0071[CurNbDid] = 1, set MSRC001_001F[GfxNbPstateDis]
* 14. If required, transition the NB COF and VID to the NbDid and NbVid from the
* P-state register pointed to by MSRC001_0061[CurPstateLimit] using the NB COF
* and VID transition sequence after a warm reset
* 15. Write MSRC001_00[68:64][PstateEn]=0 for the P-state pointed to by F3xDC[PstateMaxVal]
* 16. Write (the new) F3xDC[PstateMaxVal]-1 to F3xDC[PstateMaxVal] and exit the sequence
* 17. Copy F3xDC[PstateMaxVal]-1 to MSRC001_0062[PstateCmd]
* 18. Wait for MSRC001_0071[CurCpuFid/CurCpuDid] = CpuFid/CpuDid from the P-state
* register pointed to by F3xDC[PstateMaxVal]-1
* 19. If MSRC001_0071[CurNbDid] = 0, set MSRC001_001F[GfxNbPstateDis]
* 20. Copy F3xDC[PstateMaxVal] to MSRC001_0062[PstateCmd]
* 21. Wait for MSRC001_0071[CurCpuFid/CurCpuDid] = CpuFid/CpuDid from the P-state
* register pointed to by F3xDC[PstateMaxVal]
* 22. If MSRC001_0071[CurNbDid] = 1, set MSRC001_001F[GfxNbPstateDis]
* 23. Issue an LDTSTOP assertion in the IO hub and exit sequence
* 24. If required, transition the NB COF and VID to the NbDid and NbVid from the
* P-state register pointed to by F3xDC[PstateMaxVal] using the NB COF and VID
* transition sequence after a warm reset
*
* @param[in] FamilySpecificServices The current Family Specific Services.
* @param[in] CpuEarlyParamsPtr Service parameters
* @param[in] StdHeader Config handle for library and services.
*
*/
VOID
F10PmAfterReset (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 Socket;
UINT32 Module;
UINT32 PsMaxVal;
UINT32 CoreNum;
UINT32 MsrAddr;
UINT32 Core;
UINT32 AndMask;
UINT32 OrMask;
UINT64 LocalMsrRegister;
PCI_ADDR PciAddress;
AP_TASK TaskPtr;
AGESA_STATUS IgnoredSts;
IdentifyCore (StdHeader, &Socket, &Module, &Core, &IgnoredSts);
GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts);
GetActiveCoresInCurrentSocket (&CoreNum, StdHeader);
ASSERT (Core == 0);
// Step 1 Modify F3xDC[PstateMaxVal] to reflect the lowest performance
// P-state supported, as indicated in MSRC001_00[68:64][PstateEn]
for (MsrAddr = PS_MAX_REG; MsrAddr > PS_REG_BASE; --MsrAddr) {
LibAmdMsrRead (MsrAddr, &LocalMsrRegister, StdHeader);
if (((PSTATE_MSR *) &LocalMsrRegister)->PsEnable == 1) {
break;
}
}
PsMaxVal = MsrAddr - PS_REG_BASE;
PciAddress.Address.Function = FUNC_3;
PciAddress.Address.Register = CPTC2_REG;
AndMask = 0xFFFFFFFF;
OrMask = 0x00000000;
((CLK_PWR_TIMING_CTRL2_REGISTER *) &AndMask)->PstateMaxVal = 0;
((CLK_PWR_TIMING_CTRL2_REGISTER *) &OrMask)->PstateMaxVal = PsMaxVal;
ModifyCurrentSocketPci (&PciAddress, AndMask, OrMask, StdHeader);
// Launch each local core to perform the remaining steps.
TaskPtr.FuncAddress.PfApTask = F10PmAfterResetCore;
TaskPtr.DataTransfer.DataSizeInDwords = 0;
TaskPtr.ExeFlags = WAIT_FOR_CORE;
ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, CpuEarlyParamsPtr);
}
/**
* Family 15h Trinity core 0 entry point for performing the necessary steps after
* a warm reset has occurred.
*
* The steps are as follows:
*
* 1. Temp1=D18F5x170[SwNbPstateLoDis].
* 2. Temp2=D18F5x170[NbPstateDisOnP0].
* 3. Temp3=D18F5x170[NbPstateThreshold].
* 4. Temp4=D18F5x170[NbPstateGnbSlowDis].
* 5. If MSRC001_0070[NbPstate]=0, go to step 6. If MSRC001_0070[NbPstate]=1, go to step 11.
* 6. Write 1 to D18F5x170[NbPstateGnbSlowDis].
* 7. Write 0 to D18F5x170[SwNbPstateLoDis, NbPstateDisOnP0, NbPstateThreshold].
* 8. Wait for D18F5x174[CurNbPstate] = D18F5x170[NbPstateLo] and D18F5x174[CurNbFid, CurNb-
* Did]=[NbFid, NbDid] from D18F5x1[6C:60] indexed by D18F5x170[NbPstateLo].
* 9. Set D18F5x170[SwNbPstateLoDis]=1.
* 10. Wait for D18F5x174[CurNbPstate] = D18F5x170[NbPstateHi] and D18F5x174[CurNbFid, CurNb-
* Did]=[NbFid, NbDid] from D18F5x1[6C:60] indexed by D18F5x170[NbPstateHi]. Go to step 15.
* 11. Write 1 to D18F5x170[SwNbPstateLoDis].
* 12. Wait for D18F5x174[CurNbPstate] = D18F5x170[NbPstateHi] and D18F5x174[CurNbFid, CurNb-
* Did]=[NbFid, NbDid] from D18F5x1[6C:60] indexed by D18F5x170[NbPstateHi].
* 13. Write 0 to D18F5x170[SwNbPstateLoDis, NbPstateDisOnP0, NbPstateThreshold].
* 14. Wait for D18F5x174[CurNbPstate] = D18F5x170[NbPstateLo] and D18F5x174[CurNbFid, CurNb-
* Did]=[NbFid, NbDid] from D18F5x1[6C:60] indexed by D18F5x170[NbPstateLo].
* 15. Set D18F5x170[SwNbPstateLoDis]=Temp1, D18F5x170[NbPstateDisOnP0]=Temp2, D18F5x170[NbP-
* stateThreshold]=Temp3, and D18F5x170[NbPstateGnbSlowDis]=Temp4.
*
* @param[in] FamilySpecificServices The current Family Specific Services.
* @param[in] CpuEarlyParamsPtr Service parameters
* @param[in] StdHeader Config handle for library and services.
*
*/
VOID
F15TnPmNbAfterReset (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 Socket;
UINT32 Module;
UINT32 Core;
UINT32 TaskedCore;
UINT32 Ignored;
AP_TASK TaskPtr;
PCI_ADDR PciAddress;
AGESA_STATUS IgnoredSts;
LOCATE_HEAP_PTR Locate;
IDS_HDT_CONSOLE (CPU_TRACE, " F15TnPmNbAfterReset\n");
IdentifyCore (StdHeader, &Socket, &Module, &Core, &IgnoredSts);
ASSERT (Core == 0);
if (FamilySpecificServices->IsNbPstateEnabled (FamilySpecificServices, &CpuEarlyParamsPtr->PlatformConfig, StdHeader)) {
PciAddress.AddressValue = NB_PSTATE_CTRL_PCI_ADDR;
Locate.BufferHandle = AMD_CPU_NB_PSTATE_FIXUP_HANDLE;
if (HeapLocateBuffer (&Locate, StdHeader) == AGESA_SUCCESS) {
LibAmdPciWrite (AccessWidth32, PciAddress, Locate.BufferPtr, StdHeader);
} else {
ASSERT (FALSE);
}
}
// Launch one core per node.
TaskPtr.FuncAddress.PfApTask = F15TnPmNbAfterResetOnCore;
TaskPtr.DataTransfer.DataSizeInDwords = 0;
TaskPtr.ExeFlags = WAIT_FOR_CORE;
for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) {
if (GetGivenModuleCoreRange (Socket, Module, &TaskedCore, &Ignored, StdHeader)) {
if (TaskedCore != 0) {
ApUtilRunCodeOnSocketCore ((UINT8) Socket, (UINT8) TaskedCore, &TaskPtr, StdHeader);
}
}
}
ApUtilTaskOnExecutingCore (&TaskPtr, StdHeader, (VOID *) CpuEarlyParamsPtr);
}
STATIC VOID
IdsCmnTaskCore0Early (
IN IDS_EARLY_AP_TASK *PEarlyApTask,
IN OUT AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 Socket;
UINT32 IgnoredModule;
UINT32 IgnoredCore;
AGESA_STATUS IgnoredSts;
ASSERT (PEarlyApTask->Ap_Task0.Core != 0);
PEarlyApTask->Ap_Task0.ApTask.DataTransfer.DataPtr = &PEarlyApTask->Parameters[0];
IdentifyCore (StdHeader, &Socket, &IgnoredModule, &IgnoredCore, &IgnoredSts);
ApUtilRunCodeOnSocketCore ((UINT8)Socket, PEarlyApTask->Ap_Task0.Core, &PEarlyApTask->Ap_Task0.ApTask, StdHeader);
}
/**
* Enable high performance computing (HPC mode)
*
* @param[in] EntryPoint Timepoint designator.
* @param[in] PlatformConfig Contains the runtime modifiable feature input data.
* @param[in] StdHeader Config Handle for library, services.
*
* @retval AGESA_SUCCESS Always succeeds.
*
*/
AGESA_STATUS
STATIC
InitializePstateHpcModeFeature (
IN UINT64 EntryPoint,
IN PLATFORM_CONFIGURATION *PlatformConfig,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 BscSocket;
UINT32 Ignored;
UINT32 BscCoreNum;
UINT32 Core;
UINT32 Socket;
UINT32 NumberOfSockets;
UINT32 NumberOfCores;
AP_TASK TaskPtr;
AGESA_STATUS IgnoredSts;
if (!IsWarmReset (StdHeader)) {
IDS_HDT_CONSOLE (CPU_TRACE, " P-state HPC mode is enabled\n");
IdentifyCore (StdHeader, &BscSocket, &Ignored, &BscCoreNum, &IgnoredSts);
NumberOfSockets = GetPlatformNumberOfSockets ();
TaskPtr.FuncAddress.PfApTaskI = EnablePstateHpcModeOnAps;
TaskPtr.DataTransfer.DataSizeInDwords = 2;
TaskPtr.DataTransfer.DataPtr = PlatformConfig;
TaskPtr.DataTransfer.DataTransferFlags = 0;
TaskPtr.ExeFlags = WAIT_FOR_CORE;
for (Socket = 0; Socket < NumberOfSockets; Socket++) {
if (GetActiveCoresInGivenSocket (Socket, &NumberOfCores, StdHeader)) {
for (Core = 0; Core < NumberOfCores; Core++) {
if ((Socket != BscSocket) || (Core != BscCoreNum)) {
ApUtilRunCodeOnSocketCore ((UINT8) Socket, (UINT8) Core, &TaskPtr, StdHeader);
}
}
}
}
EnablePstateHpcModeOnAps (PlatformConfig, StdHeader);
}
return AGESA_SUCCESS;
}
/**
*
* Run code on every AP in the system.
*
* @param[in] ApParams AP task pointer.
* @param[in] StdHeader Handle to config for library and services
*
* @return The most severe AGESA_STATUS returned by an AP.
*
*/
AGESA_STATUS
RunLateApTaskOnAllAPs (
IN AP_EXE_PARAMS *ApParams,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 NumberOfSockets;
UINT32 NumberOfCores;
UINT8 Socket;
UINT8 Core;
UINT8 ApicId;
UINT32 BscSocket;
UINT32 Ignored;
UINT32 BscCoreNum;
AGESA_STATUS CalledStatus;
AGESA_STATUS IgnoredStatus;
AGESA_STATUS AgesaStatus;
ASSERT (IsBsp (StdHeader, &IgnoredStatus));
AgesaStatus = AGESA_SUCCESS;
IdentifyCore (StdHeader, &BscSocket, &Ignored, &BscCoreNum, &IgnoredStatus);
NumberOfSockets = GetPlatformNumberOfSockets ();
for (Socket = 0; Socket < NumberOfSockets; Socket++) {
if (GetActiveCoresInGivenSocket (Socket, &NumberOfCores, StdHeader)) {
for (Core = 0; Core < NumberOfCores; Core++) {
if ((Socket != BscSocket) || (Core != BscCoreNum)) {
GetApicId (StdHeader, Socket, Core, &ApicId, &IgnoredStatus);
AGESA_TESTPOINT (TpIfBeforeRunApFromAllAps, StdHeader);
CalledStatus = AgesaRunFcnOnAp ((UINTN) ApicId, ApParams);
AGESA_TESTPOINT (TpIfAfterRunApFromAllAps, StdHeader);
if (CalledStatus > AgesaStatus) {
AgesaStatus = CalledStatus;
}
}
}
}
}
return AgesaStatus;
}
/**
*
* CpuPrefetchModeApTask
*
* Parameters:
* @param[in] ApExeParams Handle to config for library and services.
*
* @retval AGESA_STATUS
*
* Processing:
*
*/
AGESA_STATUS
CpuPrefetchModeApTask (
IN AP_EXE_PARAMS *ApExeParams
)
{
UINT32 Socket;
UINT32 Module;
UINT32 Core;
AGESA_STATUS IgnoredSts;
AGESA_STATUS CalledStatus;
PREFETCH_MODE_FAMILY_SERVICES *FamilyServices;
CalledStatus = AGESA_ERROR;
IdentifyCore (&(ApExeParams->StdHeader), &Socket, &Module, &Core, &IgnoredSts);
GetFeatureServicesOfSocket (&PrefetchModeFamilyServiceTable, Socket, (CONST VOID **)&FamilyServices, &(ApExeParams->StdHeader));
if (FamilyServices != NULL) {
CalledStatus = FamilyServices->PrefetchModeControlOnCore (FamilyServices, (PLATFORM_CONFIGURATION *) (ApExeParams->RelatedDataBlock), &(ApExeParams->StdHeader));
}
return CalledStatus;
}
/**
*---------------------------------------------------------------------------------------
*
* PutAllCoreInPState0
*
* Description:
* This function will put core pstate to p0.
*
* Parameters:
* @param[in,out] *PStateBufferPtr
* @param[in] *StdHeader
*
* @retval AGESA_STATUS
*
*---------------------------------------------------------------------------------------
**/
AGESA_STATUS
PutAllCoreInPState0 (
IN OUT PSTATE_LEVELING *PStateBufferPtr,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
AP_TASK TaskPtr;
UINT32 BscSocket;
UINT32 Ignored;
UINT32 BscCoreNum;
UINT32 Core;
UINT32 Socket;
UINT32 NumberOfSockets;
UINT32 NumberOfCores;
AGESA_STATUS IgnoredSts;
TaskPtr.FuncAddress.PfApTaskI = PutCoreInPState0;
TaskPtr.DataTransfer.DataSizeInDwords = SIZE_IN_DWORDS (PSTATE_LEVELING);
TaskPtr.ExeFlags = WAIT_FOR_CORE;
TaskPtr.DataTransfer.DataPtr = PStateBufferPtr;
TaskPtr.DataTransfer.DataTransferFlags = DATA_IN_MEMORY;
IdentifyCore (StdHeader, &BscSocket, &Ignored, &BscCoreNum, &IgnoredSts);
NumberOfSockets = GetPlatformNumberOfSockets ();
PutCoreInPState0 (PStateBufferPtr, StdHeader);
for (Socket = 0; Socket < NumberOfSockets; Socket++) {
if (GetActiveCoresInGivenSocket (Socket, &NumberOfCores, StdHeader)) {
for (Core = 0; Core < NumberOfCores; Core++) {
if ((Socket != (UINT32) BscSocket) || (Core != (UINT32) BscCoreNum)) {
ApUtilRunCodeOnSocketCore ((UINT8) Socket, (UINT8) Core, &TaskPtr, StdHeader);
}
}
}
}
return AGESA_SUCCESS;
}
/**
* This function will set msr on all cores of all nodes.
*
* @param[in] CpuAmdPState Pointer to S_CPU_AMD_PSTATE.
* @param[in] StdHeader Header for library and services.
*
* @retval AGESA_SUCCESS Always succeeds
*
*/
AGESA_STATUS
StartPstateMsrModify (
IN S_CPU_AMD_PSTATE *CpuAmdPState,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
AP_TASK TaskPtr;
UINT32 BscSocket;
UINT32 Ignored;
UINT32 BscCoreNum;
UINT32 Core;
UINT32 Socket;
UINT32 NumberOfSockets;
UINT32 NumberOfCores;
AGESA_STATUS IgnoredSts;
TaskPtr.FuncAddress.PfApTaskI = CorePstateRegModify;
TaskPtr.DataTransfer.DataSizeInDwords = (UINT16) (CpuAmdPState->SizeOfBytes / 4 + 1);
TaskPtr.ExeFlags = WAIT_FOR_CORE;
TaskPtr.DataTransfer.DataPtr = CpuAmdPState;
TaskPtr.DataTransfer.DataTransferFlags = DATA_IN_MEMORY;
IdentifyCore (StdHeader, &BscSocket, &Ignored, &BscCoreNum, &IgnoredSts);
NumberOfSockets = GetPlatformNumberOfSockets ();
CorePstateRegModify (CpuAmdPState, StdHeader);
for (Socket = 0; Socket < NumberOfSockets; Socket++) {
if (GetActiveCoresInGivenSocket (Socket, &NumberOfCores, StdHeader)) {
for (Core = 0; Core < NumberOfCores; Core++) {
if ((Socket != (UINT32) BscSocket) || (Core != (UINT32) BscCoreNum)) {
ApUtilRunCodeOnSocketCore ((UINT8) Socket, (UINT8) Core, &TaskPtr, StdHeader);
}
}
}
}
return AGESA_SUCCESS;
}
/**
*
* Exit function for HDT out Function of S3 Resume
*
* Restore debug register and Deallocate heap, and will also fire a HDTOUT
* Command to let hdtout script do corresponding things.
*
* @param[in,out] StdHeader The Pointer of AGESA Header
*
**/
VOID
AmdIdsHdtOutS3ApExit (
IN OUT AMD_CONFIG_PARAMS *StdHeader
)
{
AP_TASK TaskPtr;
UINT32 Ignored;
UINT32 BscSocket;
UINT32 BscCoreNum;
UINT32 Core;
UINT32 Socket;
UINT32 NumberOfSockets;
UINT32 NumberOfCores;
AGESA_STATUS IgnoredSts;
if (AmdIdsHdtOutSupport ()) {
// run code on all APs except BSP
TaskPtr.FuncAddress.PfApTaskI = (PF_AP_TASK_I)AmdIdsHdtOutExitCoreTask;
TaskPtr.DataTransfer.DataSizeInDwords = 0;
TaskPtr.DataTransfer.DataPtr = NULL;
TaskPtr.DataTransfer.DataTransferFlags = 0;
TaskPtr.ExeFlags = WAIT_FOR_CORE;
NumberOfSockets = GetPlatformNumberOfSockets ();
IdentifyCore (StdHeader, &BscSocket, &Ignored, &BscCoreNum, &IgnoredSts);
for (Socket = 0; Socket < NumberOfSockets; Socket++) {
if (IsProcessorPresent (Socket, StdHeader)) {
if (GetActiveCoresInGivenSocket (Socket, &NumberOfCores, StdHeader)) {
for (Core = 0; Core < NumberOfCores; Core++) {
if ((Socket != BscSocket) || (Core != BscCoreNum)) {
ApUtilRunCodeOnSocketCore ((UINT8) Socket, (UINT8) Core, &TaskPtr, StdHeader);
}
}
}
}
}
}
}
/**
* Runs the given task on all cores (including self) on the socket of the executing
* core 0.
*
* This function is used to invoke all APs on the socket of the executing core 0 to
* run a specified AGESA procedure.
*
* @param[in] TaskPtr Function descriptor
* @param[in] StdHeader Config handle for library and services
* @param[in] CpuEarlyParamsPtr Required input parameters for early CPU initialization
*
*/
VOID
ApUtilRunCodeOnAllLocalCoresAtEarly (
IN AP_TASK *TaskPtr,
IN AMD_CONFIG_PARAMS *StdHeader,
IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr
)
{
UINT32 Core;
UINT32 Socket;
UINT32 IgnoredModule;
UINT32 IgnoredCore;
UINT32 ActiveCores;
AGESA_STATUS IgnoredSts;
IdentifyCore (StdHeader, &Socket, &IgnoredModule, &IgnoredCore, &IgnoredSts);
GetActiveCoresInCurrentSocket (&ActiveCores, StdHeader);
for (Core = 1; Core < (UINT8) ActiveCores; ++Core) {
ApUtilRunCodeOnSocketCore ((UINT8)Socket, (UINT8)Core, TaskPtr, StdHeader);
}
ApUtilTaskOnExecutingCore (TaskPtr, StdHeader, (VOID *) CpuEarlyParamsPtr);
}
/**
*
* Run code on core 0 of every socket in the system.
*
* @param[in] ApParams AP task pointer.
* @param[in] StdHeader Handle to config for library and services
*
* @return The most severe AGESA_STATUS returned by an AP.
*
*/
AGESA_STATUS
RunLateApTaskOnAllCore0s (
IN AP_EXE_PARAMS *ApParams,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 NumberOfSockets;
UINT8 Socket;
UINT8 ApicId;
UINT32 BscSocket;
UINT32 IgnoredModule;
UINT32 IgnoredCore;
AGESA_STATUS CalledStatus;
AGESA_STATUS IgnoredStatus;
AGESA_STATUS AgesaStatus;
ASSERT (IsBsp (StdHeader, &IgnoredStatus));
AgesaStatus = AGESA_SUCCESS;
IdentifyCore (StdHeader, &BscSocket, &IgnoredModule, &IgnoredCore, &IgnoredStatus);
NumberOfSockets = GetPlatformNumberOfSockets ();
for (Socket = 0; Socket < NumberOfSockets; Socket++) {
if (IsProcessorPresent (Socket, StdHeader)) {
if (Socket != BscSocket) {
GetApicId (StdHeader, Socket, 0, &ApicId, &IgnoredStatus);
AGESA_TESTPOINT (TpIfBeforeRunApFromAllCore0s, StdHeader);
CalledStatus = AgesaRunFcnOnAp ((UINTN) ApicId, ApParams);
AGESA_TESTPOINT (TpIfAfterRunApFromAllCore0s, StdHeader);
if (CalledStatus > AgesaStatus) {
AgesaStatus = CalledStatus;
}
}
}
}
return AgesaStatus;
}
/**
*
*
* BSC task to run Core0 task at early, must only run on BSC
*
* @param[in] Socket - Socket which run the task
* @param[in] Core - Core which run the task
* @param[in] ApTask - Task for AP
* @param[in,out] StdHeader - The Pointer of AGESA Header
*
*/
VOID
IdsRunCodeOnCoreEarly (
IN UINT8 Socket,
IN UINT8 Core,
IN AP_TASK* ApTask,
IN OUT AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 BscSocket;
UINT32 BscCoreNum;
UINT32 IgnoredModule;
AGESA_STATUS IgnoredSts;
AP_TASK Core0Task;
IDS_EARLY_AP_TASK IdsEarlyTask;
IdentifyCore (StdHeader, &BscSocket, &IgnoredModule, &BscCoreNum, &IgnoredSts);
ASSERT (~((Socket == BscSocket) && (Core == BscCoreNum)));
if ((Socket == BscSocket) || (Core == 0)) {
ApUtilRunCodeOnSocketCore (Socket, Core, ApTask, StdHeader);
} else {
//Init IDS_EARLY_AP_TASK for Core 0
IdsEarlyTask.Ap_Task0.ApTask = *ApTask;
IdsEarlyTask.Ap_Task0.Core = Core;
//Init Parameter buffer, Target core can't get the parameter from pointer, which point to Host Core memory space
ASSERT ((ApTask->DataTransfer.DataSizeInDwords * sizeof (UINT32)) <= IDS_EARLY_AP_TASK_PARA_NUM);
LibAmdMemCopy (&IdsEarlyTask.Parameters[0], ApTask->DataTransfer.DataPtr, sizeof (UINT32) * ApTask->DataTransfer.DataSizeInDwords, StdHeader);
if ((ApTask->DataTransfer.DataSizeInDwords * sizeof (UINT32)) <= IDS_EARLY_AP_TASK_PARA_NUM) {
//Lauch Core0 1st
Core0Task.FuncAddress.PfApTaskI = (PF_AP_TASK_I)IdsCmnTaskCore0Early;
Core0Task.ExeFlags = WAIT_FOR_CORE;
Core0Task.DataTransfer.DataSizeInDwords = SIZE_IN_DWORDS (IDS_EARLY_AP_TASK0) + ApTask->DataTransfer.DataSizeInDwords;
Core0Task.DataTransfer.DataPtr = &IdsEarlyTask;
Core0Task.DataTransfer.DataTransferFlags = 0;
ApUtilRunCodeOnSocketCore (Socket, 0, &Core0Task, StdHeader);
}
}
}
/**
* Enable the C6 C-state
*
* @param[in] EntryPoint Timepoint designator.
* @param[in] PlatformConfig Contains the runtime modifiable feature input data.
* @param[in] StdHeader Config Handle for library, services.
*
* @retval AGESA_SUCCESS Always succeeds.
*
*/
AGESA_STATUS
STATIC
InitializeC6Feature (
IN UINT64 EntryPoint,
IN PLATFORM_CONFIGURATION *PlatformConfig,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 BscSocket;
UINT32 Ignored;
UINT32 BscCoreNum;
UINT32 Core;
UINT32 Socket;
UINT32 NumberOfSockets;
UINT32 NumberOfCores;
AP_TASK TaskPtr;
AMD_CPU_EARLY_PARAMS CpuEarlyParams;
C6_FAMILY_SERVICES *C6FamilyServices;
AGESA_STATUS IgnoredSts;
CpuEarlyParams.PlatformConfig = *PlatformConfig;
TaskPtr.FuncAddress.PfApTaskIC = EnableC6OnSocket;
TaskPtr.DataTransfer.DataSizeInDwords = 2;
TaskPtr.DataTransfer.DataPtr = &EntryPoint;
TaskPtr.DataTransfer.DataTransferFlags = 0;
TaskPtr.ExeFlags = PASS_EARLY_PARAMS;
OptionMultiSocketConfiguration.BscRunCodeOnAllSystemCore0s (&TaskPtr, StdHeader, &CpuEarlyParams);
if (((EntryPoint & (CPU_FEAT_AFTER_POST_MTRR_SYNC | CPU_FEAT_AFTER_RESUME_MTRR_SYNC)) != 0) &&
!(IsSecureS3 (StdHeader))) {
// Load any required microcode patches on both normal boot and resume from S3.
IdentifyCore (StdHeader, &BscSocket, &Ignored, &BscCoreNum, &IgnoredSts);
GetFeatureServicesOfSocket (&C6FamilyServiceTable, BscSocket, (CONST VOID **)&C6FamilyServices, StdHeader);
if (C6FamilyServices != NULL) {
C6FamilyServices->ReloadMicrocodePatchAfterMemInit (StdHeader);
}
// run code on all APs
TaskPtr.DataTransfer.DataSizeInDwords = 0;
TaskPtr.ExeFlags = 0;
NumberOfSockets = GetPlatformNumberOfSockets ();
for (Socket = 0; Socket < NumberOfSockets; Socket++) {
if (IsProcessorPresent (Socket, StdHeader)) {
GetFeatureServicesOfSocket (&C6FamilyServiceTable, Socket, (CONST VOID **)&C6FamilyServices, StdHeader);
if (C6FamilyServices != NULL) {
// run code on all APs
TaskPtr.FuncAddress.PfApTask = C6FamilyServices->ReloadMicrocodePatchAfterMemInit;
if (GetActiveCoresInGivenSocket (Socket, &NumberOfCores, StdHeader)) {
for (Core = 0; Core < NumberOfCores; Core++) {
if ((Socket != BscSocket) || (Core != BscCoreNum)) {
ApUtilRunCodeOnSocketCore ((UINT8) Socket, (UINT8) Core, &TaskPtr, StdHeader);
}
}
}
}
}
}
}
return AGESA_SUCCESS;
}
/**
* Core 0 task to enable message-based C1e on a family 10h CPU.
*
* @param[in] MsgBasedC1eServices Pointer to this CPU's HW C1e family services.
* @param[in] EntryPoint Timepoint designator.
* @param[in] PlatformConfig Contains the runtime modifiable feature input data.
* @param[in] StdHeader Config Handle for library, services.
*
* @return AGESA_SUCCESS Always succeeds.
*
*/
AGESA_STATUS
STATIC
F10InitializeMsgBasedC1e (
IN MSG_BASED_C1E_FAMILY_SERVICES *MsgBasedC1eServices,
IN UINT64 EntryPoint,
IN PLATFORM_CONFIGURATION *PlatformConfig,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 AndMask;
UINT32 Core;
UINT32 Module;
UINT32 OrMask;
UINT32 PciRegister;
UINT32 Socket;
AP_TASK TaskPtr;
PCI_ADDR PciAddress;
AGESA_STATUS IgnoredSts;
if ((EntryPoint & (CPU_FEAT_AFTER_POST_MTRR_SYNC | CPU_FEAT_AFTER_RESUME_MTRR_SYNC)) != 0) {
// Note that this core 0 does NOT have the ability to launch
// any of its cores. Attempting to do so could lead to a system
// hang.
// Set F3xA0[IdleExitEn] = 1
PciAddress.Address.Function = FUNC_3;
PciAddress.Address.Register = PW_CTL_MISC_REG;
AndMask = 0xFFFFFFFF;
OrMask = 0;
((POWER_CTRL_MISC_REGISTER *) &OrMask)->IdleExitEn = 1;
ModifyCurrentSocketPci (&PciAddress, AndMask, OrMask, StdHeader); // F3xA0
// Set F3x188[EnStpGntOnFlushMaskWakeup] = 1
PciAddress.Address.Register = NB_EXT_CFG_LO_REG;
OrMask = 0;
((NB_EXT_CFG_LO_REGISTER *) &OrMask)->EnStpGntOnFlushMaskWakeup = 1;
ModifyCurrentSocketPci (&PciAddress, AndMask, OrMask, StdHeader); // F3x188
// Set F3xD4[MTC1eEn] = 1, F3xD4[CacheFlushImmOnAllHalt] = 1
// Set F3xD4[StutterScrubEn] = 1 if scrubbing is enabled
((CLK_PWR_TIMING_CTRL_REGISTER *) &AndMask)->StutterScrubEn = 0;
OrMask = 0;
((CLK_PWR_TIMING_CTRL_REGISTER *) &OrMask)->MTC1eEn = 1;
((CLK_PWR_TIMING_CTRL_REGISTER *) &OrMask)->CacheFlushImmOnAllHalt = 1;
IdentifyCore (StdHeader, &Socket, &Module, &Core, &IgnoredSts);
for (Module = 0; Module < (UINT8)GetPlatformNumberOfModules (); Module++) {
if (GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts)) {
PciAddress.Address.Function = FUNC_3;
PciAddress.Address.Register = CPTC0_REG;
if (IsDramScrubberEnabled (PciAddress, StdHeader)) {
((CLK_PWR_TIMING_CTRL_REGISTER *) &OrMask)->StutterScrubEn = 1;
} else {
((CLK_PWR_TIMING_CTRL_REGISTER *) &OrMask)->StutterScrubEn = 0;
}
LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
PciRegister &= AndMask;
PciRegister |= OrMask;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciRegister, StdHeader);
}
}
} else if (EntryPoint == CPU_FEAT_AFTER_PM_INIT) {
// At early, this core 0 can launch its subordinate cores.
TaskPtr.FuncAddress.PfApTaskI = F10InitializeMsgBasedC1eOnCore;
TaskPtr.DataTransfer.DataSizeInDwords = 1;
TaskPtr.DataTransfer.DataPtr = &PlatformConfig->C1ePlatformData;
TaskPtr.DataTransfer.DataTransferFlags = 0;
TaskPtr.ExeFlags = WAIT_FOR_CORE;
ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, NULL);
}
return AGESA_SUCCESS;
}
/**
* Family 15h core 0 entry point for performing the family 15h Processor-
* Systemboard Power Delivery Check.
*
* The steps are as follows:
* 1. Starting with P0, loop through all P-states until a passing state is
* found. A passing state is one in which the current required by the
* CPU is less than the maximum amount of current that the system can
* provide to the CPU. If P0 is under the limit, no further action is
* necessary.
* 2. If at least one P-State is under the limit & at least one P-State is
* over the limit, the BIOS must:
* a. If the processor's current P-State is disabled by the power check,
* then the BIOS must request a transition to an enabled P-state
* using MSRC001_0062[PstateCmd] and wait for MSRC001_0063[CurPstate]
* to reflect the new value.
* b. Copy the contents of the enabled P-state MSRs to the highest
* performance P-state locations.
* c. Request a P-state transition to the P-state MSR containing the
* COF/VID values currently applied.
* d. If a subset of boosted P-states are disabled, then copy the contents
* of the highest performance boosted P-state still enabled to the
* boosted P-states that have been disabled.
* e. If all boosted P-states are disabled, then program D18F4x15C[BoostSrc]
* to zero.
* f. Adjust the following P-state parameters affected by the P-state
* MSR copy by subtracting the number of P-states that are disabled
* by the power check.
* 1. F3x64[HtcPstateLimit]
* 2. F3x68[SwPstateLimit]
* 3. F3xDC[PstateMaxVal]
* 3. If all P-States are over the limit, the BIOS must:
* a. If the processor's current P-State is !=F3xDC[PstateMaxVal], then
* write F3xDC[PstateMaxVal] to MSRC001_0062[PstateCmd] and wait for
* MSRC001_0063[CurPstate] to reflect the new value.
* b. If MSRC001_0061[PstateMaxVal]!=000b, copy the contents of the P-state
* MSR pointed to by F3xDC[PstateMaxVal] to the software P0 MSR.
* Write 000b to MSRC001_0062[PstateCmd] and wait for MSRC001_0063
* [CurPstate] to reflect the new value.
* c. Adjust the following P-state parameters to zero:
* 1. F3x64[HtcPstateLimit]
* 2. F3x68[SwPstateLimit]
* 3. F3xDC[PstateMaxVal]
* d. Program D18F4x15C[BoostSrc] to zero.
*
* @param[in] FamilySpecificServices The current Family Specific Services.
* @param[in] CpuEarlyParams Service parameters
* @param[in] StdHeader Config handle for library and services.
*
*/
VOID
F15PmPwrCheck (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT8 DisPsNum;
UINT8 PsMaxVal;
UINT8 Pstate;
UINT32 ProcIddMax;
UINT32 LocalPciRegister;
UINT32 Socket;
UINT32 Module;
UINT32 Core;
UINT32 AndMask;
UINT32 OrMask;
UINT32 PstateLimit;
PCI_ADDR PciAddress;
UINT64 LocalMsrRegister;
AP_TASK TaskPtr;
AGESA_STATUS IgnoredSts;
PWRCHK_ERROR_DATA ErrorData;
UINT32 NumModules;
UINT32 HighCore;
UINT32 LowCore;
UINT32 ModuleIndex;
// get the socket number
IdentifyCore (StdHeader, &Socket, &Module, &Core, &IgnoredSts);
ErrorData.SocketNumber = (UINT8) Socket;
ASSERT (Core == 0);
// get the Max P-state value
for (PsMaxVal = NM_PS_REG - 1; PsMaxVal != 0; --PsMaxVal) {
LibAmdMsrRead (PS_REG_BASE + PsMaxVal, &LocalMsrRegister, StdHeader);
if (((F15_PSTATE_MSR *) &LocalMsrRegister)->PsEnable == 1) {
break;
}
}
ErrorData.HwPstateNumber = (UINT8) (PsMaxVal + 1);
// Starting with P0, loop through all P-states until a passing state is
// found. A passing state is one in which the current required by the
// CPU is less than the maximum amount of current that the system can
// provide to the CPU. If P0 is under the limit, no further action is
// necessary.
DisPsNum = 0;
for (Pstate = 0; Pstate < ErrorData.HwPstateNumber; Pstate++) {
if (FamilySpecificServices->GetProcIddMax (FamilySpecificServices, Pstate, &ProcIddMax, StdHeader)) {
if (ProcIddMax > CpuEarlyParams->PlatformConfig.VrmProperties[CoreVrm].CurrentLimit) {
// Add to event log the Pstate that exceeded the current limit
PutEventLog (AGESA_WARNING,
CPU_EVENT_PM_PSTATE_OVERCURRENT,
Socket, Pstate, 0, 0, StdHeader);
DisPsNum++;
} else {
break;
}
}
}
ErrorData.AllowablePstateNumber = ((PsMaxVal + 1) - DisPsNum);
if (ErrorData.AllowablePstateNumber == 0) {
PutEventLog (AGESA_FATAL,
CPU_EVENT_PM_ALL_PSTATE_OVERCURRENT,
Socket, 0, 0, 0, StdHeader);
}
if (DisPsNum != 0) {
GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts);
PciAddress.Address.Function = FUNC_4;
PciAddress.Address.Register = CPB_CTRL_REG;
LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); // F4x15C
ErrorData.NumberOfBoostStates = (UINT8) ((F15_CPB_CTRL_REGISTER *) &LocalPciRegister)->NumBoostStates;
if (DisPsNum >= ErrorData.NumberOfBoostStates) {
// If all boosted P-states are disabled, then program D18F4x15C[BoostSrc] to zero.
AndMask = 0xFFFFFFFF;
((F15_CPB_CTRL_REGISTER *) &AndMask)->BoostSrc = 0;
OrMask = 0x00000000;
OptionMultiSocketConfiguration.ModifyCurrSocketPci (&PciAddress, AndMask, OrMask, StdHeader); // F4x15C
// Update the result of isFeatureEnabled in heap.
UpdateFeatureStatusInHeap (CoreBoost, FALSE, StdHeader);
ErrorData.NumberOfSwPstatesDisabled = DisPsNum - ErrorData.NumberOfBoostStates;
} else {
ErrorData.NumberOfSwPstatesDisabled = 0;
}
NumModules = GetPlatformNumberOfModules ();
// Only execute this loop if this is an MCM.
if (NumModules > 1) {
// Since the P-State MSRs are shared across a
// node, we only need to set one core in the node for the modified number of supported p-states
// to be reported across all of the cores in the module.
TaskPtr.FuncAddress.PfApTaskI = F15PmPwrCheckCore;
TaskPtr.DataTransfer.DataSizeInDwords = SIZE_IN_DWORDS (PWRCHK_ERROR_DATA);
TaskPtr.DataTransfer.DataPtr = &ErrorData;
TaskPtr.DataTransfer.DataTransferFlags = 0;
TaskPtr.ExeFlags = WAIT_FOR_CORE;
for (ModuleIndex = 0; ModuleIndex < NumModules; ModuleIndex++) {
// Execute the P-State reduction code on the module's primary core only.
// Skip this code for the BSC's module.
if (ModuleIndex != Module) {
if (GetGivenModuleCoreRange (Socket, ModuleIndex, &LowCore, &HighCore, StdHeader)) {
ApUtilRunCodeOnSocketCore ((UINT8)Socket, (UINT8)LowCore, &TaskPtr, StdHeader);
}
}
}
}
// Path for SCM and the BSC
F15PmPwrCheckCore (&ErrorData, StdHeader);
// Final Step
// F3x64[HtPstatelimit] -= disPsNum
// F3x68[SwPstateLimit] -= disPsNum
// F3xDC[PstateMaxVal] -= disPsNum
PciAddress.Address.Function = FUNC_3;
PciAddress.Address.Register = HTC_REG;
AndMask = 0xFFFFFFFF;
((HTC_REGISTER *) &AndMask)->HtcPstateLimit = 0;
OrMask = 0x00000000;
LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); // F3x64
PstateLimit = ((HTC_REGISTER *) &LocalPciRegister)->HtcPstateLimit;
if (PstateLimit > ErrorData.NumberOfSwPstatesDisabled) {
PstateLimit -= ErrorData.NumberOfSwPstatesDisabled;
((HTC_REGISTER *) &OrMask)->HtcPstateLimit = PstateLimit;
}
OptionMultiSocketConfiguration.ModifyCurrSocketPci (&PciAddress, AndMask, OrMask, StdHeader); // F3x64
PciAddress.Address.Register = SW_PS_LIMIT_REG;
AndMask = 0xFFFFFFFF;
((SW_PS_LIMIT_REGISTER *) &AndMask)->SwPstateLimit = 0;
OrMask = 0x00000000;
LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); // F3x68
PstateLimit = ((SW_PS_LIMIT_REGISTER *) &LocalPciRegister)->SwPstateLimit;
if (PstateLimit > ErrorData.NumberOfSwPstatesDisabled) {
PstateLimit -= ErrorData.NumberOfSwPstatesDisabled;
((SW_PS_LIMIT_REGISTER *) &OrMask)->SwPstateLimit = PstateLimit;
}
OptionMultiSocketConfiguration.ModifyCurrSocketPci (&PciAddress, AndMask, OrMask, StdHeader); // F3x68
PciAddress.Address.Register = CPTC2_REG;
AndMask = 0xFFFFFFFF;
((CLK_PWR_TIMING_CTRL2_REGISTER *) &AndMask)->PstateMaxVal = 0;
OrMask = 0x00000000;
LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); // F3xDC
PstateLimit = ((CLK_PWR_TIMING_CTRL2_REGISTER *) &LocalPciRegister)->PstateMaxVal;
if (PstateLimit > ErrorData.NumberOfSwPstatesDisabled) {
PstateLimit -= ErrorData.NumberOfSwPstatesDisabled;
((CLK_PWR_TIMING_CTRL2_REGISTER *) &OrMask)->PstateMaxVal = PstateLimit;
}
OptionMultiSocketConfiguration.ModifyCurrSocketPci (&PciAddress, AndMask, OrMask, StdHeader); // F3xDC
}
}
/**
* Multisocket call to determine the most severe AGESA_STATUS return value after
* processing the power management initialization tables.
*
* This function loops through all possible socket locations, collecting any
* power management initialization errors that may have occurred. These errors
* are transferred from the core 0s of the socket in which the errors occurred
* to the BSC's heap. The BSC's heap is then searched for the most severe error
* that occurred, and returns it. This function must be called by the BSC only.
*
* @param[in] StdHeader Config handle for library and services
*
* @return The most severe error code from power management init
*
*/
AGESA_STATUS
GetEarlyPmErrorsMulti (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT16 i;
UINT32 BscSocket;
UINT32 BscModule;
UINT32 BscCoreNum;
UINT32 Socket;
UINT32 NumberOfSockets;
AP_TASK TaskPtr;
AGESA_EVENT EventLogEntry;
AGESA_STATUS ReturnCode;
AGESA_STATUS DummyStatus;
ASSERT (IsBsp (StdHeader, &ReturnCode));
ReturnCode = AGESA_SUCCESS;
EventLogEntry.EventClass = AGESA_SUCCESS;
EventLogEntry.EventInfo = 0;
EventLogEntry.DataParam1 = 0;
EventLogEntry.DataParam2 = 0;
EventLogEntry.DataParam3 = 0;
EventLogEntry.DataParam4 = 0;
NumberOfSockets = GetPlatformNumberOfSockets ();
IdentifyCore (StdHeader, &BscSocket, &BscModule, &BscCoreNum, &DummyStatus);
TaskPtr.FuncAddress.PfApTaskI = GetNextEvent;
TaskPtr.DataTransfer.DataSizeInDwords = SIZE_IN_DWORDS (AGESA_EVENT);
TaskPtr.DataTransfer.DataPtr = &EventLogEntry;
TaskPtr.DataTransfer.DataTransferFlags = 0;
TaskPtr.ExeFlags = WAIT_FOR_CORE | RETURN_PARAMS;
for (Socket = 0; Socket < NumberOfSockets; Socket++) {
if (Socket != BscSocket) {
if (IsProcessorPresent (Socket, StdHeader)) {
do {
ApUtilRunCodeOnSocketCore ((UINT8)Socket, (UINT8) 0, &TaskPtr, StdHeader);
if ((EventLogEntry.EventInfo & CPU_EVENT_PM_EVENT_MASK) == CPU_EVENT_PM_EVENT_CLASS) {
PutEventLog (
EventLogEntry.EventClass,
EventLogEntry.EventInfo,
EventLogEntry.DataParam1,
EventLogEntry.DataParam2,
EventLogEntry.DataParam3,
EventLogEntry.DataParam4,
StdHeader
);
}
} while (EventLogEntry.EventInfo != 0);
}
}
}
for (i = 0; PeekEventLog (&EventLogEntry, i, StdHeader); i++) {
if ((EventLogEntry.EventInfo & CPU_EVENT_PM_EVENT_MASK) == CPU_EVENT_PM_EVENT_CLASS) {
if (EventLogEntry.EventClass > ReturnCode) {
ReturnCode = EventLogEntry.EventClass;
}
}
}
return (ReturnCode);
}
/**
* Family 10h core 0 entry point for performing the family 10h Processor-
* Systemboard Power Delivery Check.
*
* The steps are as follows:
* 1. Starting with P0, loop through all P-states until a passing state is
* found. A passing state is one in which the current required by the
* CPU is less than the maximum amount of current that the system can
* provide to the CPU. If P0 is under the limit, no further action is
* necessary.
* 2. If at least one P-State is under the limit & at least one P-State is
* over the limit, the BIOS must:
* a. If the processor's current P-State is disabled by the power check,
* then the BIOS must request a transition to an enabled P-state
* using MSRC001_0062[PstateCmd] and wait for MSRC001_0063[CurPstate]
* to reflect the new value.
* b. Copy the contents of the enabled P-state MSRs to the highest
* performance P-state locations.
* c. Request a P-state transition to the P-state MSR containing the
* COF/VID values currently applied.
* d. On revision E systems with CPUID Fn8000_0007[CPB]=1, if P0 is disabled then
* program F4x15C[BoostSrc]=0. This step uses hardware P-state numbering.
* e. Adjust the following P-state parameters affected by the P-state
* MSR copy by subtracting the number of P-states that are disabled
* by the power check.
* 1. F3x64[HtcPstateLimit]
* 2. F3x68[StcPstateLimit]
* 3. F3xDC[PstateMaxVal]
* 3. If all P-States are over the limit, the BIOS must:
* a. If the processor's current P-State is !=F3xDC[PstateMaxVal], then
* write F3xDC[PstateMaxVal] to MSRC001_0062[PstateCmd] and wait for
* MSRC001_0063[CurPstate] to reflect the new value.
* b. If F3xDC[PstateMaxVal]!= 000b, copy the contents of the P-state
* MSR pointed to by F3xDC[PstateMaxVal] to MSRC001_0064 and set
* MSRC001_0064[PstateEn]
* c. Write 000b to MSRC001_0062[PstateCmd] and wait for MSRC001_0063
* [CurPstate] to reflect the new value.
* d. Adjust the following P-state parameters to zero on revision D and earlier processors.
* On revision E processors adjust the following fields to F4x15C[NumBoostStates]:
* 1. F3x64[HtcPstateLimit]
* 2. F3x68[StcPstateLimit]
* 3. F3xDC[PstateMaxVal]
* e. For revision E systems with CPUID Fn8000_0007[CPB]=1, program F4x15C[BoostSrc]=0.
*
* @param[in] FamilySpecificServices The current Family Specific Services.
* @param[in] CpuEarlyParams Service parameters
* @param[in] StdHeader Config handle for library and services.
*
*/
VOID
F10PmPwrCheck (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT8 DisPsNum;
UINT8 PsMaxVal;
UINT8 Pstate;
UINT32 ProcIddMax;
UINT32 LocalPciRegister;
UINT32 Socket;
UINT32 Module;
UINT32 Core;
UINT32 AndMask;
UINT32 OrMask;
UINT32 PstateLimit;
PCI_ADDR PciAddress;
UINT64 LocalMsrRegister;
AP_TASK TaskPtr;
AGESA_STATUS IgnoredSts;
PWRCHK_ERROR_DATA ErrorData;
// get the socket number
IdentifyCore (StdHeader, &Socket, &Module, &Core, &IgnoredSts);
ErrorData.SocketNumber = (UINT8)Socket;
ASSERT (Core == 0);
// get the Max P-state value
for (PsMaxVal = NM_PS_REG - 1; PsMaxVal != 0; --PsMaxVal) {
LibAmdMsrRead (PS_REG_BASE + PsMaxVal, &LocalMsrRegister, StdHeader);
if (((PSTATE_MSR *) &LocalMsrRegister)->PsEnable == 1) {
break;
}
}
ErrorData.HwPstateNumber = (UINT8) (PsMaxVal + 1);
DisPsNum = 0;
for (Pstate = 0; Pstate < ErrorData.HwPstateNumber; Pstate++) {
if (FamilySpecificServices->GetProcIddMax (FamilySpecificServices, Pstate, &ProcIddMax, StdHeader)) {
if (ProcIddMax > CpuEarlyParams->PlatformConfig.VrmProperties[CoreVrm].CurrentLimit) {
// Add to event log the Pstate that exceeded the current limit
PutEventLog (AGESA_WARNING,
CPU_EVENT_PM_PSTATE_OVERCURRENT,
Socket, Pstate, 0, 0, StdHeader);
DisPsNum++;
} else {
break;
}
}
}
// If all P-state registers are disabled, move P[PsMaxVal] to P0
// and transition to P0, then wait for CurPstate = 0
ErrorData.AllowablePstateNumber = ((PsMaxVal + 1) - DisPsNum);
// We only need to log this event on the BSC
if (ErrorData.AllowablePstateNumber == 0) {
PutEventLog (AGESA_FATAL,
CPU_EVENT_PM_ALL_PSTATE_OVERCURRENT,
Socket, 0, 0, 0, StdHeader);
}
if (DisPsNum != 0) {
GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts);
// Check if CPB is supported. if yes, get the number of boost states.
ErrorData.NumberofBoostStates = F10GetNumberOfBoostedPstatesOnCore (StdHeader);
TaskPtr.FuncAddress.PfApTaskI = F10PmPwrCheckCore;
TaskPtr.DataTransfer.DataSizeInDwords = SIZE_IN_DWORDS (PWRCHK_ERROR_DATA);
TaskPtr.DataTransfer.DataPtr = &ErrorData;
TaskPtr.DataTransfer.DataTransferFlags = 0;
TaskPtr.ExeFlags = WAIT_FOR_CORE;
ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, CpuEarlyParams);
// Final Step 1
// For revision E systems with CPUID Fn8000_0007[CPB]=1, if P0 is disabled then
// program F4x15C[BoostSrc]=0. This step uses hardware P-state numbering.
if (ErrorData.NumberofBoostStates == 1) {
PciAddress.Address.Function = FUNC_4;
PciAddress.Address.Register = CPB_CTRL_REG;
LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
((CPB_CTRL_REGISTER *) &LocalPciRegister)->BoostSrc = 0;
LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
}
// Final Step 2
// F3x64[HtPstatelimit] -= disPsNum
// F3x68[StcPstateLimit]-= disPsNum
// F3xDC[PstateMaxVal]-= disPsNum
PciAddress.Address.Function = FUNC_3;
PciAddress.Address.Register = HTC_REG;
AndMask = 0xFFFFFFFF;
((HTC_REGISTER *) &AndMask)->HtcPstateLimit = 0;
OrMask = 0x00000000;
LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); // F3x64
PstateLimit = ((HTC_REGISTER *) &LocalPciRegister)->HtcPstateLimit;
if (ErrorData.AllowablePstateNumber != 0) {
if (PstateLimit > DisPsNum) {
PstateLimit -= DisPsNum;
((HTC_REGISTER *) &OrMask)->HtcPstateLimit = PstateLimit;
}
} else {
((HTC_REGISTER *) &OrMask)->HtcPstateLimit = ErrorData.NumberofBoostStates;
}
ModifyCurrentSocketPci (&PciAddress, AndMask, OrMask, StdHeader); // F3x64
PciAddress.Address.Register = STC_REG;
AndMask = 0xFFFFFFFF;
((STC_REGISTER *) &AndMask)->StcPstateLimit = 0;
OrMask = 0x00000000;
LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); // F3x68
PstateLimit = ((STC_REGISTER *) &LocalPciRegister)->StcPstateLimit;
if (ErrorData.AllowablePstateNumber != 0) {
if (PstateLimit > DisPsNum) {
PstateLimit -= DisPsNum;
((STC_REGISTER *) &OrMask)->StcPstateLimit = PstateLimit;
}
} else {
((STC_REGISTER *) &OrMask)->StcPstateLimit = ErrorData.NumberofBoostStates;
}
ModifyCurrentSocketPci (&PciAddress, AndMask, OrMask, StdHeader); // F3x68
PciAddress.Address.Register = CPTC2_REG;
AndMask = 0xFFFFFFFF;
((CLK_PWR_TIMING_CTRL2_REGISTER *) &AndMask)->PstateMaxVal = 0;
OrMask = 0x00000000;
LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); // F3xDC
PstateLimit = ((CLK_PWR_TIMING_CTRL2_REGISTER *) &LocalPciRegister)->PstateMaxVal;
if (ErrorData.AllowablePstateNumber != 0) {
if (PstateLimit > DisPsNum) {
PstateLimit -= DisPsNum;
((CLK_PWR_TIMING_CTRL2_REGISTER *) &OrMask)->PstateMaxVal = PstateLimit;
}
} else {
((CLK_PWR_TIMING_CTRL2_REGISTER *) &OrMask)->PstateMaxVal = ErrorData.NumberofBoostStates;
}
ModifyCurrentSocketPci (&PciAddress, AndMask, OrMask, StdHeader); // F3xDC
// Now that P0 has changed, recalculate VSSlamTime
F10ProgramVSSlamTimeOnSocket (&PciAddress, CpuEarlyParams, StdHeader);
}
}
/**
* Support routine for F10PmAfterReset to perform MSR initialization on all
* cores of a family 10h socket.
*
* This function implements steps 2 - 24 on each core.
*
* @param[in] StdHeader Config handle for library and services.
*
*/
VOID
STATIC
F10PmAfterResetCore (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 Socket;
UINT32 Module;
UINT32 Ignored;
UINT32 PsMaxVal;
UINT32 LocalPciRegister;
UINT64 LocalMsrRegister;
UINT64 SavedMsr;
UINT64 CurrentLimitMsr;
PCI_ADDR PciAddress;
GO_TO_STEP GoToStep;
AGESA_STATUS IgnoredSts;
CPU_LOGICAL_ID LogicalId;
CPU_SPECIFIC_SERVICES *FamilySpecificServices;
// Step 2 If MSR C001_0071[CurNbDid] = 0, set MSR C001_001F[GfxNbPstateDis]
GetLogicalIdOfCurrentCore (&LogicalId, StdHeader);
GetCpuServicesFromLogicalId (&LogicalId, &FamilySpecificServices, StdHeader);
if ((LogicalId.Revision & (AMD_F10_C3 | AMD_F10_DA_C2)) != 0) {
LibAmdMsrRead (MSR_COFVID_STS, &LocalMsrRegister, StdHeader);
if (((COFVID_STS_MSR *) &LocalMsrRegister)->CurNbDid == 0) {
LibAmdMsrRead (NB_CFG, &LocalMsrRegister, StdHeader);
LocalMsrRegister |= BIT62;
LibAmdMsrWrite (NB_CFG, &LocalMsrRegister, StdHeader);
}
}
GoToStep = EXIT_SEQUENCE;
LibAmdMsrRead (MSR_PSTATE_CURRENT_LIMIT, &CurrentLimitMsr, StdHeader);
PsMaxVal = (UINT32) (((PSTATE_CURLIM_MSR *) &CurrentLimitMsr)->PstateMaxVal);
// Step 3 If MSRC001_0071[CurPstate] != F3xDC[PstateMaxVal], go to step 20
LibAmdMsrRead (MSR_COFVID_STS, &LocalMsrRegister, StdHeader);
if (((COFVID_STS_MSR *) &LocalMsrRegister)->CurPstate !=
((PSTATE_CURLIM_MSR *) &CurrentLimitMsr)->PstateMaxVal) {
GoToStep = STEP20;
} else {
// Step 4 If F3xDC[PstateMaxVal] = 0 || F3xDC[PstateMaxVal] != 4, go to step 7
if ((PsMaxVal == 0) || (PsMaxVal != 4)) {
GoToStep = STEP7;
} else {
// Step 5 If MSRC001_0061[CurPstateLimit] <= F3xDC[PstateMaxVal]-1, go to step 17
if (((PSTATE_CURLIM_MSR *) &CurrentLimitMsr)->CurPstateLimit <=
(((PSTATE_CURLIM_MSR *) &CurrentLimitMsr)->PstateMaxVal - 1)) {
GoToStep = STEP17;
}
}
}
switch (GoToStep) {
default:
case EXIT_SEQUENCE:
// Step 6 Exit the sequence
break;
case STEP7:
// Workaround for S3 ----Save the value of [The PState[4:0] Registers] MSRC001_00[68:64]
// pointed to by F3xDC[PstateMaxVal] + 1
LibAmdMsrRead ((MSR_PSTATE_0 + (PsMaxVal + 1)), &SavedMsr, StdHeader);
// Step 7 Copy the P-state register pointed to by F3xDC[PstateMaxVal] to the P-state
// register pointed to by F3xDC[PstateMaxVal]+1
LibAmdMsrRead ((MSR_PSTATE_0 + PsMaxVal), &LocalMsrRegister, StdHeader);
LibAmdMsrWrite ((MSR_PSTATE_0 + (PsMaxVal + 1)), &LocalMsrRegister, StdHeader);
// Step 8 Write F3xDC[PstateMaxVal]+1 to F3xDC[PstateMaxVal]
IdentifyCore (StdHeader, &Socket, &Module, &Ignored, &IgnoredSts);
GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts);
PciAddress.Address.Function = FUNC_3;
PciAddress.Address.Register = CPTC2_REG;
LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
((CLK_PWR_TIMING_CTRL2_REGISTER *) &LocalPciRegister)->PstateMaxVal = PsMaxVal + 1;
LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
// Step 9 Write (the new) F3xDC[PstateMaxVal] to MSRC001_0062[PstateCmd]
FamilySpecificServices->TransitionPstate (FamilySpecificServices, (UINT8) (PsMaxVal + 1), (BOOLEAN) FALSE, StdHeader);
// Step 10 Wait for MSRC001_0071[CurCpuFid/CurCpuDid] = CpuFid/CpuDid from the P-state
// register pointed to by (the new) F3xDC[PstateMaxVal]
WaitForCpuFidAndDidToMatch ((UINT32) (PsMaxVal + 1), StdHeader);
// Step 11 Copy (the new) F3xDC[PstateMaxVal]-1 to MSRC001_0062[PstateCmd]
FamilySpecificServices->TransitionPstate (FamilySpecificServices, (UINT8) PsMaxVal, (BOOLEAN) FALSE, StdHeader);
// Step 12 Wait for MSRC001_0071[CurCpuFid/CurCpuDid] = CpuFid/CpuDid from the P-state
// register pointed to by (the new) F3xDC[PstateMaxVal]-1
WaitForCpuFidAndDidToMatch (PsMaxVal, StdHeader);
// Step 13 If MSRC001_0071[CurNbDid] = 1, set MSRC001_001F[GfxNbPstateDis]
if ((LogicalId.Revision & (AMD_F10_C3 | AMD_F10_DA_C2)) != 0) {
LibAmdMsrRead (MSR_COFVID_STS, &LocalMsrRegister, StdHeader);
if (((COFVID_STS_MSR *) &LocalMsrRegister)->CurNbDid == 1) {
LibAmdMsrRead (NB_CFG, &LocalMsrRegister, StdHeader);
LocalMsrRegister |= BIT62;
LibAmdMsrWrite (NB_CFG, &LocalMsrRegister, StdHeader);
}
}
// Step 14 If required, transition the NB COF and VID to the NbDid and NbVid from the
// P-state register pointed to by MSRC001_0061[CurPstateLimit] using the NB COF
// and VID transition sequence after a warm reset
// Step 15 Write 0 to PstateEn of the P-state register pointed to by (the new) F3xDC[PstateMaxVal]
// Workaround for S3----Restore the value of [The PState[4:0] Registers] MSRC001_00[68:64]
// pointed to by F3xDC[PstateMaxVal] + 1
((PSTATE_MSR *) &SavedMsr)->PsEnable = 0;
LibAmdMsrWrite ((MSR_PSTATE_0 + (PsMaxVal + 1)), &SavedMsr, StdHeader);
// Step 16 Write (the new) F3xDC[PstateMaxVal]-1 to F3xDC[PstateMaxVal]
LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
((CLK_PWR_TIMING_CTRL2_REGISTER *) &LocalPciRegister)->PstateMaxVal = PsMaxVal;
LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
break;
case STEP17:
// Step 17 Copy F3xDC[PstateMaxVal]-1 to MSRC001_0062[PstateCmd]
FamilySpecificServices->TransitionPstate (FamilySpecificServices, (UINT8) (PsMaxVal - 1), (BOOLEAN) FALSE, StdHeader);
// Step 18 Wait for MSRC001_0071[CurCpuFid/CurCpuDid] = CpuFid/CpuDid from the P-state
// register pointed to by F3xDC[PstateMaxVal]-1
WaitForCpuFidAndDidToMatch ((UINT32) (PsMaxVal - 1), StdHeader);
// Step 19 If MSR C001_0071[CurNbDid] = 0, set MSR C001_001F[GfxNbPstateDis]
if ((LogicalId.Revision & (AMD_F10_C3 | AMD_F10_DA_C2)) != 0) {
LibAmdMsrRead (MSR_COFVID_STS, &LocalMsrRegister, StdHeader);
if (((COFVID_STS_MSR *) &LocalMsrRegister)->CurNbDid == 0) {
LibAmdMsrRead (NB_CFG, &LocalMsrRegister, StdHeader);
LocalMsrRegister |= BIT62;
LibAmdMsrWrite (NB_CFG, &LocalMsrRegister, StdHeader);
}
}
// Fall through from step 19 to step 20
case STEP20:
// Step 20 Copy F3xDC[PstateMaxVal] to MSRC001_0062[PstateCmd]
FamilySpecificServices->TransitionPstate (FamilySpecificServices, (UINT8) PsMaxVal, (BOOLEAN) FALSE, StdHeader);
// Step 21 Wait for MSRC001_0071[CurCpuFid/CurCpuDid] = CpuFid/CpuDid from the P-state
// register pointed to by F3xDC[PstateMaxVal]
WaitForCpuFidAndDidToMatch (PsMaxVal, StdHeader);
// Step 22 If MSR C001_0071[CurNbDid] = 1, set MSR C001_001F[GfxNbPstateDis] and exit
// the sequence
if ((LogicalId.Revision & (AMD_F10_C3 | AMD_F10_DA_C2)) != 0) {
LibAmdMsrRead (MSR_COFVID_STS, &LocalMsrRegister, StdHeader);
if (((COFVID_STS_MSR *) &LocalMsrRegister)->CurNbDid == 1) {
LibAmdMsrRead (NB_CFG, &LocalMsrRegister, StdHeader);
LocalMsrRegister |= BIT62;
LibAmdMsrWrite (NB_CFG, &LocalMsrRegister, StdHeader);
break;
}
}
// Step 23 Issue an LDTSTOP and exit the sequence
// Step 24 If required, transition the NB COF and VID to the NbDid and NbVid from the
// P-state register pointed to by F3xDC[PstateMaxVal] using the NB COF and VID
// transition sequence after a warm reset
break;
}
}
/**
*
*
* This is the training function which set up the environment for remote
* training on the ap and launches the remote routine.
*
* @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
*
* @return TRUE - Launch training on AP successfully.
* @return FALSE - Fail to launch training on AP.
*/
BOOLEAN
MemFParallelTrainingHy (
IN OUT MEM_NB_BLOCK *NBPtr
)
{
AMD_CONFIG_PARAMS *StdHeader;
DIE_STRUCT *MCTPtr;
REMOTE_TRAINING_ENV *EnvPtr;
AP_TASK TrainingTask;
UINT8 Socket;
UINT8 Module;
UINT8 APCore;
UINT8 p;
UINT32 LowCore;
UINT32 HighCore;
UINT32 BspSocket;
UINT32 BspModule;
UINT32 BspCore;
AGESA_STATUS Status;
ALLOCATE_HEAP_PARAMS AllocHeapParams;
UINT16 MctDataSize;
StdHeader = &(NBPtr->MemPtr->StdHeader);
MCTPtr = NBPtr->MCTPtr;
Socket = MCTPtr->SocketId;
Module = MCTPtr->DieId;
//
// Allocate buffer for REMOTE_TRAINING_ENV
//
MctDataSize = MAX_DCTS_PER_NODE_HY * (
sizeof (DCT_STRUCT) + (
MAX_CHANNELS_PER_DCT_HY * (sizeof (CH_DEF_STRUCT) + sizeof (MEM_PS_BLOCK))
)
);
AllocHeapParams.RequestedBufferSize = MctDataSize + sizeof (REMOTE_TRAINING_ENV);
AllocHeapParams.BufferHandle = GENERATE_MEM_HANDLE (ALLOC_PAR_TRN_HANDLE, Socket, Module, 0);
AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) == AGESA_SUCCESS) {
EnvPtr = (REMOTE_TRAINING_ENV *) AllocHeapParams.BufferPtr;
AllocHeapParams.BufferPtr += sizeof (REMOTE_TRAINING_ENV);
//
// Setup Remote training environment
//
LibAmdMemCopy (&(EnvPtr->StdHeader), StdHeader, sizeof (AMD_CONFIG_PARAMS), StdHeader);
LibAmdMemCopy (&(EnvPtr->DieStruct), MCTPtr, sizeof (DIE_STRUCT), StdHeader);
for (p = 0; p < MAX_PLATFORM_TYPES; p++) {
EnvPtr->GetPlatformCfg[p] = NBPtr->MemPtr->GetPlatformCfg[p];
}
EnvPtr->ErrorHandling = NBPtr->MemPtr->ErrorHandling;
EnvPtr->NBBlockCtor = MemConstructRemoteNBBlockHY;
EnvPtr->FeatPtr = NBPtr->FeatPtr;
EnvPtr->HoleBase = NBPtr->RefPtr->HoleBase;
EnvPtr->BottomIo = NBPtr->RefPtr->BottomIo;
EnvPtr->UmaSize = NBPtr->RefPtr->UmaSize;
EnvPtr->SysLimit = NBPtr->RefPtr->SysLimit;
EnvPtr->TableBasedAlterations = NBPtr->RefPtr->TableBasedAlterations;
EnvPtr->PlatformMemoryConfiguration = NBPtr->RefPtr->PlatformMemoryConfiguration;
LibAmdMemCopy (AllocHeapParams.BufferPtr, MCTPtr->DctData, MctDataSize, StdHeader);
//
// Get Socket, Core of the BSP
//
IdentifyCore (StdHeader, &BspSocket, &BspModule, &BspCore, &Status);
EnvPtr->BspSocket = ((UINT8)BspSocket & 0x000000FF);
EnvPtr->BspCore = ((UINT8)BspCore & 0x000000FF);
//
// Set up the remote task structure
//
TrainingTask.DataTransfer.DataPtr = EnvPtr;
TrainingTask.DataTransfer.DataSizeInDwords = (UINT16) (AllocHeapParams.RequestedBufferSize + 3) / 4;
TrainingTask.DataTransfer.DataTransferFlags = 0;
TrainingTask.ExeFlags = 0;
TrainingTask.FuncAddress.PfApTaskI = (PF_AP_TASK_I)MemFParallelTraining;
//
// Get Target AP Core
//
GetGivenModuleCoreRange (Socket, Module, &LowCore, &HighCore, StdHeader);
APCore = (UINT8) (LowCore & 0x000000FF);
//
// Launch Remote Training
//
ApUtilRunCodeOnSocketCore (Socket, APCore, &TrainingTask, StdHeader);
HeapDeallocateBuffer (AllocHeapParams.BufferHandle, StdHeader);
return TRUE;
} else {
PutEventLog (AGESA_FATAL, MEM_ERROR_HEAP_ALLOCATE_FOR_REMOTE_TRAINING_ENV, NBPtr->Node, 0, 0, 0, StdHeader);
SetMemError (AGESA_FATAL, MCTPtr);
ASSERT(FALSE); // Could not allocated heap space for "REMOTE_TRAINING_ENV"
return FALSE;
}
}
/**
* Family 10h core 0 entry point for performing the "Northbridge COF and
* VID Configuration" algorithm.
*
* The steps are as follows:
* 1. Determine if the algorithm is necessary by checking if all NB FIDs
* match in the coherent fabric. If so, check to see if NbCofVidUpdate
* is zero for all CPUs. If that is also true, no further steps are
* necessary. If not + cold reset, proceed to step 2. If not + warm
* reset, proceed to step 8.
* 2. Determine NewNbVid & NewNbFid.
* 3. Copy Startup Pstate settings to P0/P1 MSRs on all local cores.
* 4. Copy NewNbVid to P0 NbVid on all local cores.
* 5. Transition to P1 on all local cores.
* 6. Transition to P0 on local core 0 only.
* 7. Copy NewNbFid to F3xD4[NbFid], set NbFidEn, and issue a warm reset.
* 8. Update all enabled Pstate MSRs' NbVids according to NbVidUpdateAll
* on all local cores.
* 9. Transition to Startup Pstate on all local cores.
*
* @param[in] FamilySpecificServices The current Family Specific Services.
* @param[in] CpuEarlyParamsPtr Service related parameters (unused).
* @param[in] StdHeader Config handle for library and services.
*
*/
VOID
F10PmNbCofVidInit (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
BOOLEAN PerformNbCofVidCfg;
BOOLEAN SystemNbCofsMatch;
UINT8 NewNbFid;
UINT8 NewNbVid;
UINT32 Socket;
UINT32 Module;
UINT32 Core;
UINT32 SystemNbCof;
UINT32 AndMask;
UINT32 OrMask;
UINT32 Ignored;
UINT32 NewNbVoltage;
WARM_RESET_REQUEST Request;
AP_TASK TaskPtr;
PCI_ADDR PciAddress;
AGESA_STATUS IgnoredSts;
NB_COF_VID_INIT_WARM FunctionData;
PerformNbCofVidCfg = TRUE;
OptionMultiSocketConfiguration.GetSystemNbCof (&SystemNbCof, &SystemNbCofsMatch, StdHeader);
if (SystemNbCofsMatch) {
if (!OptionMultiSocketConfiguration.GetSystemNbCofVidUpdate (StdHeader)) {
PerformNbCofVidCfg = FALSE;
}
}
if (PerformNbCofVidCfg) {
// get the local node ID
IdentifyCore (StdHeader, &Socket, &Module, &Core, &IgnoredSts);
GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts);
ASSERT (Core == 0);
// get NewNbVid
FamilySpecificServices->GetNbFrequency (FamilySpecificServices, &PciAddress, &Ignored, &NewNbVoltage, StdHeader);
ASSERT (((1550000 - NewNbVoltage) % 12500) == 0);
NewNbVid = (UINT8) ((1550000 - NewNbVoltage) / 12500);
ASSERT (NewNbVid < 0x80);
if (!(IsWarmReset (StdHeader))) {
// determine NewNbFid
NewNbFid = (UINT8) ((SystemNbCof / 200) - 4);
TaskPtr.FuncAddress.PfApTaskI = PmNbCofVidInitP0P1Core;
TaskPtr.DataTransfer.DataSizeInDwords = 1;
TaskPtr.DataTransfer.DataPtr = &NewNbVid;
TaskPtr.DataTransfer.DataTransferFlags = 0;
TaskPtr.ExeFlags = 0;
ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, CpuEarlyParamsPtr);
// Transition core 0 to P0 and wait for change to complete
FamilySpecificServices->TransitionPstate (FamilySpecificServices, (UINT8) 0, (BOOLEAN) TRUE, StdHeader);
PciAddress.Address.Register = CPTC0_REG;
AndMask = 0xFFFFFFFF;
((CLK_PWR_TIMING_CTRL_REGISTER *) &AndMask)->NbFid = 0;
OrMask = 0x00000000;
((CLK_PWR_TIMING_CTRL_REGISTER *) &OrMask)->NbFid = NewNbFid;
((CLK_PWR_TIMING_CTRL_REGISTER *) &OrMask)->NbFidEn = 1;
ModifyCurrentSocketPci (&PciAddress, AndMask, OrMask, StdHeader);
// warm reset request
FamilySpecificServices->GetWarmResetFlag (FamilySpecificServices, StdHeader, &Request);
Request.RequestBit = TRUE;
FamilySpecificServices->SetWarmResetFlag (FamilySpecificServices, StdHeader, &Request);
} else {
// warm reset path
FunctionData.NewNbVid = NewNbVid;
FamilySpecificServices->IsNbCofInitNeeded (FamilySpecificServices, &PciAddress, &FunctionData.NbVidUpdateAll, StdHeader);
TaskPtr.FuncAddress.PfApTaskI = PmNbCofVidInitWarmCore;
TaskPtr.DataTransfer.DataSizeInDwords = SIZE_IN_DWORDS (NB_COF_VID_INIT_WARM);
TaskPtr.DataTransfer.DataPtr = &FunctionData;
TaskPtr.DataTransfer.DataTransferFlags = 0;
TaskPtr.ExeFlags = WAIT_FOR_CORE;
ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, CpuEarlyParamsPtr);
}
} // skip whole algorithm
}
/**
* Family 10h core 0 entry point for performing power plane initialization.
*
* The steps are as follows:
* 1. If single plane, program lower VID code of CpuVid & NbVid for all
* enabled P-States.
* 2. Configure F3xA0[SlamMode] & F3xD8[VsRampTime & VsSlamTime] based on
* platform requirements.
* 3. Configure F3xD4[PowerStepUp & PowerStepDown]
* 4. Optionally configure F3xA0[PsiVidEn & PsiVid]
*
* @param[in] FamilySpecificServices The current Family Specific Services.
* @param[in] CpuEarlyParams Service parameters
* @param[in] StdHeader Config handle for library and services.
*
*/
VOID
F10CpuAmdPmPwrPlaneInit (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
BOOLEAN PviModeFlag;
PCI_ADDR PciAddress;
UINT16 PowerStepTime;
UINT32 PowerStepEncoded;
UINT32 PciRegister;
UINT32 VsSlamTime;
UINT32 Socket;
UINT32 Module;
UINT32 Core;
UINT32 NumOfCores;
UINT32 LowCore;
UINT32 AndMask;
UINT32 OrMask;
UINT64 MsrRegister;
AP_TASK TaskPtr;
AGESA_STATUS IgnoredSts;
PLATFORM_FEATS Features;
CPU_LOGICAL_ID LogicalId;
// Initialize the union
Features.PlatformValue = 0;
GetPlatformFeatures (&Features, &CpuEarlyParams->PlatformConfig, StdHeader);
IdentifyCore (StdHeader, &Socket, &Module, &Core, &IgnoredSts);
GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts);
ASSERT (Core == 0);
GetLogicalIdOfCurrentCore (&LogicalId, StdHeader);
// Set SlamVidMode
PciAddress.Address.Function = FUNC_3;
PciAddress.Address.Register = PW_CTL_MISC_REG;
LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
AndMask = 0xFFFFFFFF;
OrMask = 0x00000000;
if (((POWER_CTRL_MISC_REGISTER *) &PciRegister)->PviMode == 1) {
PviModeFlag = TRUE;
((POWER_CTRL_MISC_REGISTER *) &AndMask)->SlamVidMode = 0;
// Have all single plane cores adjust their NB and CPU VID fields
TaskPtr.FuncAddress.PfApTask = F10PmPwrPlaneInitPviCore;
TaskPtr.DataTransfer.DataSizeInDwords = 0;
TaskPtr.ExeFlags = WAIT_FOR_CORE;
ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, CpuEarlyParams);
} else {
PviModeFlag = FALSE;
((POWER_CTRL_MISC_REGISTER *) &OrMask)->SlamVidMode = 1;
}
ModifyCurrentSocketPci (&PciAddress, AndMask, OrMask, StdHeader);
F10ProgramVSSlamTimeOnSocket (&PciAddress, CpuEarlyParams, StdHeader);
// Configure PowerStepUp/PowerStepDown
PciAddress.Address.Register = CPTC0_REG;
if ((Features.PlatformFeatures.PlatformSingleLink == 1) ||
(Features.PlatformFeatures.PlatformUma == 1) ||
(Features.PlatformFeatures.PlatformUmaIfcm == 1) ||
(Features.PlatformFeatures.PlatformIfcm == 1) ||
(Features.PlatformFeatures.PlatformIommu == 1)) {
PowerStepEncoded = 0x8;
} else {
GetGivenModuleCoreRange ((UINT32) Socket,
(UINT32) Module,
&LowCore,
&NumOfCores,
StdHeader);
NumOfCores = ((NumOfCores - LowCore) + 1);
PowerStepTime = (UINT16) (400 / NumOfCores);
for (PowerStepEncoded = 0xF; PowerStepEncoded > 0; PowerStepEncoded--) {
if (PowerStepTime <= PowerStepEncodings[PowerStepEncoded]) {
break;
}
}
}
AndMask = 0xFFFFFFFF;
((CLK_PWR_TIMING_CTRL_REGISTER *) &AndMask)->PowerStepUp = 0;
((CLK_PWR_TIMING_CTRL_REGISTER *) &AndMask)->PowerStepDown = 0;
OrMask = 0x00000000;
((CLK_PWR_TIMING_CTRL_REGISTER *) &OrMask)->PowerStepUp = PowerStepEncoded;
((CLK_PWR_TIMING_CTRL_REGISTER *) &OrMask)->PowerStepDown = PowerStepEncoded;
ModifyCurrentSocketPci (&PciAddress, AndMask, OrMask, StdHeader);
if ((LogicalId.Revision & AMD_F10_C3) != 0) {
// Set up Pop up P-state register
PciAddress.Address.Register = CPTC2_REG;
LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
AndMask = 0xFFFFFFFF;
((POPUP_PSTATE_REGISTER *) &AndMask)->PopupPstate = 0;
((POPUP_PSTATE_REGISTER *) &AndMask)->PopupCpuVid = 0;
((POPUP_PSTATE_REGISTER *) &AndMask)->PopupCpuFid = 0;
((POPUP_PSTATE_REGISTER *) &AndMask)->PopupCpuDid = 0;
OrMask = 0x00000000;
((POPUP_PSTATE_REGISTER *) &OrMask)->PopupEn = 0;
((POPUP_PSTATE_REGISTER *) &OrMask)->PopupPstate = ((CLK_PWR_TIMING_CTRL2_REGISTER *) &PciRegister)->PstateMaxVal;
LibAmdMsrRead ((((CLK_PWR_TIMING_CTRL2_REGISTER *) &PciRegister)->PstateMaxVal + PS_REG_BASE), &MsrRegister, StdHeader);
((POPUP_PSTATE_REGISTER *) &OrMask)->PopupCpuVid = (UINT32) ((PSTATE_MSR *) &MsrRegister)->CpuVid;
((POPUP_PSTATE_REGISTER *) &OrMask)->PopupCpuFid = (UINT32) ((PSTATE_MSR *) &MsrRegister)->CpuFid;
((POPUP_PSTATE_REGISTER *) &OrMask)->PopupCpuDid = (UINT32) ((PSTATE_MSR *) &MsrRegister)->CpuDid;
PciAddress.Address.Register = POPUP_PSTATE_REG;
ModifyCurrentSocketPci (&PciAddress, AndMask, OrMask, StdHeader);
// Set AltVidStart
PciAddress.Address.Register = CPTC1_REG;
AndMask = 0xFFFFFFFF;
((CLK_PWR_TIMING_CTRL1_REGISTER *) &AndMask)->AltVidStart = 0;
OrMask = 0x00000000;
((CLK_PWR_TIMING_CTRL1_REGISTER *) &OrMask)->AltVidStart = (UINT32) ((PSTATE_MSR *) &MsrRegister)->CpuVid;
ModifyCurrentSocketPci (&PciAddress, AndMask, OrMask, StdHeader);
// Set up Altvid slam time
PciAddress.Address.Register = CPTC2_REG;
VsSlamTime = F10CalculateAltvidVSSlamTimeOnCore (PviModeFlag, &PciAddress, CpuEarlyParams, StdHeader);
AndMask = 0xFFFFFFFF;
((CLK_PWR_TIMING_CTRL2_REGISTER *) &AndMask)->AltvidVSSlamTime = 0;
((CLK_PWR_TIMING_CTRL2_REGISTER *) &AndMask)->SlamTimeMode = 0;
OrMask = 0x00000000;
((CLK_PWR_TIMING_CTRL2_REGISTER *) &OrMask)->AltvidVSSlamTime = VsSlamTime;
((CLK_PWR_TIMING_CTRL2_REGISTER *) &OrMask)->SlamTimeMode = 2;
ModifyCurrentSocketPci (&PciAddress, AndMask, OrMask, StdHeader);
}
if (IsWarmReset (StdHeader) && !PviModeFlag) {
// Configure PsiVid
F10PmVrmLowPowerModeEnable (FamilySpecificServices, CpuEarlyParams, StdHeader);
}
}