void enable_watchdog(void)
{
    printk(KERN_INFO "** enable watchdog\n");
    aml_write_reg32(P_WATCHDOG_RESET, 0);
    aml_write_reg32(P_WATCHDOG_TC, 1 << WATCHDOG_ENABLE_BIT | 0x1FFFFF);//about 20sec

    aml_write_reg32(P_AO_RTI_STATUS_REG1, MESON_NORMAL_BOOT);
}
Example #2
0
static void hpll_load_en(void)
{
//hdmi load gen
    aml_set_reg32_bits(P_HHI_VID_CLK_CNTL, 1, 19, 1);
    aml_set_reg32_bits(P_HHI_VID_CLK_CNTL, 7, 0 , 3);
    aml_set_reg32_bits(P_HHI_VID_CLK_CNTL, 1, 16, 3);  // tmp use fclk_div4
    aml_write_reg32(P_ENCL_VIDEO_EN, 0x1);
    msleep(20);
    aml_write_reg32(P_ENCL_VIDEO_EN, 0x0);
    msleep(20);
//    printk("read Addr: 0x%x[0x%x]  Data: 0x%x\n", P_HHI_HDMI_PLL_CNTL, (P_HHI_HDMI_PLL_CNTL & 0xffff) >> 2, aml_read_reg32(P_HHI_HDMI_PLL_CNTL));
    aml_set_reg32_bits(P_HHI_VID_CLK_CNTL, 0, 16, 3);  // use vid_pll
}
/*
 * if user_pet_count is not 0 and does not chagned in 10s,
 * stop pet, and the watchdog timer will reset.
 */
static void aml_wdt_timer_ping(unsigned long data)
{
	if (user_pet) {
		if(user_pet_debug != 0) {
			pr_info("%s, user_pet:%u user_pet_old:%u user_pet_timer_count:%u\n", __func__,
			user_pet, user_pet_old, user_pet_timer_count);
		}

		if (user_pet_old != user_pet) {
			user_pet_old = user_pet;
			user_pet_timer_count = 0;
		} else
			user_pet_timer_count++;

		if (user_pet_timer_count < user_pet_timer_count_max) {
			aml_wdt_keepalive();
			mod_timer(&ping_timer, jiffies + (ping_timeout * HZ));
		} else {
			/* fixed */
			aml_write_reg32(P_AO_RTI_STATUS_REG0, 0);
			aml_write_reg32(P_AO_RTI_STATUS_REG1, 0x8765a5a);

			if(user_pet_reset_enable == 0) {
				user_pet_timer_count = 0;
				aml_wdt_keepalive();
			}
			pr_info("\n*****SOFTWARE WATCHDOG IS Triggered*********************************\n");
			pr_info("%s, user_pet:%u user_pet_old:%u user_pet_timer_count:%u\n", __func__,
			user_pet, user_pet_old, user_pet_timer_count);
			pr_info("*****SOFTWARE WATCHDOG IS Triggered*********************************\n");
			if(user_pet_reset_enable == 0) {
				mod_timer(&ping_timer, jiffies + (ping_timeout * HZ));
			}
		}
	} else {
		aml_wdt_keepalive();
		mod_timer(&ping_timer, jiffies + (ping_timeout * HZ));
	}
}
/*
 * enable/disable the watchdog reset
 */
static inline void aml_wdt_set_enable(bool enable)
{
	/* NOTES: if we only write the enalbe bit, the other bits of the register
	* will be reset to zero, so we must save the other bits value before we
	* write the enable bit.
	*/
	unsigned int timeout = READ_CBUS_REG_BITS(WATCHDOG_TC, 0, 22);
	reset_enable = enable;

	/* fix reboot by robin.zhu */
	if (enable) {
		aml_write_reg32(P_AO_RTI_STATUS_REG0, 0);
	}

	WRITE_CBUS_REG(WATCHDOG_RESET, 0);
	WRITE_CBUS_REG(WATCHDOG_TC, ((enable ? 1 : 0) << WATCHDOG_ENABLE_BIT) | timeout);
}
static void aml_wdt_hw_init(bool enable, unsigned int timeout)
{
	unsigned int val = 0;
	enable = aml_wdt_get_enable();

	/* fix reboot by robin.zhu */
	if (enable) {
		aml_write_reg32(P_AO_RTI_STATUS_REG0, 0);
	}

	val = (enable ? 1 : 0) << WATCHDOG_ENABLE_BIT;
	timeout = READ_CBUS_REG_BITS(WATCHDOG_TC, 0, 22);
	if ((timeout/0x186a0) < AML_WDT_STARTUP_TIMEOUT)
	timeout = 0x186a0 * AML_WDT_STARTUP_TIMEOUT;
	val |= timeout;
	WRITE_CBUS_REG(WATCHDOG_RESET, 0);
	WRITE_CBUS_REG(WATCHDOG_TC, val);
}
Example #6
0
static int snd_request_hw_timer(void *data)
{
    int ret = 0;
    mutex_lock(&timer_mutex);
    if (hw_timer_init == 0) {
        aml_clr_reg32_mask(P_ISA_TIMER_MUX, ((3 << 4) | (1 << 14) | (1 << 18)));
        aml_set_reg32_mask(P_ISA_TIMER_MUX, ((TIMERB_RESOLUTION << 4)
                                             | (TIMERB_MODE << 14)
                                             | (1 << 18)));
        aml_write_reg32(P_ISA_TIMERC, TIMER_COUNT);
        hw_timer_init = 1;
    }
    mutex_unlock(&timer_mutex);
    ret = request_irq(INT_TIMER_C, audio_isr_handler, IRQF_SHARED, "timerc_irq", data);
    if (ret < 0) {
        printk("audio hw interrupt register fail \n");
        return -1;
    }
    return 0;
}
Example #7
0
static int _switch_gate(mod_type_t type, int flag)
{
	int ret = 0;
	switch(type) {
	case MOD_VDEC:
		PRINT_INFO("turn %s vdec module\n", flag?"on":"off");
		if (flag) {			   
			__CLK_GATE_ON(VLD_CLK);
			__CLK_GATE_ON(IQIDCT_CLK);
			__CLK_GATE_ON(MC_CLK);
			__CLK_GATE_ON(MDEC_CLK_ASSIST);
			__CLK_GATE_ON(MDEC_CLK_DBLK);
			__CLK_GATE_ON(MDEC_CLK_PIC_DC);
			__CLK_GATE_ON(MDEC_CLK_PSC);
		} else {
			__CLK_GATE_OFF(VLD_CLK);
			__CLK_GATE_OFF(IQIDCT_CLK);
			__CLK_GATE_OFF(MC_CLK);
			__CLK_GATE_OFF(MDEC_CLK_ASSIST);
			__CLK_GATE_OFF(MDEC_CLK_DBLK);
			__CLK_GATE_OFF(MDEC_CLK_PIC_DC);
			__CLK_GATE_OFF(MDEC_CLK_PSC);
		}
		break;
	case MOD_AUDIO:
		PRINT_INFO("turn %s audio module\n", flag?"on":"off");
		if (flag) {
			__CLK_GATE_ON(AIU_AI_TOP_GLUE);
			__CLK_GATE_ON(AIU_IEC958);
			__CLK_GATE_ON(AIU_I2S_OUT);
			__CLK_GATE_ON(AIU_AMCLK_MEASURE);
			__CLK_GATE_ON(AIU_AIFIFO2);
			__CLK_GATE_ON(AIU_AUD_MIXER);
			__CLK_GATE_ON(AIU_MIXER_REG);
			__CLK_GATE_ON(AIU_ADC);
			//__CLK_GATE_ON(AIU_PCLK);
			__CLK_GATE_ON(AIU_AOCLK);
			__CLK_GATE_ON(AIU_ICE958_AMCLK);
			
		} else { 
			__CLK_GATE_OFF(AIU_AI_TOP_GLUE);
			__CLK_GATE_OFF(AIU_IEC958);
			__CLK_GATE_OFF(AIU_I2S_OUT);
			__CLK_GATE_OFF(AIU_AMCLK_MEASURE);
			__CLK_GATE_OFF(AIU_AIFIFO2);
			__CLK_GATE_OFF(AIU_AUD_MIXER);
			__CLK_GATE_OFF(AIU_MIXER_REG);
			__CLK_GATE_OFF(AIU_ADC);
			//__CLK_GATE_OFF(AIU_PCLK);
			__CLK_GATE_OFF(AIU_AOCLK);
			__CLK_GATE_OFF(AIU_ICE958_AMCLK);
	  
		}
		break;
	case MOD_HDMI:
		PRINT_INFO("turn %s hdmi module\n", flag?"on":"off");
		if (flag) {
			__CLK_GATE_ON(HDMI_INTR_SYNC);
			__CLK_GATE_ON(HDMI_PCLK);
			__CLK_GATE_ON(VCLK1_HDMI);
		} else {
			__CLK_GATE_OFF(HDMI_INTR_SYNC);
			__CLK_GATE_OFF(HDMI_PCLK);
			__CLK_GATE_OFF(VCLK1_HDMI);
		}			
		break;
	case MOD_VENC:
		PRINT_INFO("turn %s venc module\n", flag?"on":"off");
		if (flag) {
			__CLK_GATE_ON(VCLK2_VENCI);
			__CLK_GATE_ON(VCLK2_VENCI1);
			__CLK_GATE_ON(VCLK2_VENCP);
			__CLK_GATE_ON(VCLK2_VENCP1);
			__CLK_GATE_ON(VCLK2_ENCI);
			__CLK_GATE_ON(VCLK2_ENCP);	
			__CLK_GATE_ON(VCLK2_OTHER);
			__CLK_GATE_ON(VCLK2_OTHER1);
			__CLK_GATE_ON(ENC480P);
			__CLK_GATE_ON(VENC_DAC);
			__CLK_GATE_ON(DAC_CLK);
		} else {
			__CLK_GATE_OFF(VCLK2_VENCI);
			__CLK_GATE_OFF(VCLK2_VENCI1);
			__CLK_GATE_OFF(VCLK2_VENCP);
			__CLK_GATE_OFF(VCLK2_VENCP1);
			__CLK_GATE_OFF(VCLK2_ENCI);  
			__CLK_GATE_OFF(VCLK2_ENCP);
			__CLK_GATE_OFF(VCLK2_OTHER);
			__CLK_GATE_OFF(VCLK2_OTHER1);
			__CLK_GATE_OFF(ENC480P);
			__CLK_GATE_OFF(VENC_DAC);
			__CLK_GATE_OFF(DAC_CLK);
		}
		break;
	case MOD_TCON:
		//PRINT_INFO("turn %s tcon module\n", flag?"on":"off");
		if (flag) {
			__CLK_GATE_ON(VENCT_INT);
			__CLK_GATE_ON(VCLK2_ENCT);
			__CLK_GATE_ON(VCLK2_VENCT);
			__CLK_GATE_ON(VCLK2_VENCT1);
		} else {
			__CLK_GATE_OFF(VENCT_INT);
			__CLK_GATE_OFF(VCLK2_ENCT);
			__CLK_GATE_OFF(VCLK2_VENCT);
			__CLK_GATE_OFF(VCLK2_VENCT1);
		}
		break;
	case MOD_LVDS:
		PRINT_INFO("turn %s lcd module\n", flag?"on":"off");
		if (flag) {
			__CLK_GATE_ON(VENCL_INT);
			__CLK_GATE_ON(VCLK2_ENCL);
			__CLK_GATE_ON(VCLK2_VENCL);
		} else {
			__CLK_GATE_OFF(VENCL_INT);
			__CLK_GATE_OFF(VCLK2_VENCL);
			__CLK_GATE_OFF(VCLK2_ENCL);
		}
		break;
	case MOD_SPI:
		PRINT_INFO("turn %s spi module\n", flag?"on":"off");
		if (flag) {
			__CLK_GATE_ON(SPICC);
			__CLK_GATE_ON(SPI1);
			__CLK_GATE_ON(SPI2);
		} else {
			__CLK_GATE_OFF(SPICC);
			__CLK_GATE_OFF(SPI1);
			__CLK_GATE_OFF(SPI2);
		}
		break;
	case MOD_UART0:
		PRINT_INFO("turn %s uart0 module\n", flag?"on":"off");
		if (flag) {
			__CLK_GATE_ON(UART0);
		} else {
			__CLK_GATE_OFF(UART0);
		}
		break;
	case MOD_UART1:
		PRINT_INFO("turn %s uart1 module\n", flag?"on":"off");
		if (flag) {
			__CLK_GATE_ON(UART1);
		} else {
			__CLK_GATE_OFF(UART1);
		}
		break;
	case MOD_UART2:
		PRINT_INFO("turn %s uart2 module\n", flag?"on":"off");
		if (flag) {
			__CLK_GATE_ON(UART2);
		} else {
			__CLK_GATE_OFF(UART2);
		}
		break;
	case MOD_ROM:
		PRINT_INFO("turn %s rom module\n", flag?"on":"off");
		if (flag) {
			__CLK_GATE_ON(ROM_CLK);
		} else {
			__CLK_GATE_OFF(ROM_CLK);
		}
		break;
	case MOD_EFUSE:
		PRINT_INFO("turn %s efuse module\n", flag?"on":"off");
		if (flag) {
			__CLK_GATE_ON(EFUSE);
		} else {
			__CLK_GATE_OFF(EFUSE);
		}
		break;
	case MOD_RANDOM_NUM_GEN:
		PRINT_INFO("turn %s random_num_gen module\n", flag?"on":"off");
		if (flag) {
			__CLK_GATE_ON(RANDOM_NUM_GEN);
		} else {
			__CLK_GATE_OFF(RANDOM_NUM_GEN);
		}
		break;
	case MOD_ETHERNET:
		PRINT_INFO("turn %s ethernet module\n", flag?"on":"off");
		if (flag) {
			__CLK_GATE_ON(ETHERNET);
		} else {
			__CLK_GATE_OFF(ETHERNET);
		}
		break;
	case MOD_MEDIA_CPU:
		PRINT_INFO("trun %s Audio DSP\n", flag? " on" : "off");
		if(flag){
			__CLK_GATE_ON(MEDIA_CPU);
		}else{
			 __CLK_GATE_OFF(MEDIA_CPU);
		}
		break;
	case MOD_GE2D:
		PRINT_INFO("trun %s GE2D\n", flag? " on" : "off");
		if(flag){
			__CLK_GATE_ON(GE2D);
		}else{
			__CLK_GATE_OFF(GE2D);
		}
		break;
	case MOD_AHB:
		PRINT_INFO("trun %s ahb\n", flag? " on" : "off");
		if(flag){
			__CLK_GATE_ON(AHB_ARB0);
			__CLK_GATE_ON(AHB_BRIDGE);
			__CLK_GATE_ON(AHB_DATA_BUS);
			__CLK_GATE_ON(AHB_CONTROL_BUS);
			__CLK_GATE_ON(AHB_BUS);
			__CLK_GATE_ON(AHB_SRAM);
		}else{
			__CLK_GATE_OFF(AHB_ARB0);
			__CLK_GATE_OFF(AHB_BRIDGE);
			__CLK_GATE_OFF(AHB_DATA_BUS);
			__CLK_GATE_OFF(AHB_CONTROL_BUS);
			__CLK_GATE_OFF(AHB_BUS);
			__CLK_GATE_OFF(AHB_SRAM);
		}
		break;
	case MOD_DEMUX:
		PRINT_INFO("trun %s demux\n", flag? " on" : "off");
		if(flag){
			__CLK_GATE_ON(DEMUX);
		}else{
			__CLK_GATE_OFF(DEMUX);
		}
		break;
	case MOD_SMART_CARD:
		PRINT_INFO("trun %s smart card\n", flag? " on" : "off");
		if(flag){
			__CLK_GATE_ON(SMART_CARD_MPEG_DOMAIN);
		}else{
			__CLK_GATE_OFF(SMART_CARD_MPEG_DOMAIN);
		}
		break;
	case MOD_SDHC:
		PRINT_INFO("trun %s sdhc\n", flag? " on" : "off");
		if(flag){
			__CLK_GATE_ON(SDHC);
		}else{
			__CLK_GATE_OFF(SDHC);
		}
		break;
	case MOD_STREAM:
		PRINT_INFO("trun %s stream\n", flag? " on" : "off");
		if(flag){
			__CLK_GATE_ON(STREAM);
		}else{
			__CLK_GATE_OFF(STREAM);
		}
		break;
	case MOD_BLK_MOV:
		PRINT_INFO("trun %s blk_mov\n", flag? " on" : "off");
		if(flag){
			__CLK_GATE_ON(BLK_MOV);
		}else{
			__CLK_GATE_OFF(BLK_MOV);
		}
		break;
	case MOD_MISC_DVIN:
		PRINT_INFO("trun %s dvin\n", flag? " on" : "off");
		if(flag){
			__CLK_GATE_ON(MISC_DVIN);
		}else{
			__CLK_GATE_OFF(MISC_DVIN);
		}
		break;
        case MOD_MISC_RDMA:
		PRINT_INFO("trun %s rdma\n", flag? " on" : "off");
		if(flag){
			__CLK_GATE_ON(MISC_RDMA);
		}else{
			__CLK_GATE_OFF(MISC_RDMA);
		}
		break;
	case MOD_USB0:
		PRINT_INFO("trun %s rdma\n", flag? " on" : "off");
		if(flag){
			__CLK_GATE_ON(USB0);
			__CLK_GATE_ON(MISC_USB0_TO_DDR);
		}else{
			__CLK_GATE_OFF(USB0);
			__CLK_GATE_OFF(MISC_USB0_TO_DDR);
		}
		break;
	case MOD_USB1:
		PRINT_INFO("trun %s rdma\n", flag? " on" : "off");
		if(flag){
			__CLK_GATE_ON(USB1);
			__CLK_GATE_ON(MISC_USB1_TO_DDR);
		}else{
			__CLK_GATE_OFF(USB1);
			__CLK_GATE_ON(MISC_USB1_TO_DDR);
		}
		break;
	case MOD_SDIO:
		PRINT_INFO("trun %s rdma\n", flag? " on" : "off");
		if(flag){
			__CLK_GATE_ON(SDIO);
		}else{
			__CLK_GATE_OFF(SDIO);
		}
		break;
        case MOD_VI_CORE:
 		PRINT_INFO("trun %s vi core\n", flag? " on" : "off");
 		if(flag){
 			__CLK_GATE_ON(VI_CORE);
 		}else{
 			__CLK_GATE_OFF(VI_CORE);
 		}
 		break;
        case MOD_LED_PWM:
		PRINT_INFO("trun %s led pwm\n", flag? " on" : "off");
		if(flag){
			__CLK_GATE_ON(LED_PWM);
		}else{
			__CLK_GATE_OFF(LED_PWM);
		}
		break;
        case MOD_VDAC:
		printk("trun %s vdac\n", flag? " on" : "off");
		if(flag){
			aml_write_reg32(P_VENC_VDAC_SETTING, 0x0);
		}else{
			aml_write_reg32(P_VENC_VDAC_SETTING, 0xffffffff);
		}
		break;
	default:
		PRINT_INFO("mod type not support\n");
		ret = -1;
		break;
	}
	return ret;
}
Example #8
0
static irqreturn_t vsync_isr(int irq, void *dev_id)
#endif
{
	unsigned  int  fb0_cfg_w0,fb1_cfg_w0;
	unsigned  int  current_field;
	
	if (aml_read_reg32(P_ENCI_VIDEO_EN) & 1)
		osd_hw.scan_mode= SCAN_MODE_INTERLACE;
	else if (aml_read_reg32(P_ENCP_VIDEO_MODE) & (1 << 12))
		osd_hw.scan_mode= SCAN_MODE_INTERLACE;
	else
		osd_hw.scan_mode= SCAN_MODE_PROGRESSIVE;
	
	if(osd_hw.free_scale_enable[OSD1])
	{
		osd_hw.scan_mode= SCAN_MODE_PROGRESSIVE;
	}
	if (osd_hw.scan_mode== SCAN_MODE_INTERLACE)
	{
		fb0_cfg_w0=aml_read_reg32(P_VIU_OSD1_BLK0_CFG_W0);
		fb1_cfg_w0=aml_read_reg32(P_VIU_OSD1_BLK0_CFG_W0+ REG_OFFSET);
		if (aml_read_reg32(P_ENCP_VIDEO_MODE) & (1 << 12))
        	{
       		 /* 1080I */
			 
        		if (aml_read_reg32(P_VENC_ENCP_LINE) >= 562) {
           		 /* bottom field */
           			current_field = 0;
        		} else {
           			current_field = 1;
        		}
    		} else {
        		current_field = aml_read_reg32(P_VENC_STATA) & 1;
    		}
		fb0_cfg_w0 &=~1;
		fb1_cfg_w0 &=~1;
		fb0_cfg_w0 |=current_field;
		fb1_cfg_w0 |=current_field;
		aml_write_reg32(P_VIU_OSD1_BLK0_CFG_W0, fb0_cfg_w0);
		aml_write_reg32(P_VIU_OSD1_BLK1_CFG_W0, fb0_cfg_w0);
		aml_write_reg32(P_VIU_OSD1_BLK2_CFG_W0, fb0_cfg_w0);
		aml_write_reg32(P_VIU_OSD1_BLK3_CFG_W0, fb0_cfg_w0);
		aml_write_reg32(P_VIU_OSD1_BLK0_CFG_W0+ REG_OFFSET, fb1_cfg_w0);
		aml_write_reg32(P_VIU_OSD1_BLK1_CFG_W0+ REG_OFFSET, fb1_cfg_w0);
		aml_write_reg32(P_VIU_OSD1_BLK2_CFG_W0+ REG_OFFSET, fb1_cfg_w0);
		aml_write_reg32(P_VIU_OSD1_BLK3_CFG_W0+ REG_OFFSET, fb1_cfg_w0);
	}

	//go through update list
	walk_through_update_list();
	osd_update_3d_mode(osd_hw.mode_3d[OSD1].enable,osd_hw.mode_3d[OSD2].enable);
	
	if (!vsync_hit)
	{
#ifdef FIQ_VSYNC
		fiq_bridge_pulse_trigger(&osd_hw.fiq_handle_item);
#else
		wait_vsync_wakeup();
#endif
	}

#ifndef FIQ_VSYNC
	return  IRQ_HANDLED ;
#endif
}
void reset_watchdog(void)
{
    //printk(KERN_INFO "** reset watchdog\n");
    aml_write_reg32(P_WATCHDOG_RESET, 0);
}
void disable_watchdog(void)
{
    printk(KERN_INFO "** disable watchdog\n");
    aml_write_reg32(P_WATCHDOG_RESET, 0);
    aml_clr_reg32_mask(P_WATCHDOG_TC,(1 << WATCHDOG_ENABLE_BIT));
}
Example #11
0
static void aml_write_reg32_d(unsigned int addr, unsigned int val)
{
    aml_write_reg32(addr, val);
    //printk("W: 0x%08x  0x%08x %s 0x%08x\n", addr, val, (val == aml_read_reg32(addr)) ? "==" : "!=", aml_read_reg32(addr));
}