vaddr_t pl310_base(void) { static void *va __data; /* in case it's used before .bss is cleared */ if (cpu_mmu_enabled()) { if (!va) va = phys_to_virt(PL310_BASE, MEM_AREA_IO_SEC); return (vaddr_t)va; } return PL310_BASE; }
static vaddr_t console_base(void) { static void *va; if (cpu_mmu_enabled()) { if (!va) va = phys_to_virt(CONSOLE_UART_BASE, MEM_AREA_IO_NSEC); return (vaddr_t)va; } return CONSOLE_UART_BASE; }
static vaddr_t sfr_base(void) { static void *va; if (cpu_mmu_enabled()) { if (!va) va = phys_to_virt(SFR_BASE, MEM_AREA_IO_SEC); return (vaddr_t)va; } return SFR_BASE; }
vaddr_t matrix64_base(void) { static void *va; if (cpu_mmu_enabled()) { if (!va) va = phys_to_virt(AT91C_BASE_MATRIX64, MEM_AREA_IO_SEC); return (vaddr_t)va; } return AT91C_BASE_MATRIX64; }
static vaddr_t console_base(void) { /* in case it's used before .bss is cleared */ static void *va __early_bss; if (cpu_mmu_enabled()) { if (!va) va = phys_to_virt(UART_CONSOLE_BASE, MEM_AREA_IO_NSEC); return (vaddr_t)va; } return UART_CONSOLE_BASE; }
static vaddr_t bckreg_base(void) { static void *va; if (!cpu_mmu_enabled()) return BKP_REGS_BASE + BKP_REGISTER_OFF; if (!va) va = phys_to_virt(BKP_REGS_BASE + BKP_REGISTER_OFF, MEM_AREA_IO_SEC); return (vaddr_t)va; }
int dt_map_dev(const void *fdt, int offs, vaddr_t *base, size_t *size) { enum teecore_memtypes mtype; paddr_t pbase; vaddr_t vbase; ssize_t sz; int st; assert(cpu_mmu_enabled()); st = _fdt_get_status(fdt, offs); if (st == DT_STATUS_DISABLED) return -1; pbase = _fdt_reg_base_address(fdt, offs); if (pbase == (paddr_t)-1) return -1; sz = _fdt_reg_size(fdt, offs); if (sz < 0) return -1; if ((st & DT_STATUS_OK_SEC) && !(st & DT_STATUS_OK_NSEC)) mtype = MEM_AREA_IO_SEC; else mtype = MEM_AREA_IO_NSEC; /* Check if we have a mapping, create one if needed */ if (!core_mmu_add_mapping(mtype, pbase, sz)) { EMSG("Failed to map %zu bytes at PA 0x%"PRIxPA, (size_t)sz, pbase); return -1; } vbase = (vaddr_t)phys_to_virt(pbase, mtype); if (!vbase) { EMSG("Failed to get VA for PA 0x%"PRIxPA, pbase); return -1; } *base = vbase; *size = sz; return 0; }
paddr_t pa; bool secure; } uarts[] = { [0] = { .pa = 0 }, [1] = { .pa = USART1_BASE, .secure = true, }, [2] = { .pa = USART2_BASE, .secure = false, }, [3] = { .pa = USART3_BASE, .secure = false, }, [4] = { .pa = UART4_BASE, .secure = false, }, [5] = { .pa = UART5_BASE, .secure = false, }, [6] = { .pa = USART6_BASE, .secure = false, }, [7] = { .pa = UART7_BASE, .secure = false, }, [8] = { .pa = UART8_BASE, .secure = false, }, }; COMPILE_TIME_ASSERT(ARRAY_SIZE(uarts) > CFG_STM32_EARLY_CONSOLE_UART); assert(!cpu_mmu_enabled()); if (!uarts[CFG_STM32_EARLY_CONSOLE_UART].pa) return; /* No clock yet bound to the UART console */ console_data.clock = DT_INFO_INVALID_CLOCK; console_data.secure = uarts[CFG_STM32_EARLY_CONSOLE_UART].secure; stm32_uart_init(&console_data, uarts[CFG_STM32_EARLY_CONSOLE_UART].pa); register_serial_console(&console_data.chip); IMSG("Early console on UART#%u", CFG_STM32_EARLY_CONSOLE_UART); }
void *get_dt_blob(void) { assert(cpu_mmu_enabled()); return dt_blob_addr; }