void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { struct sys_info *sysinfo = &sysinfo_car; static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, }; u32 bsp_apicid = 0, val; msr_t msr; if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ /* mov bsp to bus 0xff when > 8 nodes */ set_bsp_node_CHtExtNodeCfgEn(); enumerate_ht_chain(); //enable port80 decoding and southbridge poweron init sb_Poweron_Init(); } post_code(0x30); if (bist == 0) { bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); /* mmconf is inited in init_cpus */ /* All cores run this but the BSP(node0,core0) is the only core that returns. */ } post_code(0x32); enable_rs780_dev8(); sb800_clk_output_48Mhz(); w83627hf_set_clksel_48(PNP_DEV(CONFIG_SIO_PORT, 0)); w83627hf_enable_serial(0, CONFIG_TTYS0_BASE); uart_init(); console_init(); printk(BIOS_DEBUG, "\n"); // dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE); /* Halt if there was a built in self test failure */ report_bist_failure(bist); // Load MPB val = cpuid_eax(1); printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val); printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); printk(BIOS_DEBUG, "bsp_apicid = %02x \n", bsp_apicid); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx); /* Setup sysinfo defaults */ set_sysinfo_in_ram(0); #if CONFIG_UPDATE_CPU_MICROCODE update_microcode(val); #endif post_code(0x33); cpuSetAMDMSR(); post_code(0x34); amd_ht_init(sysinfo); post_code(0x35); /* Setup nodes PCI space and start core 0 AP init. */ finalize_node_setup(sysinfo); /* Setup any mainboard PCI settings etc. */ setup_mb_resource_map(); post_code(0x36); /* wait for all the APs core0 started by finalize_node_setup. */ /* FIXME: A bunch of cores are going to start output to serial at once. It would be nice to fixup prink spinlocks for ROM XIP mode. I think it could be done by putting the spinlock flag in the cache of the BSP located right after sysinfo. */ wait_all_core0_started(); #if CONFIG_LOGICAL_CPUS /* Core0 on each node is configured. Now setup any additional cores. */ printk(BIOS_DEBUG, "start_other_cores()\n"); start_other_cores(); post_code(0x37); wait_all_other_cores_started(bsp_apicid); #endif post_code(0x38); /* run _early_setup before soft-reset. */ rs780_early_setup(); #if CONFIG_SET_FIDVID msr = rdmsr(0xc0010071); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo); post_code(0x39); if (!warm_reset_detect(0)) { // BSP is node 0 init_fidvid_bsp(bsp_apicid, sysinfo->nodes); } else { init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0 } post_code(0x3A); /* show final fid and vid */ msr=rdmsr(0xc0010071); printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo); #endif rs780_htinit(); /* Reset for HT, FIDVID, PLL and errata changes to take affect. */ if (!warm_reset_detect(0)) { print_info("...WARM RESET...\n\n\n"); soft_reset(); die("After soft_reset_x - shouldn't see this message!!!\n"); } post_code(0x3B); /* It's the time to set ctrl in sysinfo now; */ printk(BIOS_DEBUG, "fill_mem_ctrl()\n"); fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); post_code(0x40); // die("Die Before MCT init."); printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); post_code(0x41); /* dump_pci_device_range(PCI_DEV(0, 0x18, 0), 0, 0x200); dump_pci_device_range(PCI_DEV(0, 0x18, 1), 0, 0x200); dump_pci_device_range(PCI_DEV(0, 0x18, 2), 0, 0x200); dump_pci_device_range(PCI_DEV(0, 0x18, 3), 0, 0x200); */ // ram_check(0x00200000, 0x00200000 + (640 * 1024)); // ram_check(0x40200000, 0x40200000 + (640 * 1024)); // die("After MCT init before CAR disabled."); rs780_before_pci_init(); post_code(0x42); post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. post_code(0x43); // Should never see this post code. }
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; post_code(0x30); agesawrapper_amdinitmmio(); post_code(0x31); /* Halt if there was a built in self test failure */ post_code(0x33); report_bist_failure(bist); sb7xx_51xx_enable_wideio(0, 0x1600); /* though UARTs are on the NUVOTON BMC */ wpcm450_enable_dev(WPCM450_SP1, SIO_PORT, CONFIG_TTYS0_BASE); sb7xx_51xx_disable_wideio(0); post_code(0x34); post_code(0x35); console_init(); val = cpuid_eax(1); printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx); post_code(0x37); val = agesawrapper_amdinitreset(); if (val) { printk(BIOS_DEBUG, "agesawrapper_amdinitreset failed: %x \n", val); } else { printk(BIOS_DEBUG, "agesawrapper_amdinitreset passed\n"); } if (!cpu_init_detectedx && boot_cpu()) { post_code(0x38); /* * SR5650/5670/5690 RD890 chipset, read pci config space hang at POR, * Disable all Pcie Bridges to work around It. */ sr56x0_rd890_disable_pcie_bridge(); post_code(0x39); nb_Poweron_Init(); post_code(0x3A); sb_Poweron_Init(); } post_code(0x3B); val = agesawrapper_amdinitearly(); if(val) { printk(BIOS_DEBUG, "agesawrapper_amdinitearly failed: %x \n", val); } else { printk(BIOS_DEBUG, "agesawrapper_amdinitearly passed\n"); } post_code(0x3C); /* W83627DHG pin89,90 function select is RSTOUT3#, RSTOUT2# by default. * In order to access W83795G/ADG HWM using I2C protocol, * we select function to SDA, SCL function (or GP33, GP32 function). */ w83627dhg_enable_i2c(PNP_DEV(0x2E, W83627DHG_SPI)); nb_Ht_Init(); post_code(0x3D); /* Reset for HT, FIDVID, PLL and ucode patch(errata) changes to take affect. */ if (!warm_reset_detect(0)) { print_info("...WARM RESET...\n\n\n"); distinguish_cpu_resets(0); soft_reset(); die("After soft_reset_x - shouldn't see this message!!!\n"); } post_code(0x40); val = agesawrapper_amdinitpost(); if (val) { printk(BIOS_DEBUG, "agesawrapper_amdinitpost failed: %x \n", val); } else { printk(BIOS_DEBUG, "agesawrapper_amdinitpost passed\n"); } post_code(0x41); val = agesawrapper_amdinitenv(); if(val) { printk(BIOS_DEBUG, "agesawrapper_amdinitenv failed: %x \n", val); } printk(BIOS_DEBUG, "agesawrapper_amdinitenv passed\n"); post_code(0x42); post_code(0x50); print_debug("Disabling cache as ram "); disable_cache_as_ram(); print_debug("done\n"); post_code(0x51); copy_and_run(); /* We will not return, Should never see this message and post code. */ print_debug("should not be here -\n"); post_code(0x54); }
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; /* Must come first to enable PCI MMCONF. */ amd_initmmio(); if (!cpu_init_detectedx && boot_cpu()) { post_code(0x30); sb_Poweron_Init(); post_code(0x31); winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); } /* Halt if there was a built in self test failure */ post_code(0x34); report_bist_failure(bist); /* Load MPB */ val = cpuid_eax(1); printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); post_code(0x37); agesawrapper_amdinitreset(); post_code(0x39); agesawrapper_amdinitearly(); int s3resume = acpi_is_wakeup_s3(); if (!s3resume) { post_code(0x40); /* Reboots with outb(3,0x92), outb(4,0xcf9) or triple-fault all * hang, looks like DRAM re-init goes wrong, don't know why. */ val = agesawrapper_amdinitpost(); if (val == 7) /* fatal, amdinitenv below is going to hang */ outb(0x06, 0x0cf9); /* reset system harder instead */ post_code(0x42); agesawrapper_amdinitenv(); amd_initenv(); } else { /* S3 detect */ printk(BIOS_INFO, "S3 detected\n"); post_code(0x60); agesawrapper_amdinitresume(); agesawrapper_amds3laterestore(); post_code(0x61); prepare_for_resume(); } post_code(0x50); copy_and_run(); printk(BIOS_ERR, "Error: copy_and_run() returned!\n"); post_code(0x54); /* Should never see this post code. */ }
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; if (!cpu_init_detectedx && boot_cpu()) { post_code(0x30); sb_Poweron_Init(); post_code(0x31); kbc1100_early_init(CONFIG_SIO_PORT); console_init(); } /* Halt if there was a built in self test failure */ post_code(0x34); report_bist_failure(bist); // Load MPB val = cpuid_eax(1); printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx); post_code(0x35); val = agesawrapper_amdinitmmio(); post_code(0x37); val = agesawrapper_amdinitreset(); if(val) { printk(BIOS_DEBUG, "agesawrapper_amdinitreset failed: %x \n", val); } post_code(0x38); printk(BIOS_DEBUG, "Got past sb800_early_setup\n"); post_code(0x39); val = agesawrapper_amdinitearly (); if(val) { printk(BIOS_DEBUG, "agesawrapper_amdinitearly failed: %x \n", val); } printk(BIOS_DEBUG, "Got past agesawrapper_amdinitearly\n"); post_code(0x40); val = agesawrapper_amdinitpost (); if(val) { printk(BIOS_DEBUG, "agesawrapper_amdinitpost failed: %x \n", val); } printk(BIOS_DEBUG, "Got past agesawrapper_amdinitpost\n"); post_code(0x41); val = agesawrapper_amdinitenv (); if(val) { printk(BIOS_DEBUG, "agesawrapper_amdinitenv failed: %x \n", val); } printk(BIOS_DEBUG, "Got past agesawrapper_amdinitenv\n"); /* Initialize i8259 pic */ post_code(0x41); setup_i8259 (); /* Initialize i8254 timers */ post_code(0x42); setup_i8254 (); post_code(0x50); copy_and_run(0); post_code(0x54); // Should never see this post code. }
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; /* all cores: allow caching of flash chip code and data * (there are no cache-as-ram reliability concerns with family 14h) */ __writemsr (0x20c, (0x0100000000ull - CACHE_ROM_SIZE) | 5); __writemsr (0x20d, (0x1000000000ull - CACHE_ROM_SIZE) | 0x800); /* all cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */ __writemsr (0xc0010062, 0); if (!cpu_init_detectedx && boot_cpu()) { post_code(0x30); sb_Poweron_Init(); post_code(0x31); kbc1100_early_init(CONFIG_SIO_PORT); console_init(); } /* Halt if there was a built in self test failure */ post_code(0x34); report_bist_failure(bist); /* Load MPB */ val = cpuid_eax(1); printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx); post_code(0x35); printk(BIOS_DEBUG, "agesawrapper_amdinitmmio "); val = agesawrapper_amdinitmmio(); if (val) printk(BIOS_DEBUG, "error level: %x \n", val); else printk(BIOS_DEBUG, "passed.\n"); post_code(0x37); printk(BIOS_DEBUG, "agesawrapper_amdinitreset "); val = agesawrapper_amdinitreset(); if (val) printk(BIOS_DEBUG, "error level: %x \n", val); else printk(BIOS_DEBUG, "passed.\n"); post_code(0x39); printk(BIOS_DEBUG, "agesawrapper_amdinitearly "); val = agesawrapper_amdinitearly(); if (val) printk(BIOS_DEBUG, "error level: %x \n", val); else printk(BIOS_DEBUG, "passed.\n"); post_code(0x40); printk(BIOS_DEBUG, "agesawrapper_amdinitpost "); val = agesawrapper_amdinitpost(); if (val) printk(BIOS_DEBUG, "error level: %x \n", val); else printk(BIOS_DEBUG, "passed.\n"); post_code(0x41); printk(BIOS_DEBUG, "agesawrapper_amdinitenv "); val = agesawrapper_amdinitenv(); if (val) printk(BIOS_DEBUG, "error level: %x \n", val); else printk(BIOS_DEBUG, "passed.\n"); post_code(0x50); copy_and_run(); printk(BIOS_ERR, "Error: copy_and_run() returned!\n"); post_code(0x54); /* Should never see this post code. */ }
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; #if CONFIG_HAVE_ACPI_RESUME void *resume_backup_memory; #endif /* * All cores: allow caching of flash chip code and data * (there are no cache-as-ram reliability concerns with family 14h) */ __writemsr (0x20c, (0x0100000000ull - CONFIG_ROM_SIZE) | 5); __writemsr (0x20d, (0x1000000000ull - CONFIG_ROM_SIZE) | 0x800); /* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */ __writemsr (0xc0010062, 0); if (!cpu_init_detectedx && boot_cpu()) { post_code(0x30); sb_Poweron_Init(); post_code(0x31); f81865f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); } /* Halt if there was a built in self test failure */ post_code(0x34); report_bist_failure(bist); /* Load MPB */ val = cpuid_eax(1); printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx); post_code(0x35); printk(BIOS_DEBUG, "agesawrapper_amdinitmmio "); val = agesawrapper_amdinitmmio(); if (val) printk(BIOS_DEBUG, "error level: %x \n", val); else printk(BIOS_DEBUG, "passed.\n"); post_code(0x37); printk(BIOS_DEBUG, "agesawrapper_amdinitreset "); val = agesawrapper_amdinitreset(); if (val) printk(BIOS_DEBUG, "error level: %x \n", val); else printk(BIOS_DEBUG, "passed.\n"); post_code(0x39); printk(BIOS_DEBUG, "agesawrapper_amdinitearly "); val = agesawrapper_amdinitearly (); if (val) printk(BIOS_DEBUG, "error level: %x \n", val); else printk(BIOS_DEBUG, "passed.\n"); #if CONFIG_HAVE_ACPI_RESUME if (!acpi_is_wakeup_early()) { /* Check for S3 resume */ #endif post_code(0x40); printk(BIOS_DEBUG, "agesawrapper_amdinitpost "); val = agesawrapper_amdinitpost (); if (val) printk(BIOS_DEBUG, "error level: %x \n", val); else printk(BIOS_DEBUG, "passed.\n"); post_code(0x42); printk(BIOS_DEBUG, "agesawrapper_amdinitenv "); val = agesawrapper_amdinitenv (); if (val) printk(BIOS_DEBUG, "error level: %x \n", val); else printk(BIOS_DEBUG, "passed.\n"); #if CONFIG_HAVE_ACPI_RESUME } else { /* S3 detect */ printk(BIOS_INFO, "S3 detected\n"); post_code(0x60); printk(BIOS_DEBUG, "agesawrapper_amdinitresume "); val = agesawrapper_amdinitresume(); if (val) printk(BIOS_DEBUG, "error level: %x \n", val); else printk(BIOS_DEBUG, "passed.\n"); printk(BIOS_DEBUG, "agesawrapper_amds3laterestore "); val = agesawrapper_amds3laterestore (); if (val) printk(BIOS_DEBUG, "error level: %x \n", val); else printk(BIOS_DEBUG, "passed.\n"); post_code(0x61); printk(BIOS_DEBUG, "Find resume memory location\n"); resume_backup_memory = backup_resume(); post_code(0x62); printk(BIOS_DEBUG, "Move CAR stack.\n"); move_stack_high_mem(); printk(BIOS_DEBUG, "stack moved to: 0x%x\n", (u32) (resume_backup_memory + HIGH_MEMORY_SAVE)); post_code(0x63); disable_cache_as_ram(); printk(BIOS_DEBUG, "CAR disabled.\n"); set_resume_cache(); /* * Copy the system memory that is in the ramstage area to the * reserved area. */ if (resume_backup_memory) memcpy(resume_backup_memory, (void *)(CONFIG_RAMBASE), HIGH_MEMORY_SAVE); printk(BIOS_DEBUG, "System memory saved. OK to load ramstage.\n"); } #endif /* Initialize i8259 pic */ post_code(0x43); setup_i8259 (); /* Initialize i8254 timers */ post_code(0x44); setup_i8254 (); post_code(0x50); copy_and_run(); printk(BIOS_ERR, "Error: copy_and_run() returned!\n"); post_code(0x54); /* Should never see this post code. */ }
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; /* Must come first to enable PCI MMCONF. */ amd_initmmio(); post_code(0x31); /* Halt if there was a built in self test failure */ post_code(0x33); report_bist_failure(bist); sb7xx_51xx_enable_wideio(0, 0x1600); /* though UARTs are on the NUVOTON BMC */ wpcm450_enable_dev(WPCM450_SP1, 0x164E, CONFIG_TTYS0_BASE); sb7xx_51xx_disable_wideio(0); post_code(0x34); post_code(0x35); console_init(); val = cpuid_eax(1); printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); post_code(0x37); agesawrapper_amdinitreset(); if (!cpu_init_detectedx && boot_cpu()) { post_code(0x38); /* * SR5650/5670/5690 RD890 chipset, read pci config space hang at POR, * Disable all Pcie Bridges to work around It. */ sr56x0_rd890_disable_pcie_bridge(); post_code(0x39); nb_Poweron_Init(); post_code(0x3A); sb_Poweron_Init(); } post_code(0x3B); agesawrapper_amdinitearly(); post_code(0x3C); nb_Ht_Init(); post_code(0x3D); /* Reset for HT, FIDVID, PLL and ucode patch(errata) changes to take affect. */ if (!warm_reset_detect(0)) { printk(BIOS_INFO, "...WARM RESET...\n\n\n"); distinguish_cpu_resets(0); soft_reset(); die("After soft_reset_x - shouldn't see this message!!!\n"); } post_code(0x40); agesawrapper_amdinitpost(); post_code(0x41); agesawrapper_amdinitenv(); post_code(0x42); post_code(0x50); printk(BIOS_DEBUG, "Disabling cache as RAM "); disable_cache_as_ram(); printk(BIOS_DEBUG, "done\n"); post_code(0x51); copy_and_run(); /* We will not return, Should never see this message and post code. */ printk(BIOS_DEBUG, "should not be here -\n"); post_code(0x54); }
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; /* * All cores: allow caching of flash chip code and data * (there are no cache-as-ram reliability concerns with family 14h) */ __writemsr (0x20c, (0x0100000000ull - CACHE_ROM_SIZE) | 5); __writemsr (0x20d, (0x1000000000ull - CACHE_ROM_SIZE) | 0x800); /* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */ __writemsr (0xc0010062, 0); amd_initmmio(); if (!cpu_init_detectedx && boot_cpu()) { post_code(0x30); sb_Poweron_Init(); post_code(0x31); fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); } /* Halt if there was a built in self test failure */ post_code(0x34); report_bist_failure(bist); /* Load MPB */ val = cpuid_eax(1); printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); post_code(0x37); agesawrapper_amdinitreset(); post_code(0x39); agesawrapper_amdinitearly(); int s3resume = acpi_is_wakeup_s3(); if (!s3resume) { post_code(0x40); agesawrapper_amdinitpost(); post_code(0x42); agesawrapper_amdinitenv(); amd_initenv(); } else { /* S3 detect */ printk(BIOS_INFO, "S3 detected\n"); post_code(0x60); agesawrapper_amdinitresume(); agesawrapper_amds3laterestore(); post_code(0x61); prepare_for_resume(); } post_code(0x50); copy_and_run(); printk(BIOS_ERR, "Error: copy_and_run() returned!\n"); post_code(0x54); /* Should never see this post code. */ }
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; if (!cpu_init_detectedx && boot_cpu()) { post_code(0x30); sch4037_early_init (CONFIG_SIO_PORT); /* Detect SMSC SIO1036 LPC Debug Card status */ if (detect_sio1036_chip(0x4E)) { /* Found SMSC SIO1036 LPC Debug Card */ sio1036_early_init(0x4E); } post_code(0x31); console_init(); /* * SR5650/5670/5690 RD890 chipset, read pci config space hang at POR, * Disable all Pcie Bridges to work around It. */ sr56x0_rd890_disable_pcie_bridge(); } post_code(0x32); val = agesawrapper_amdinitmmio(); if (val) { printk(BIOS_DEBUG, "agesawrapper_amdinitmmio failed: %x \n", val); } else { printk(BIOS_DEBUG, "agesawrapper_amdinitmmio passed\n"); } /* Halt if there was a built in self test failure */ post_code(0x33); report_bist_failure(bist); // Load MPB val = cpuid_eax(1); printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx); if(boot_cpu()) { post_code(0x34); sb_Poweron_Init(); } post_code(0x35); val = agesawrapper_amdinitreset(); if (val) { printk(BIOS_DEBUG, "agesawrapper_amdinitreset failed: %x \n", val); } else { printk(BIOS_DEBUG, "agesawrapper_amdinitreset passed\n"); } post_code(0x36); val = agesawrapper_amdinitearly (); if (val) { printk(BIOS_DEBUG, "agesawrapper_amdinitearly failed: %x \n", val); } else { printk(BIOS_DEBUG, "agesawrapper_amdinitearly passed\n"); } post_code(0x37); nb_Poweron_Init(); post_code(0x38); nb_Ht_Init(); post_code(0x39); val = agesawrapper_amdinitpost (); if (val) { printk(BIOS_DEBUG, "agesawrapper_amdinitpost failed: %x \n", val); } else { printk(BIOS_DEBUG, "agesawrapper_amdinitpost passed\n"); } post_code(0x40); val = agesawrapper_amdinitenv (); if (val) { printk(BIOS_DEBUG, "agesawrapper_amdinitenv failed: %x \n", val); } else { printk(BIOS_DEBUG, "agesawrapper_amdinitenv passed\n"); } post_code(0x43); print_debug("Disabling cache as ram "); disable_cache_as_ram(); print_debug("done\n"); post_code(0x44); copy_and_run(); post_code(0x45); // Should never see this post code. }
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; amd_initmmio(); if (!cpu_init_detectedx && boot_cpu()) { post_code(0x30); sch4037_early_init(0x2e); sio1036_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); post_code(0x31); console_init(); /* * SR5650/5670/5690 RD890 chipset, read pci config space hang at POR, * Disable all Pcie Bridges to work around It. */ sr56x0_rd890_disable_pcie_bridge(); } /* Halt if there was a built in self test failure */ post_code(0x33); report_bist_failure(bist); // Load MPB val = cpuid_eax(1); printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); if(boot_cpu()) { post_code(0x34); sb_Poweron_Init(); } post_code(0x35); agesawrapper_amdinitreset(); post_code(0x36); agesawrapper_amdinitearly(); post_code(0x37); nb_Poweron_Init(); post_code(0x38); nb_Ht_Init(); post_code(0x39); agesawrapper_amdinitpost(); post_code(0x40); agesawrapper_amdinitenv(); post_code(0x43); printk(BIOS_DEBUG, "Disabling cache as ram "); disable_cache_as_ram(); printk(BIOS_DEBUG, "done\n"); post_code(0x44); copy_and_run(); post_code(0x45); // Should never see this post code. }
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; msr_t msr; /* * All cores: allow caching of flash chip code and data * (there are no cache-as-ram reliability concerns with family 14h) */ msr.lo = ((0x0100000000ull - CACHE_ROM_SIZE) | 5) & 0xFFFFFFFF; msr.hi = ((0x0100000000ull - CACHE_ROM_SIZE) | 5) >> 32; wrmsr (MSR_MTRR_VARIABLE_BASE6, msr); msr.lo = ((0x1000000000ull - CACHE_ROM_SIZE) | 0x800) & 0xFFFFFFFF; msr.hi = ((0x1000000000ull - CACHE_ROM_SIZE) | 0x800) >> 32; wrmsr (MSR_MTRR_VARIABLE_MASK6, msr); /* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */ msr.lo = 0; msr.hi = 0; wrmsr (MSR_PSTATE_CONTROL, msr); amd_initmmio(); if (!cpu_init_detectedx && boot_cpu()) { post_code(0x30); sb_Poweron_Init(); post_code(0x31); console_init(); } /* Halt if there was a built in self test failure */ post_code(0x34); report_bist_failure(bist); /* Load MPB */ val = cpuid_eax(1); printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); post_code(0x37); agesawrapper_amdinitreset(); post_code(0x39); agesawrapper_amdinitearly(); int s3resume = acpi_is_wakeup_s3(); if (!s3resume) { post_code(0x40); agesawrapper_amdinitpost(); post_code(0x42); agesawrapper_amdinitenv(); amd_initenv(); } else { /* S3 detect */ printk(BIOS_INFO, "S3 detected\n"); post_code(0x60); agesawrapper_amdinitresume(); agesawrapper_amds3laterestore(); post_code(0x61); prepare_for_resume(); } post_code(0x50); copy_and_run(); printk(BIOS_ERR, "Error: copy_and_run() returned!\n"); post_code(0x54); /* Should never see this post code. */ }