/*---------------------------------------------------------------------------*/
int
enc28j60_send(const uint8_t *data, uint16_t datalen)
{
uint16_t dataend;
if(!initialized) {
return -1;
}
/*
1. Appropriately program the ETXST pointer to point to an unused
location in memory. It will point to the per packet control
byte. In the uart_demo, it would be programmed to 0120h. It is
recommended that an even address be used for ETXST.
2. Use the WBM SPI command to write the per packet control byte,
the destination address, the source MAC address, the
type/length and the data payload.
3. Appropriately program the ETXND pointer. It should point to the
last byte in the data payload. In the uart_demo, it would be
programmed to 0156h.
4. Clear EIR.TXIF, set EIE.TXIE and set EIE.INTIE to enable an
interrupt when done (if desired).
5. Start the transmission process by setting
ECON1.TXRTS.
*/
setregbank(ERXTX_BANK);
/* Set up the transmit buffer pointer */
writereg(ETXSTL, TX_BUF_START & 0xff);
writereg(ETXSTH, TX_BUF_START >> 8);
writereg(EWRPTL, TX_BUF_START & 0xff);
writereg(EWRPTH, TX_BUF_START >> 8);
/* Write the transmission control register as the first byte of the
output packet. We write 0x00 to indicate that the default
configuration (the values in MACON3) will be used. */
writedatabyte(0x00); /* MACON3 */
writedata(data, datalen);
/* Write a pointer to the last data byte. */
dataend = TX_BUF_START + datalen;
writereg(ETXNDL, dataend & 0xff);
writereg(ETXNDH, dataend >> 8);
/* Clear EIR.TXIF */
clearregbitfield(EIR, EIR_TXIF);
/* Don't care about interrupts for now */
/* Send the packet */
setregbitfield(ECON1, ECON1_TXRTS);
while((readreg(ECON1) & ECON1_TXRTS) > 0);
#if DEBUG
if((readreg(ESTAT) & ESTAT_TXABRT) != 0) {
uint16_t erdpt;
uint8_t tsv[7];
erdpt = (readreg(ERDPTH) << 8) | readreg(ERDPTL);
writereg(ERDPTL, (dataend + 1) & 0xff);
writereg(ERDPTH, (dataend + 1) >> 8);
readdata(tsv, sizeof(tsv));
writereg(ERDPTL, erdpt & 0xff);
writereg(ERDPTH, erdpt >> 8);
PRINTF("enc28j60: tx err: %d: %02x:%02x:%02x:%02x:%02x:%02x\n"
" tsv: %02x%02x%02x%02x%02x%02x%02x\n", datalen,
0xff & data[0], 0xff & data[1], 0xff & data[2],
0xff & data[3], 0xff & data[4], 0xff & data[5],
tsv[6], tsv[5], tsv[4], tsv[3], tsv[2], tsv[1], tsv[0]);
} else {
/*---------------------------------------------------------------------------*/
int
enc28j60_send(uint8_t *data, uint16_t datalen)
{
int padding = 0;
if(!initialized) {
return -1;
}
/*
1. Appropriately program the ETXST pointer to point to an unused
location in memory. It will point to the per packet control
byte. In the example, it would be programmed to 0120h. It is
recommended that an even address be used for ETXST.
2. Use the WBM SPI command to write the per packet control byte,
the destination address, the source MAC address, the
type/length and the data payload.
3. Appropriately program the ETXND pointer. It should point to the
last byte in the data payload. In the example, it would be
programmed to 0156h.
4. Clear EIR.TXIF, set EIE.TXIE and set EIE.INTIE to enable an
interrupt when done (if desired).
5. Start the transmission process by setting
ECON1.TXRTS.
*/
setregbank(ERXTX_BANK);
/* Set up the transmit buffer pointer */
writereg(ETXSTL, TX_BUF_START & 0xff);
writereg(ETXSTH, TX_BUF_START >> 8);
writereg(EWRPTL, TX_BUF_START & 0xff);
writereg(EWRPTH, TX_BUF_START >> 8);
/* Write the transmission control register as the first byte of the
output packet. We write 0x00 to indicate that the default
configuration (the values in MACON3) will be used. */
#define WITH_MANUAL_PADDING 1
#if WITH_MANUAL_PADDING
#define PADDING_MIN_SIZE 60
writedatabyte(0x0B); /* POVERRIDE, PCRCEN, PHUGEEN. Not PPADEN */
if(datalen < PADDING_MIN_SIZE) {
padding = PADDING_MIN_SIZE - datalen;
} else {
padding = 0;
}
#else /* WITH_MANUAL_PADDING */
writedatabyte(0x00); /* MACON3 */
padding = 0;
#endif /* WITH_MANUAL_PADDING */
/* Write a pointer to the last data byte. */
writereg(ETXNDL, (TX_BUF_START + datalen + 0 + padding) & 0xff);
writereg(ETXNDH, (TX_BUF_START + datalen + 0 + padding) >> 8);
writedata(data, datalen);
if(padding > 0) {
uint8_t padding_buf[60];
memset(padding_buf, 0, padding);
writedata(padding_buf, padding);
}
/* Clear EIR.TXIF */
writereg(EIR, readreg(EIR) & (~EIR_TXIF));
/* Don't care about interrupts for now */
/* Send the packet */
writereg(ECON1, readreg(ECON1) | ECON1_TXRTS);
while((readreg(ECON1) & ECON1_TXRTS) > 0);
if((readreg(ESTAT) & ESTAT_TXABRT) != 0) {
PRINTF("enc28j60: tx err: %d: %02x:%02x:%02x:%02x:%02x:%02x\n", datalen,
0xff&data[0], 0xff&data[1], 0xff&data[2],
0xff&data[3], 0xff&data[4], 0xff&data[5]);
} else {
PRINTF("enc28j60: tx: %d: %02x:%02x:%02x:%02x:%02x:%02x\n", datalen,
0xff&data[0], 0xff&data[1], 0xff&data[2],
0xff&data[3], 0xff&data[4], 0xff&data[5]);
}
sent_packets++;
PRINTF("enc28j60: sent_packets %d\n", sent_packets);
return datalen;
}