//Analyze a subset of chips in a Domain... //This is a mini analysis of some of the chips in the Fabric Domain. int32_t FabricDomain::AnalyzeTheseChips(STEP_CODE_DATA_STRUCT & serviceData, ATTENTION_TYPE attentionType, TARGETING::TargetHandleList & i_chips) { using namespace TARGETING ; PRDF_DENTER( "FabricDomain::AnalyzeTheseChips" ); int32_t l_rc = ~SUCCESS; PRDF_DTRAC( "FabricDomain::AnalyzeTheseChips:: Domain ID = 0x%X", GetId() ); if(i_chips.size() != 0) { for (TargetHandleList::iterator i = i_chips.begin(); i != i_chips.end(); ++i) { PRDF_DTRAC( "FabricDomain::AnalyzeTheseChips::Before--chip=0x%X", PlatServices::getHuid(*i)); } OrderTheseChips(attentionType, i_chips); for (TargetHandleList::iterator i = i_chips.begin(); i != i_chips.end(); ++i) { PRDF_DTRAC( "FabricDomain::AnalyzeTheseChips::After--chip=0x%X", PlatServices::getHuid(*i) ); } //After the Order function is called the first chip should contain the chip to look at. //Look here for the correct LookUp function. I don't think this is working. RuleChip * l_fabChip = FindChipInTheseChips(i_chips[0], i_chips); PRDF_DTRAC( "FabricDomain::AnalyzeTheseChips::Analyzing this one: 0x%X", l_fabChip->GetId() ); if(NULL != l_fabChip) { l_rc = l_fabChip->Analyze(serviceData, attentionType); } else { PRDF_DTRAC( "FabricDomain::AnalyzeTheseChips::l_fabChip is NULL" ); l_rc = ~SUCCESS; } } else { PRDF_DTRAC( "FabricDomain::AnalyzeTheseChips::i_chips = %d", i_chips.size() ); } //Get P7 chip Global FIR data for FFDC for (TargetHandleList::iterator i = i_chips.begin(); i != i_chips.end(); ++i) { RuleChip * l_fabChip = FindChipInTheseChips(*i, i_chips); l_fabChip->CaptureErrorData( serviceData.service_data->GetCaptureData(), Util::hashString("GlobalFIRs")); } PRDF_DEXIT( "FabricDomain::AnalyzeTheseChips" ); return l_rc; }
//Swaps chip at location 0 with a chip at location i_chipToFront void FabricDomain::MoveToFrontInTheseChips(uint32_t i_chipToFront, TARGETING::TargetHandleList & i_chips) { using namespace TARGETING; for (TargetHandleList::iterator i = i_chips.begin()+i_chipToFront; i != i_chips.begin(); i--) { std::swap((*i), (*(i-1))); } }
/** * @brief This function updates the NVDIMM firmware code */ void call_nvdimm_update() { TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace,ENTER_MRK"call_nvdimm_update()"); TARGETING::TargetHandleList l_nvdimmTargetList; TARGETING::TargetHandleList l_procList; TARGETING::getAllChips(l_procList, TARGETING::TYPE_PROC, false); // grab the NVDIMMs under each processor and add to overall list for (auto l_proc : l_procList) { TARGETING::TargetHandleList tmpList = TARGETING::getProcNVDIMMs(l_proc); l_nvdimmTargetList.insert(l_nvdimmTargetList.end(), tmpList.begin(), tmpList.end()); } // Run the nvdimm update function if the list is not empty if ( !l_nvdimmTargetList.empty() ) { TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, "call_nvdimm_update(): found %d nvdimms to check for update", l_nvdimmTargetList.size()); bool updateWorked = NVDIMM::nvdimm_update(l_nvdimmTargetList); if (!updateWorked) { TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, "call_nvdimm_update(): nvdimm update failed"); } } TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace,EXIT_MRK"call_nvdimm_update()"); }
//****************************************************************************** // wrapper function to call proc_build_smp //****************************************************************************** void* call_proc_build_smp( void *io_pArgs ) { errlHndl_t l_errl = NULL; IStepError l_StepError; TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_proc_build_smp entry" ); do { // Get all functional proc chip targets TARGETING::TargetHandleList l_cpuTargetList; getAllChips(l_cpuTargetList, TYPE_PROC); // Collect all valid abus connections and xbus connections TargetPairs_t l_abusConnections; TargetPairs_t l_xbusConnections; l_errl = PbusLinkSvc::getTheInstance().getPbusConnections( l_abusConnections, TYPE_ABUS, false ); if (l_errl) { // Create IStep error log and cross reference error that occurred l_StepError.addErrorDetails( l_errl); // Commit error errlCommit( l_errl, HWPF_COMP_ID ); } // Get XBUS connections l_errl = PbusLinkSvc::getTheInstance().getPbusConnections( l_xbusConnections, TYPE_XBUS, false ); if (l_errl) { // Create IStep error log and cross reference error that occurred l_StepError.addErrorDetails( l_errl); // Commit error errlCommit( l_errl, HWPF_COMP_ID ); } // Populate l_proc_Chips vector for each good processor chip // if a A/X-bus endpoint has a valid connection, then // obtain the proc chip target of the other endpoint of the // connection, build the fapi target to update the corresponding // chip object of this A/X-bus endpoint for the procEntry std::vector<proc_build_smp_proc_chip> l_procChips; // Get the master proc TARGETING::Target * l_masterProc = NULL; (void)TARGETING::targetService(). masterProcChipTargetHandle( l_masterProc ); for (TARGETING::TargetHandleList::const_iterator l_cpuIter = l_cpuTargetList.begin(); l_cpuIter != l_cpuTargetList.end(); ++l_cpuIter) { const TARGETING::Target* l_pTarget = *l_cpuIter; fapi::Target l_fapiproc_target( TARGET_TYPE_PROC_CHIP, (const_cast<TARGETING::Target*>(l_pTarget))); proc_build_smp_proc_chip l_procEntry; l_procEntry.this_chip = l_fapiproc_target; l_procEntry.enable_f0 = false; l_procEntry.enable_f1 = false; if (l_pTarget == l_masterProc) { l_procEntry.master_chip_sys_next = true; } else { l_procEntry.master_chip_sys_next = false; } // Get A-BUS //abus connections were found so can get the a-bus TARGETING::TargetHandleList l_abuses; getChildChiplets( l_abuses, l_pTarget, TYPE_ABUS ); for (TARGETING::TargetHandleList::const_iterator l_abusIter = l_abuses.begin(); l_abusIter != l_abuses.end(); ++l_abusIter) { const TARGETING::Target * l_target = *l_abusIter; uint8_t l_srcID = l_target->getAttr<ATTR_CHIP_UNIT>(); TargetPairs_t::iterator l_itr = l_abusConnections.find(l_target); if ( l_itr == l_abusConnections.end() ) { continue; } fapi::Target l_fapiEndpointTarget(TARGET_TYPE_ABUS_ENDPOINT, (const_cast<TARGETING::Target*>(l_itr->second)) ); switch (l_srcID) { case 0: l_procEntry.a0_chip = l_fapiEndpointTarget; break; case 1: l_procEntry.a1_chip = l_fapiEndpointTarget; break; case 2: l_procEntry.a2_chip = l_fapiEndpointTarget; break; default: break; } const TARGETING::Target *l_pParent = getParentChip( (const_cast<TARGETING::Target*>(l_itr->second))); l_procEntry.f0_node_id = static_cast<proc_fab_smp_node_id>( l_pTarget->getAttr<TARGETING::ATTR_FABRIC_NODE_ID>()); l_procEntry.f1_node_id = static_cast<proc_fab_smp_node_id>( l_pParent->getAttr<TARGETING::ATTR_FABRIC_NODE_ID>()); } // Get X-BUS TARGETING::TargetHandleList l_xbuses; getChildChiplets( l_xbuses, l_pTarget, TYPE_XBUS ); for (TARGETING::TargetHandleList::const_iterator l_xbusIter = l_xbuses.begin(); l_xbusIter != l_xbuses.end(); ++l_xbusIter) { const TARGETING::Target * l_target = *l_xbusIter; uint8_t l_srcID = l_target->getAttr<ATTR_CHIP_UNIT>(); TargetPairs_t::iterator l_itr = l_xbusConnections.find(l_target); if ( l_itr == l_xbusConnections.end() ) { continue; } fapi::Target l_fapiEndpointTarget(TARGET_TYPE_XBUS_ENDPOINT, (const_cast<TARGETING::Target*>(l_itr->second)) ); switch (l_srcID) { case 0: l_procEntry.x0_chip = l_fapiEndpointTarget; break; case 1: l_procEntry.x1_chip = l_fapiEndpointTarget; break; case 2: l_procEntry.x2_chip = l_fapiEndpointTarget; break; case 3: l_procEntry.x3_chip = l_fapiEndpointTarget; break; default: break; } } l_procChips.push_back( l_procEntry ); } // call the HWP with each fapi::Target FAPI_INVOKE_HWP( l_errl, proc_build_smp, l_procChips, SMP_ACTIVATE_PHASE1 ); if(l_errl) { TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, "ERROR : proc_build_smp" ); // Create IStep error log and cross reference error that occurred l_StepError.addErrorDetails(l_errl); // Commit error errlCommit( l_errl, HWPF_COMP_ID ); break; } else { TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, "SUCCESS : proc_build_smp" ); } // At the point where we can now change the proc chips to use // XSCOM rather than FSISCOM which is the default. TARGETING::TargetHandleList procChips; getAllChips(procChips, TYPE_PROC); TARGETING::TargetHandleList::iterator curproc = procChips.begin(); // Loop through all proc chips while(curproc != procChips.end()) { TARGETING::Target* l_proc_target = *curproc; // If the proc chip supports xscom.. if (l_proc_target->getAttr<ATTR_PRIMARY_CAPABILITIES>() .supportsXscom) { ScomSwitches l_switches = l_proc_target->getAttr<ATTR_SCOM_SWITCHES>(); // If Xscom is not already enabled. if ((l_switches.useXscom != 1) || (l_switches.useFsiScom != 0)) { l_switches.useFsiScom = 0; l_switches.useXscom = 1; // Turn off FSI scom and turn on Xscom. l_proc_target->setAttr<ATTR_SCOM_SWITCHES>(l_switches); // Reset the FSI2OPB logic on the new chips l_errl = FSI::resetPib2Opb(l_proc_target); if(l_errl) { TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, "ERROR : resetPib2Opb on %.8X", TARGETING::get_huid(l_proc_target)); // Create IStep error log and cross reference error that occurred l_StepError.addErrorDetails(l_errl); // Commit error errlCommit( l_errl, HWPF_COMP_ID ); break; } } } // Enable PSI interrupts even if can't Xscom as // Pbus is up and interrupts can flow l_errl = INTR::enablePsiIntr(l_proc_target); if(l_errl) { // capture the target data in the elog ErrlUserDetailsTarget(l_proc_target).addToLog( l_errl ); break; } ++curproc; } } while (0); TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_proc_build_smp exit" ); // end task, returning any errorlogs to IStepDisp return l_StepError.getErrorHandle(); }
int32_t FabricDomain::OrderTheseChips(ATTENTION_TYPE attentionType, TARGETING::TargetHandleList & i_chips) { using namespace PluginDef; using namespace TARGETING; PRDF_DENTER( "FabricDomain::OrderTheseChips" ); uint32_t l_internalOnlyCount = 0; uint64_t l_externalDrivers[i_chips.size()]; uint64_t l_wofValues[i_chips.size()]; bool l_internalCS[i_chips.size()]; union { uint64_t * u; CPU_WORD * c; } ptr; uint32_t l_chip = 0; uint32_t l_chipToFront = 0; // Get internal setting and external driver list for each chip. for (TargetHandleList::iterator i = i_chips.begin(); i != i_chips.end(); ++i) { RuleChip * l_fabChip = FindChipInTheseChips(*i, i_chips); ptr.u = &l_externalDrivers[l_chip]; BitString l_externalChips(i_chips.size(), ptr.c); TargetHandleList l_tmpList; if(l_fabChip != NULL) { // Call "GetCheckstopInfo" plugin. ExtensibleChipFunction * l_extFunc = l_fabChip->getExtensibleFunction("GetCheckstopInfo"); (*l_extFunc)(l_fabChip, bindParm<bool &, TargetHandleList &, uint64_t &> (l_internalCS[l_chip], l_tmpList, l_wofValues[l_chip] ) ); } else { l_internalCS[l_chip] = false; PRDF_DTRAC( "FabricDomain::OrderTheseChips: l_fabChip is NULL" ); } //If we are just checking for internal errors then there is no need for //a list of what chips sent checkstops where. // Update bit buffer. for (TargetHandleList::iterator j = l_tmpList.begin(); j != l_tmpList.end(); ++j) { for (uint32_t k = 0; k < i_chips.size(); k++) if ((*j) == LookUp(k)->GetChipHandle()) l_externalChips.Set(k); }; // Check if is internal. if (l_internalCS[l_chip]) { l_internalOnlyCount++; l_chipToFront = l_chip; } l_chip++; //Move to next chip in the list. } // Check if we are done... only one with an internal error. if (1 == l_internalOnlyCount) { MoveToFrontInTheseChips(l_chipToFront, i_chips); return(SUCCESS); } PRDF_DEXIT( "FabricDomain::OrderTheseChips" ); return(SUCCESS); }
void HBVddrMsg::createVddrData( VDDR_MSG_TYPE i_requestType, RequestContainer& io_request) const { TRACFCOMP( g_trac_volt, ENTER_MRK "HBVddrMsg::createVddrData" ); // Go through all the memory buffers and gather their domains, domain // specific IDs, and domain specific voltages io_request.clear(); do{ TARGETING::TargetHandleList membufTargetList; //When request is a disable command, disable all present Centaurs // in case we go through a reconfigure loop if(i_requestType == HB_VDDR_DISABLE) { getChipResources( membufTargetList, TYPE_MEMBUF, UTIL_FILTER_PRESENT ); } //When the request is an enable command, enable only functional // centaurs. else { getAllChips(membufTargetList, TYPE_MEMBUF); } TARGETING::Target* pMembuf =NULL; for (TARGETING::TargetHandleList::const_iterator ppMembuf = membufTargetList.begin(); ppMembuf != membufTargetList.end(); ++ppMembuf) { pMembuf = *ppMembuf; if(i_requestType == HB_VDDR_ENABLE) { (void)addMemoryVoltageDomains< TARGETING::ATTR_MSS_CENT_VDD_OFFSET_DISABLE, TARGETING::ATTR_MEM_VDD_OFFSET_MILLIVOLTS, TARGETING::ATTR_MEM_VDD_OFFSET_MILLIVOLTS, TARGETING::ATTR_VDD_ID>( pMembuf, io_request); (void)addMemoryVoltageDomains< TARGETING::ATTR_MSS_CENT_AVDD_OFFSET_DISABLE, TARGETING::ATTR_MEM_AVDD_OFFSET_MILLIVOLTS, TARGETING::ATTR_MEM_AVDD_OFFSET_MILLIVOLTS, TARGETING::ATTR_AVDD_ID>( pMembuf, io_request); (void)addMemoryVoltageDomains< TARGETING::ATTR_MSS_CENT_VCS_OFFSET_DISABLE, TARGETING::ATTR_MEM_VCS_OFFSET_MILLIVOLTS, TARGETING::ATTR_MEM_VCS_OFFSET_MILLIVOLTS, TARGETING::ATTR_VCS_ID>( pMembuf, io_request); (void)addMemoryVoltageDomains< TARGETING::ATTR_MSS_VOLT_VPP_OFFSET_DISABLE, TARGETING::ATTR_MEM_VPP_OFFSET_MILLIVOLTS, TARGETING::ATTR_VPP_BASE, TARGETING::ATTR_VPP_ID>( pMembuf, io_request); } (void)addMemoryVoltageDomains< TARGETING::ATTR_MSS_VOLT_VDDR_OFFSET_DISABLE, TARGETING::ATTR_MEM_VDDR_OFFSET_MILLIVOLTS, TARGETING::ATTR_MSS_VOLT, TARGETING::ATTR_VMEM_ID>( pMembuf, io_request); } if (membufTargetList.size() > 1) { // Take out the duplicate records in io_request by first // sorting and then removing the duplicates std::sort(io_request.begin(), io_request.end(), compareVids); std::vector<hwsvPowrMemVoltDomainRequest_t>::iterator pInvalidEntries = std::unique( io_request.begin(), io_request.end(), areVidsEqual); io_request.erase(pInvalidEntries,io_request.end()); } if( ( (i_requestType == HB_VDDR_ENABLE) || (i_requestType == HB_VDDR_POST_DRAM_INIT_ENABLE) ) && (!membufTargetList.empty()) ) { // Inhibit sending any request to turn on a domain with no voltage. // When disabling we don't need to do this because the voltage is // ignored. io_request.erase( std::remove_if(io_request.begin(), io_request.end(), isUnusedVoltageDomain),io_request.end()); } } while(0); TRACFCOMP( g_trac_volt, EXIT_MRK "HBVddrMsg::createVddrData" ); return; }
//****************************************************************************** // fenceAttachedMembufs - helper function for hwp proc_cen_ref_clk_enable //****************************************************************************** void fenceAttachedMembufs( TARGETING::Target * i_procTarget ) { errlHndl_t l_errl = NULL; TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, "Fencing attached (present) membuf chips downstream from " "proc chip with HUID of 0x%08X", i_procTarget->getAttr<TARGETING::ATTR_HUID>()); // Get list of membuf chips downstream from the given proc chip TARGETING::TargetHandleList MembufChipList; getChildAffinityTargetsByState( MembufChipList, const_cast<TARGETING::Target*>(i_procTarget ), TARGETING::CLASS_CHIP, TARGETING::TYPE_MEMBUF, TARGETING::UTIL_FILTER_PRESENT); // loop through the membufs for(TARGETING::TargetHandleList::const_iterator pTargetItr = MembufChipList.begin(); pTargetItr != MembufChipList.end(); pTargetItr++) { //Get CFAM "1012" -- FSI GP3 and set bits 23-27 (various fence bits) //Note 1012 is ecmd addressing, real address is 0x1048 (byte) uint64_t l_addr = 0x1048; const uint32_t l_fence_bits= 0x000001F0; uint32_t l_data = 0; size_t l_size = sizeof(uint32_t); l_errl = deviceRead(*pTargetItr, &l_data, l_size, DEVICE_FSI_ADDRESS(l_addr)); if (l_errl) { TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, "Failed getcfam 1012 to HUID 0x%08X, ignoring, skipping", (*pTargetItr)->getAttr<TARGETING::ATTR_HUID>()); delete l_errl; l_errl = NULL; continue; } l_data |= l_fence_bits; l_errl = deviceWrite(*pTargetItr, &l_data, l_size, DEVICE_FSI_ADDRESS(l_addr)); if (l_errl) { TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, "Failed putcfam 1012 to HUID 0x%08X, ignoring, skipping", (*pTargetItr)->getAttr<TARGETING::ATTR_HUID>()); delete l_errl; l_errl = NULL; continue; } } }
//****************************************************************************** // getMembufsAttachedBitMask - helper function for hwp proc_cen_ref_clk_enable //****************************************************************************** uint8_t getMembufsAttachedBitMask( TARGETING::Target * i_procTarget ) { const uint8_t MCS_WITH_ATTACHED_CENTAUR_MASK = 0x80; TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, "Finding functional membuf chips downstream from " "proc chip with HUID of 0x%08X", i_procTarget->getAttr<TARGETING::ATTR_HUID>()); uint8_t l_attachedMembufs = 0; // Get list of functional membuf chips downstream from the given // proc chip TARGETING::TargetHandleList functionalMembufChipList; getChildAffinityTargets( functionalMembufChipList, const_cast<TARGETING::Target*>(i_procTarget ), TARGETING::CLASS_CHIP, TARGETING::TYPE_MEMBUF, true); // loop through the functional membufs for(TARGETING::TargetHandleList::const_iterator pTargetItr = functionalMembufChipList.begin(); pTargetItr != functionalMembufChipList.end(); pTargetItr++) { // Find each functional membuf chip's upstream functional MCS // unit, if any, and accumulate it into the attached membuf // chips mask TARGETING::TargetHandleList functionalMcsUnitList; getParentAffinityTargets( functionalMcsUnitList, *pTargetItr, TARGETING::CLASS_UNIT, TARGETING::TYPE_MCS, true ); if(functionalMcsUnitList.empty()) { TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, "Functional membuf chip with HUID of 0x%08X " "is not attached to an upstream functional MCS", (*pTargetItr)->getAttr< TARGETING::ATTR_HUID>()); continue; } TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, "Found functional MCS unit with HUID of 0x%08X " "upstream from functional membuf chip with HUID of 0x%08X", ((*functionalMcsUnitList.begin())->getAttr< TARGETING::ATTR_CHIP_UNIT>()), (*pTargetItr)->getAttr< TARGETING::ATTR_HUID>()); l_attachedMembufs |= ((MCS_WITH_ATTACHED_CENTAUR_MASK) >> ((*functionalMcsUnitList.begin())->getAttr< TARGETING::ATTR_CHIP_UNIT>())); } TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, "Proc chip with HUID of 0x%08X has attached membuf " "mask (l_attachedMembufs) of 0x%02X", i_procTarget->getAttr<TARGETING::ATTR_HUID>(), l_attachedMembufs); // return the bitmask return l_attachedMembufs; }
//****************************************************************************** // call_proc_cen_ref_clock_enable //****************************************************************************** void* call_proc_cen_ref_clk_enable(void *io_pArgs ) { errlHndl_t l_errl = NULL; IStepError l_stepError; TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_proc_cen_ref_clock_enable enter" ); TARGETING::TargetHandleList functionalProcChipList; getAllChips(functionalProcChipList, TYPE_PROC, true); // loop thru the list of processors for (TargetHandleList::const_iterator l_proc_iter = functionalProcChipList.begin(); l_proc_iter != functionalProcChipList.end(); ++l_proc_iter) { TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, "target HUID %.8X", TARGETING::get_huid( *l_proc_iter )); uint8_t l_membufsAttached = 0; // get a bit mask of present/functional dimms assocated with // this processor l_membufsAttached = getMembufsAttachedBitMask( *l_proc_iter ); //Perform a workaround for GA1 to raise fences on centaurs //to prevent FSP from analyzing if HB TIs for recoverable //errors //RTC 106276 fenceAttachedMembufs( *l_proc_iter ); TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, "passing target HUID %.8X and 0x%x mask", TARGETING::get_huid( *l_proc_iter ), l_membufsAttached ); if( l_membufsAttached ) { fapi::Target l_fapiProcTarget( fapi::TARGET_TYPE_PROC_CHIP, *l_proc_iter ); // Invoke the HWP passing in the proc target and // a bit mask indicating connected centaurs FAPI_INVOKE_HWP(l_errl, proc_cen_ref_clk_enable, l_fapiProcTarget, l_membufsAttached ); if (l_errl) { TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, "ERROR : proc_cen_ref_clk_enable", "failed, returning errorlog" ); // capture the target data in the elog ErrlUserDetailsTarget( *l_proc_iter ).addToLog( l_errl ); // Create IStep error log and cross ref error that occurred l_stepError.addErrorDetails( l_errl ); // Commit error log errlCommit( l_errl, HWPF_COMP_ID ); } else { TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, "SUCCESS : proc_cen_ref_clk_enable", "completed ok"); } } } // endfor TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_proc_cen_ref_clock_enable exit" ); // end task, returning any errorlogs to IStepDisp return l_stepError.getErrorHandle(); }
// ------------------------------------------------------------------ // dimmPresenceDetect // ------------------------------------------------------------------ errlHndl_t dimmPresenceDetect( DeviceFW::OperationType i_opType, TARGETING::Target * i_target, void * io_buffer, size_t & io_buflen, int64_t i_accessType, va_list i_args ) { errlHndl_t err = NULL; bool present = false; size_t presentSz = sizeof(present); TRACSSCOMP( g_trac_spd, ENTER_MRK"dimmPresenceDetect()" ); do { // Check to be sure that the buffer is big enough. if( !(io_buflen >= sizeof(bool)) ) { TRACFCOMP( g_trac_spd, ERR_MRK"dimmPresenceDetect() - Invalid Data Length: %d", io_buflen ); /*@ * @errortype * @reasoncode VPD::VPD_INSUFFICIENT_BUFFER_SIZE * @severity ERRORLOG::ERRL_SEV_UNRECOVERABLE * @moduleid VPD::VPD_SPD_PRESENCE_DETECT * @userdata1 Buffer Length * @userdata2 <UNUSED> * @devdesc Buffer for checking Presence Detect * was not the correct size. */ err = new ERRORLOG::ErrlEntry( ERRORLOG::ERRL_SEV_UNRECOVERABLE, VPD::VPD_SPD_PRESENCE_DETECT, VPD::VPD_INSUFFICIENT_BUFFER_SIZE, TO_UINT64(io_buflen), 0x0, true /*Add HB Software Callout*/); err->collectTrace( "SPD", 256); break; } // Is the target present #ifdef CONFIG_DJVPD_READ_FROM_HW // Check if the parent MBA/MEMBUF is present. If it is not then // no reason to check the DIMM which would otherwise generate // tons of FSI errors. We can't just check if parent MBA // is functional because DIMM presence detect is called before // the parent MBA/MEMBUF is set as present/functional. TARGETING::TargetHandleList membufList; TARGETING::PredicateCTM membufPred( TARGETING::CLASS_CHIP, TARGETING::TYPE_MEMBUF ); TARGETING::targetService().getAssociated( membufList, i_target, TARGETING::TargetService::PARENT_BY_AFFINITY, TARGETING::TargetService::ALL, &membufPred); bool parentPresent = false; const TARGETING::TargetHandle_t membufTarget = *(membufList.begin()); err = deviceRead(membufTarget, &parentPresent, presentSz, DEVICE_PRESENT_ADDRESS()); if (err) { TRACFCOMP( g_trac_spd, "Error reading parent MEMBUF present: huid 0x%X DIMM huid 0x%X", TARGETING::get_huid(membufTarget), TARGETING::get_huid(i_target) ); break; } if (!parentPresent) { present = false; // Invalidate the SPD in PNOR err = VPD::invalidatePnorCache(i_target); if (err) { TRACFCOMP( g_trac_spd, "Error invalidating SPD in PNOR" ); } break; } #endif present = spdPresent( i_target ); if( present == false ) { TRACUCOMP( g_trac_spd, INFO_MRK"Dimm was found to be NOT present." ); } else { TRACUCOMP( g_trac_spd, INFO_MRK"Dimm was found to be present." ); } #if defined(CONFIG_DJVPD_READ_FROM_HW) && defined(CONFIG_DJVPD_READ_FROM_PNOR) if( present ) { // Check if the VPD data in the PNOR matches the SEEPROM err = VPD::ensureCacheIsInSync( i_target ); if( err ) { present = false; TRACFCOMP(g_trac_spd,ERR_MRK "dimmPresenceDetectt> Error during ensureCacheIsInSync (SPD)" ); break; } } else { // SPD is not present, invalidate the SPD in PNOR err = VPD::invalidatePnorCache(i_target); if (err) { TRACFCOMP( g_trac_spd, "Error invalidating SPD in PNOR" ); } } #endif if( present && !err ) { //Fsp sets PN/SN so if there is none, do it here if(!INITSERVICE::spBaseServicesEnabled()) { //populate serial and part number attributes SPD::setPartAndSerialNumberAttributes( i_target ); } // Read ATTR_CLEAR_DIMM_SPD_ENABLE attribute TARGETING::Target* l_sys = NULL; TARGETING::targetService().getTopLevelTarget(l_sys); TARGETING::ATTR_CLEAR_DIMM_SPD_ENABLE_type l_clearSPD = l_sys->getAttr<TARGETING::ATTR_CLEAR_DIMM_SPD_ENABLE>(); // If SPD clear is enabled then write 0's into magic word for // DIMM_BAD_DQ_DATA keyword // Note: If there's an error from performing the clearing, // just log the error and continue. if (l_clearSPD) { size_t l_size = 0; // Do a read to get the DIMM_BAD_DQ_DATA keyword size err = deviceRead(i_target, NULL, l_size, DEVICE_SPD_ADDRESS( DIMM_BAD_DQ_DATA )); if (err) { TRACFCOMP(g_trac_spd, "dimmPresenceDetect - " "Error reading DIMM_BAD_DQ_DATA keyword size"); errlCommit( err, VPD_COMP_ID ); } else { // Clear the data TRACFCOMP( g_trac_spd, "Clearing out BAD_DQ_DATA SPD on " "DIMM HUID 0x%X", TARGETING::get_huid(i_target)); uint8_t * l_data = static_cast<uint8_t*>(malloc( l_size )); memset(l_data, 0, l_size); err = deviceWrite(i_target, l_data, l_size, DEVICE_SPD_ADDRESS( DIMM_BAD_DQ_DATA )); if (err) { TRACFCOMP( g_trac_spd, "Error trying to clear SPD on " "DIMM HUID 0x%X", TARGETING::get_huid(i_target)); errlCommit( err, VPD_COMP_ID ); } // Free the memory if (NULL != l_data) { free(l_data); } } } } // copy present value into output buffer so caller can read it memcpy( io_buffer, &present, presentSz ); io_buflen = presentSz; } while( 0 ); TRACSSCOMP( g_trac_spd, EXIT_MRK"dimmPresenceDetect()" ); return err; } // end dimmPresenceDetect
errlHndl_t initiateDrtm() { SB_ENTER("initiateDrtm"); errlHndl_t pError = nullptr; // For DRTM, the thread has to be pinned to a core (and therefore pinned to // a chip) task_affinity_pin(); void* drtmPayloadVirtAddr = nullptr; do { const std::vector<SECUREBOOT::ProcSecurity> LLP { SECUREBOOT::ProcSecurity::LLPBit, }; const std::vector<SECUREBOOT::ProcSecurity> LLS { SECUREBOOT::ProcSecurity::LLSBit, }; // Determine which fabric group and chip this task is executing on and // create a filter to find the matching chip target auto cpuId = task_getcpuid(); auto groupId = PIR_t::groupFromPir(cpuId); auto chipId = PIR_t::chipFromPir(cpuId); TARGETING::PredicateAttrVal<TARGETING::ATTR_FABRIC_GROUP_ID> matchesGroup(groupId); TARGETING::PredicateAttrVal<TARGETING::ATTR_FABRIC_CHIP_ID> matchesChip(chipId); TARGETING::PredicatePostfixExpr matchesGroupAndChip; matchesGroupAndChip.push(&matchesGroup).push(&matchesChip).And(); // Get all the functional proc chips and find the chip we're running on TARGETING::TargetHandleList funcProcChips; TARGETING::getAllChips(funcProcChips, TARGETING::TYPE_PROC); if(funcProcChips.empty()) { // TODO: RTC 167205: GA error handling assert(false,"initiateDrtm: BUG! Functional proc chips is empty, " "yet this code is running on a functional chip!"); break; } // NOTE: std::find_if requires predicates to be copy constructable, but // predicates are not; hence use a wrapper lambda function to bypass // that limitation auto pMatch = std::find_if(funcProcChips.begin(),funcProcChips.end(), [&matchesGroupAndChip] ( TARGETING::Target* pTarget ) { return matchesGroupAndChip(pTarget); } ); if(pMatch == funcProcChips.end()) { // TODO: RTC 167205: GA error handling assert(false, "initiateDrtm: BUG! No functional chip found " "to be running this code"); break; } // Move the matching target to the end of the list. // NOTE: If reverse iterators were supported, we could have verified the // last element of the container is not the match, and done a // std::iter_swap of the match and the last element TARGETING::Target* const pMatchTarget = *pMatch; funcProcChips.erase(pMatch); funcProcChips.push_back(pMatchTarget); // Map to the DRTM payload area in mainstore const uint32_t drtmPayloadPhysAddrMb = DRTM_RIT_PAYLOAD_PHYS_ADDR_MB; drtmPayloadVirtAddr = mm_block_map( reinterpret_cast<void*>(drtmPayloadPhysAddrMb*BYTES_PER_MEGABYTE), PAGESIZE); if(drtmPayloadVirtAddr == nullptr) { // TODO: RTC 167205: GA error handling assert(false, "initiateDrtm: BUG! Failed in call to mm_block_map " "to map the DRTM payload."); break; } // Copy the DRTM payload to the DRTM payload area memcpy( reinterpret_cast<uint32_t*>(drtmPayloadVirtAddr), DRTM_RIT_PAYLOAD, sizeof(DRTM_RIT_PAYLOAD)); // The required generic sequencing to initiate DRTM is as follows: // 1) Initiating task must pin itself to a core (to ensure it // will not be accidentally queisced by SBE) // 2) It must set the DRTM payload information in the master processor // mailbox scratch registers (registers 7 and 8) before it goes // offline // 3) It must determine the processor it's currently running on // 4) It must set the late launch bit (LL) on all other processors // 4a) If the given processor is an active master, it must set // late launch primary (LLP) bit // 4b) Otherwise it must set late launch secondary (LLS) bit // 5) Finally, it must its own processor's LL bit last, according to the // rules of step 4. for(auto &pFuncProc :funcProcChips) { const auto procMasterType = pFuncProc->getAttr< TARGETING::ATTR_PROC_MASTER_TYPE>(); // If master chip, set the DRTM payload address and validity if(procMasterType == TARGETING::PROC_MASTER_TYPE_ACTING_MASTER) { (void)setDrtmPayloadPhysAddrMb(drtmPayloadPhysAddrMb); } pError = SECUREBOOT::setSecuritySwitchBits(procMasterType == TARGETING::PROC_MASTER_TYPE_ACTING_MASTER ? LLP : LLS, pFuncProc); if(pError) { SB_ERR("initiateDrtm: setSecuritySwitchBits() failed for proc " "= 0x%08X. Tried to set LLP or LLS.", get_huid(pFuncProc)); break; } } if(pError) { break; } SB_INF("initiateDrtm: SBE should eventually quiesce all cores; until " "then, endlessly yield the task"); while(1) { task_yield(); } } while(0); // If we -do- come back from this function (on error path only), then we // should unpin task_affinity_unpin(); if(drtmPayloadVirtAddr) { auto rc = mm_block_unmap(const_cast<void*>(drtmPayloadVirtAddr)); if(rc != 0) { // TODO: RTC 167205: GA error handling assert(false,"initiateDrtm: BUG! mm_block_unmap failed for virtual " "address 0x%16llX.", drtmPayloadVirtAddr); } } if(pError) { SB_ERR("initiateDrtm: plid=0x%08X, eid=0x%08X, reason=0x%04X", ERRL_GETPLID_SAFE(pError), ERRL_GETEID_SAFE(pError), ERRL_GETRC_SAFE(pError)); } SB_EXIT("initiateDrtm"); return pError; }