EFI_STATUS
InitializeExceptions (
IN EFI_CPU_ARCH_PROTOCOL *Cpu
)
{
EFI_STATUS Status;
BOOLEAN IrqEnabled;
BOOLEAN FiqEnabled;
Status = EFI_SUCCESS;
ZeroMem (gExceptionHandlers,sizeof(*gExceptionHandlers));
//
// Disable interrupts
//
Cpu->GetInterruptState (Cpu, &IrqEnabled);
Cpu->DisableInterrupt (Cpu);
//
// EFI does not use the FIQ, but a debugger might so we must disable
// as we take over the exception vectors.
//
FiqEnabled = ArmGetFiqState ();
ArmDisableFiq ();
// AArch64 alignment? The Vector table must be 2k-byte aligned (bottom 11 bits zero)?
//DEBUG ((EFI_D_ERROR, "vbar set addr: 0x%016lx\n",(UINTN)ExceptionHandlersStart));
//ASSERT(((UINTN)ExceptionHandlersStart & ((1 << 11)-1)) == 0);
// We do not copy the Exception Table at PcdGet32(PcdCpuVectorBaseAddress). We just set Vector Base Address to point into CpuDxe code.
ArmWriteVBar ((UINTN)ExceptionHandlersStart);
if (FiqEnabled) {
ArmEnableFiq ();
}
if (IrqEnabled) {
//
// Restore interrupt state
//
Status = Cpu->EnableInterrupt (Cpu);
}
return Status;
}
/**
Enable/Disable the interrupt of debug timer and return the interrupt state
prior to the operation.
If EnableStatus is TRUE, enable the interrupt of debug timer.
If EnableStatus is FALSE, disable the interrupt of debug timer.
@param[in] EnableStatus Enable/Disable.
@retval TRUE Debug timer interrupt were enabled on entry to this call.
@retval FALSE Debug timer interrupt were disabled on entry to this call.
**/
BOOLEAN
EFIAPI
SaveAndSetDebugTimerInterrupt (
IN BOOLEAN EnableStatus
)
{
BOOLEAN FiqEnabled;
FiqEnabled = ArmGetFiqState ();
if (EnableStatus) {
DebugAgentTimerSetPeriod (PcdGet32 (PcdGdbTimerPeriodMilliseconds));
ArmEnableFiq ();
} else {
DebugAgentTimerSetPeriod (0);
ArmDisableFiq ();
}
return FiqEnabled;
}
