uint32_t GPDMA_CalcRxControl(uint32_t transfer_size, uint32_t src_conn)
{
return GPDMA_DMACCxControl_TransferSize(transfer_size) \
| GPDMA_DMACCxControl_SBSize((uint32_t)GPDMA_LUTPerBurst[src_conn]) \
| GPDMA_DMACCxControl_DBSize((uint32_t)GPDMA_LUTPerBurst[src_conn]) \
| GPDMA_DMACCxControl_SWidth((uint32_t)GPDMA_LUTPerWid[src_conn]) \
| GPDMA_DMACCxControl_DWidth((uint32_t)GPDMA_LUTPerWid[src_conn]) \
| GPDMA_DMACCxControl_DI \
| GPDMA_DMACCxControl_I;
}
/********************************************************************//**
* @brief Setup GPDMA channel peripheral according to the specified
* parameters in the GPDMAChannelConfig.
* @param[in] GPDMAChannelConfig Pointer to a GPDMA_CH_CFG_Type
* structure that contains the configuration
* information for the specified GPDMA channel peripheral.
* @return ERROR if selected channel is enabled before
* or SUCCESS if channel is configured successfully
*********************************************************************/
Status GPDMA_Setup(GPDMA_Channel_CFG_Type *GPDMAChannelConfig)
{
LPC_GPDMACH_TypeDef *pDMAch;
uint32_t tmp1, tmp2;
if (LPC_GPDMA->DMACEnbldChns & (GPDMA_DMACEnbldChns_Ch(GPDMAChannelConfig->ChannelNum))) {
// This channel is enabled, return ERROR, need to release this channel first
return ERROR;
}
// Get Channel pointer
pDMAch = (LPC_GPDMACH_TypeDef *) pGPDMACh[GPDMAChannelConfig->ChannelNum];
// Reset the Interrupt status
LPC_GPDMA->DMACIntTCClear = GPDMA_DMACIntTCClear_Ch(GPDMAChannelConfig->ChannelNum);
LPC_GPDMA->DMACIntErrClr = GPDMA_DMACIntErrClr_Ch(GPDMAChannelConfig->ChannelNum);
// Clear DMA configure
pDMAch->DMACCControl = 0x00;
pDMAch->DMACCConfig = 0x00;
/* Assign Linker List Item value */
pDMAch->DMACCLLI = GPDMAChannelConfig->DMALLI;
/* Set value to Channel Control Registers */
switch (GPDMAChannelConfig->TransferType)
{
// Memory to memory
case GPDMA_TRANSFERTYPE_M2M:
// Assign physical source and destination address
pDMAch->DMACCSrcAddr = GPDMAChannelConfig->SrcMemAddr;
pDMAch->DMACCDestAddr = GPDMAChannelConfig->DstMemAddr;
pDMAch->DMACCControl
= GPDMA_DMACCxControl_TransferSize(GPDMAChannelConfig->TransferSize) \
| GPDMA_DMACCxControl_SBSize(GPDMA_BSIZE_32) \
| GPDMA_DMACCxControl_DBSize(GPDMA_BSIZE_32) \
| GPDMA_DMACCxControl_SWidth(GPDMAChannelConfig->TransferWidth) \
| GPDMA_DMACCxControl_DWidth(GPDMAChannelConfig->TransferWidth) \
| GPDMA_DMACCxControl_SI \
| GPDMA_DMACCxControl_DI \
| GPDMA_DMACCxControl_I;
break;
// Memory to peripheral
case GPDMA_TRANSFERTYPE_M2P:
// Assign physical source
pDMAch->DMACCSrcAddr = GPDMAChannelConfig->SrcMemAddr;
// Assign peripheral destination address
pDMAch->DMACCDestAddr = (uint32_t)GPDMA_LUTPerAddr[GPDMAChannelConfig->DstConn];
pDMAch->DMACCControl
= GPDMA_DMACCxControl_TransferSize((uint32_t)GPDMAChannelConfig->TransferSize) \
| GPDMA_DMACCxControl_SBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->DstConn]) \
| GPDMA_DMACCxControl_DBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->DstConn]) \
| GPDMA_DMACCxControl_SWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->DstConn]) \
| GPDMA_DMACCxControl_DWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->DstConn]) \
| GPDMA_DMACCxControl_SI \
| GPDMA_DMACCxControl_I;
break;
// Peripheral to memory
case GPDMA_TRANSFERTYPE_P2M:
// Assign peripheral source address
pDMAch->DMACCSrcAddr = (uint32_t)GPDMA_LUTPerAddr[GPDMAChannelConfig->SrcConn];
// Assign memory destination address
pDMAch->DMACCDestAddr = GPDMAChannelConfig->DstMemAddr;
pDMAch->DMACCControl
= GPDMA_DMACCxControl_TransferSize((uint32_t)GPDMAChannelConfig->TransferSize) \
| GPDMA_DMACCxControl_SBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->SrcConn]) \
| GPDMA_DMACCxControl_DBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->SrcConn]) \
| GPDMA_DMACCxControl_SWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->SrcConn]) \
| GPDMA_DMACCxControl_DWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->SrcConn]) \
| GPDMA_DMACCxControl_DI \
| GPDMA_DMACCxControl_I;
break;
// Peripheral to peripheral
case GPDMA_TRANSFERTYPE_P2P:
// Assign peripheral source address
pDMAch->DMACCSrcAddr = (uint32_t)GPDMA_LUTPerAddr[GPDMAChannelConfig->SrcConn];
// Assign peripheral destination address
pDMAch->DMACCDestAddr = (uint32_t)GPDMA_LUTPerAddr[GPDMAChannelConfig->DstConn];
pDMAch->DMACCControl
= GPDMA_DMACCxControl_TransferSize((uint32_t)GPDMAChannelConfig->TransferSize) \
| GPDMA_DMACCxControl_SBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->SrcConn]) \
| GPDMA_DMACCxControl_DBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->DstConn]) \
| GPDMA_DMACCxControl_SWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->SrcConn]) \
| GPDMA_DMACCxControl_DWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->DstConn]) \
| GPDMA_DMACCxControl_I;
break;
// Do not support any more transfer type, return ERROR
default:
return ERROR;
}
/* Re-Configure DMA Request Select for source peripheral */
if (GPDMAChannelConfig->SrcConn > 15)
{
DMAREQSEL |= (1<<(GPDMAChannelConfig->SrcConn - 16));
} else {
DMAREQSEL &= ~(1<<(GPDMAChannelConfig->SrcConn - 8));
}
/* Re-Configure DMA Request Select for Destination peripheral */
if (GPDMAChannelConfig->DstConn > 15)
{
DMAREQSEL |= (1<<(GPDMAChannelConfig->DstConn - 16));
} else {
DMAREQSEL &= ~(1<<(GPDMAChannelConfig->DstConn - 8));
}
/* Enable DMA channels, little endian */
LPC_GPDMA->DMACConfig = GPDMA_DMACConfig_E;
while (!(LPC_GPDMA->DMACConfig & GPDMA_DMACConfig_E));
// Calculate absolute value for Connection number
tmp1 = GPDMAChannelConfig->SrcConn;
tmp1 = ((tmp1 > 15) ? (tmp1 - 8) : tmp1);
tmp2 = GPDMAChannelConfig->DstConn;
tmp2 = ((tmp2 > 15) ? (tmp2 - 8) : tmp2);
// Configure DMA Channel, enable Error Counter and Terminate counter
pDMAch->DMACCConfig = GPDMA_DMACCxConfig_IE | GPDMA_DMACCxConfig_ITC /*| GPDMA_DMACCxConfig_E*/ \
| GPDMA_DMACCxConfig_TransferType((uint32_t)GPDMAChannelConfig->TransferType) \
| GPDMA_DMACCxConfig_SrcPeripheral(tmp1) \
| GPDMA_DMACCxConfig_DestPeripheral(tmp2);
return SUCCESS;
}
/********************************************************************//**
* @brief Setup GPDMA channel peripheral according to the specified
* parameters in the GPDMAChannelConfig.
* @param[in] GPDMAChannelConfig Pointer to a GPDMA_CH_CFG_Type structure
* that contains the configuration information for the specified
* GPDMA channel peripheral.
* @return Setup status, could be:
* - ERROR :if selected channel is enabled before
* - SUCCESS :if channel is configured successfully
*********************************************************************/
Status GPDMA_Setup(GPDMA_Channel_CFG_Type *GPDMAChannelConfig)
{
LPC_GPDMACH_TypeDef *pDMAch;
uint8_t SrcPeripheral=0, DestPeripheral=0;
if (LPC_GPDMA->ENBLDCHNS & (GPDMA_DMACEnbldChns_Ch(GPDMAChannelConfig->ChannelNum))) {
// This channel is enabled, return ERROR, need to release this channel first
return ERROR;
}
// Get Channel pointer
pDMAch = (LPC_GPDMACH_TypeDef *) pGPDMACh[GPDMAChannelConfig->ChannelNum];
// Reset the Interrupt status
LPC_GPDMA->INTTCCLEAR = GPDMA_DMACIntTCClear_Ch(GPDMAChannelConfig->ChannelNum);
LPC_GPDMA->INTERRCLR = GPDMA_DMACIntErrClr_Ch(GPDMAChannelConfig->ChannelNum);
// Clear DMA configure
pDMAch->CControl = 0x00;
pDMAch->CConfig = 0x00;
/* Assign Linker List Item value */
pDMAch->CLLI = GPDMAChannelConfig->DMALLI;
/* Set value to Channel Control Registers */
switch (GPDMAChannelConfig->TransferType)
{
// Memory to memory
case GPDMA_TRANSFERTYPE_M2M_CONTROLLER_DMA:
// Assign physical source and destination address
pDMAch->CSrcAddr = GPDMAChannelConfig->SrcMemAddr;
pDMAch->CDestAddr = GPDMAChannelConfig->DstMemAddr;
pDMAch->CControl
= GPDMA_DMACCxControl_TransferSize(GPDMAChannelConfig->TransferSize) \
| GPDMA_DMACCxControl_SBSize(GPDMA_BSIZE_32) \
| GPDMA_DMACCxControl_DBSize(GPDMA_BSIZE_32) \
| GPDMA_DMACCxControl_SWidth(GPDMAChannelConfig->TransferWidth) \
| GPDMA_DMACCxControl_DWidth(GPDMAChannelConfig->TransferWidth) \
| GPDMA_DMACCxControl_SI \
| GPDMA_DMACCxControl_DI \
| GPDMA_DMACCxControl_I;
break;
// Memory to peripheral
case GPDMA_TRANSFERTYPE_M2P_CONTROLLER_DMA:
// Assign physical source
pDMAch->CSrcAddr = GPDMAChannelConfig->SrcMemAddr;
// Assign peripheral destination address
pDMAch->CDestAddr = (uint32_t)GPDMA_LUTPerAddr[GPDMAChannelConfig->DstConn];
pDMAch->CControl
= GPDMA_DMACCxControl_TransferSize((uint32_t)GPDMAChannelConfig->TransferSize) \
| GPDMA_DMACCxControl_SBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->DstConn]) \
| GPDMA_DMACCxControl_DBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->DstConn]) \
| GPDMA_DMACCxControl_SWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->DstConn]) \
| GPDMA_DMACCxControl_DWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->DstConn]) \
| GPDMA_DMACCxControl_DestTransUseAHBMaster1 \
| GPDMA_DMACCxControl_SI \
| GPDMA_DMACCxControl_I;
DestPeripheral = DMAMUX_Config(GPDMAChannelConfig->DstConn);
break;
// Peripheral to memory
case GPDMA_TRANSFERTYPE_P2M_CONTROLLER_DMA:
// Assign peripheral source address
pDMAch->CSrcAddr = (uint32_t)GPDMA_LUTPerAddr[GPDMAChannelConfig->SrcConn];
// Assign memory destination address
pDMAch->CDestAddr = GPDMAChannelConfig->DstMemAddr;
pDMAch->CControl
= GPDMA_DMACCxControl_TransferSize((uint32_t)GPDMAChannelConfig->TransferSize) \
| GPDMA_DMACCxControl_SBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->SrcConn]) \
| GPDMA_DMACCxControl_DBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->SrcConn]) \
| GPDMA_DMACCxControl_SWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->SrcConn]) \
| GPDMA_DMACCxControl_DWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->SrcConn]) \
| GPDMA_DMACCxControl_SrcTransUseAHBMaster1 \
| GPDMA_DMACCxControl_DI \
| GPDMA_DMACCxControl_I;
SrcPeripheral = DMAMUX_Config(GPDMAChannelConfig->SrcConn);
break;
// Peripheral to peripheral
case GPDMA_TRANSFERTYPE_P2P_CONTROLLER_DMA:
// Assign peripheral source address
pDMAch->CSrcAddr = (uint32_t)GPDMA_LUTPerAddr[GPDMAChannelConfig->SrcConn];
// Assign peripheral destination address
pDMAch->CDestAddr = (uint32_t)GPDMA_LUTPerAddr[GPDMAChannelConfig->DstConn];
pDMAch->CControl
= GPDMA_DMACCxControl_TransferSize((uint32_t)GPDMAChannelConfig->TransferSize) \
| GPDMA_DMACCxControl_SBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->SrcConn]) \
| GPDMA_DMACCxControl_DBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->DstConn]) \
| GPDMA_DMACCxControl_SWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->SrcConn]) \
| GPDMA_DMACCxControl_DWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->DstConn]) \
| GPDMA_DMACCxControl_SrcTransUseAHBMaster1 \
| GPDMA_DMACCxControl_DestTransUseAHBMaster1 \
| GPDMA_DMACCxControl_I;
SrcPeripheral = DMAMUX_Config(GPDMAChannelConfig->SrcConn);
DestPeripheral = DMAMUX_Config(GPDMAChannelConfig->DstConn);
break;
case GPDMA_TRANSFERTYPE_P2P_CONTROLLER_DestPERIPHERAL:
case GPDMA_TRANSFERTYPE_M2P_CONTROLLER_PERIPHERAL:
case GPDMA_TRANSFERTYPE_P2M_CONTROLLER_PERIPHERAL:
case GPDMA_TRANSFERTYPE_P2P_CONTROLLER_SrcPERIPHERAL:
//to be defined
// Do not support any more transfer type, return ERROR
default:
return ERROR;
}
/* Enable DMA channels, little endian */
LPC_GPDMA->CONFIG = GPDMA_DMACConfig_E;
while (!(LPC_GPDMA->CONFIG & GPDMA_DMACConfig_E));
// Configure DMA Channel, enable Error Counter and Terminate counter
pDMAch->CConfig = GPDMA_DMACCxConfig_IE | GPDMA_DMACCxConfig_ITC /*| GPDMA_DMACCxConfig_E*/ \
| GPDMA_DMACCxConfig_TransferType((uint32_t)GPDMAChannelConfig->TransferType) \
| GPDMA_DMACCxConfig_SrcPeripheral(SrcPeripheral) \
| GPDMA_DMACCxConfig_DestPeripheral(DestPeripheral);
return SUCCESS;
}
uint32_t IP_GPDMA_MakeCtrlWord(const GPDMA_Channel_CFG_Type *GPDMAChannelConfig,
uint32_t GPDMA_LUTPerBurstSrcConn,
uint32_t GPDMA_LUTPerBurstDstConn,
uint32_t GPDMA_LUTPerWidSrcConn,
uint32_t GPDMA_LUTPerWidDstConn)
{
uint32_t ctrl_word = 0;
switch (GPDMAChannelConfig->TransferType) {
/* Memory to memory */
case GPDMA_TRANSFERTYPE_M2M_CONTROLLER_DMA:
ctrl_word = GPDMA_DMACCxControl_TransferSize(GPDMAChannelConfig->TransferSize)
| GPDMA_DMACCxControl_SBSize((4UL)) /**< Burst size = 32 */
| GPDMA_DMACCxControl_DBSize((4UL)) /**< Burst size = 32 */
| GPDMA_DMACCxControl_SWidth(GPDMAChannelConfig->TransferWidth)
| GPDMA_DMACCxControl_DWidth(GPDMAChannelConfig->TransferWidth)
| GPDMA_DMACCxControl_SI
| GPDMA_DMACCxControl_DI
| GPDMA_DMACCxControl_I;
break;
case GPDMA_TRANSFERTYPE_M2P_CONTROLLER_DMA:
case GPDMA_TRANSFERTYPE_M2P_CONTROLLER_PERIPHERAL:
ctrl_word = GPDMA_DMACCxControl_TransferSize((uint32_t) GPDMAChannelConfig->TransferSize)
| GPDMA_DMACCxControl_SBSize(GPDMA_LUTPerBurstDstConn)
| GPDMA_DMACCxControl_DBSize(GPDMA_LUTPerBurstDstConn)
| GPDMA_DMACCxControl_SWidth(GPDMA_LUTPerWidDstConn)
| GPDMA_DMACCxControl_DWidth(GPDMA_LUTPerWidDstConn)
| GPDMA_DMACCxControl_DestTransUseAHBMaster1
| GPDMA_DMACCxControl_SI
| GPDMA_DMACCxControl_I;
break;
case GPDMA_TRANSFERTYPE_P2M_CONTROLLER_DMA:
case GPDMA_TRANSFERTYPE_P2M_CONTROLLER_PERIPHERAL:
ctrl_word = GPDMA_DMACCxControl_TransferSize((uint32_t) GPDMAChannelConfig->TransferSize)
| GPDMA_DMACCxControl_SBSize(GPDMA_LUTPerBurstSrcConn)
| GPDMA_DMACCxControl_DBSize(GPDMA_LUTPerBurstSrcConn)
| GPDMA_DMACCxControl_SWidth(GPDMA_LUTPerWidSrcConn)
| GPDMA_DMACCxControl_DWidth(GPDMA_LUTPerWidSrcConn)
| GPDMA_DMACCxControl_SrcTransUseAHBMaster1
| GPDMA_DMACCxControl_DI
| GPDMA_DMACCxControl_I;
break;
case GPDMA_TRANSFERTYPE_P2P_CONTROLLER_DMA:
case GPDMA_TRANSFERTYPE_P2P_CONTROLLER_DestPERIPHERAL:
case GPDMA_TRANSFERTYPE_P2P_CONTROLLER_SrcPERIPHERAL:
ctrl_word = GPDMA_DMACCxControl_TransferSize((uint32_t) GPDMAChannelConfig->TransferSize)
| GPDMA_DMACCxControl_SBSize(GPDMA_LUTPerBurstSrcConn)
| GPDMA_DMACCxControl_DBSize(GPDMA_LUTPerBurstDstConn)
| GPDMA_DMACCxControl_SWidth(GPDMA_LUTPerWidSrcConn)
| GPDMA_DMACCxControl_DWidth(GPDMA_LUTPerWidDstConn)
| GPDMA_DMACCxControl_SrcTransUseAHBMaster1
| GPDMA_DMACCxControl_DestTransUseAHBMaster1
| GPDMA_DMACCxControl_I;
break;
/* Do not support any more transfer type, return ERROR */
default:
return ERROR;
}
return ctrl_word;
}
void dma_setup(char ChannelNum, unsigned int SrcMemAddr,unsigned int DstMemAddr, unsigned int SrcPeriph, unsigned int DstPeriph, unsigned int TransferSize, unsigned int BurstSize, unsigned int TransferWidth, unsigned int TransferType, unsigned int Dmalli ){
LPC_GPDMACH_TypeDef *pDMAch;
// Get Channel pointer
pDMAch = ((LPC_GPDMACH_TypeDef *) (LPC_GPDMACH0_BASE + 0x20 * (ChannelNum)));
// Reset the Interrupt status
LPC_GPDMA->IntTCClear = GPDMA_DMACIntTCClear_Ch(ChannelNum);
LPC_GPDMA->IntErrClr = GPDMA_DMACIntErrClr_Ch(ChannelNum);
// Clear DMA configure
pDMAch->CControl = 0x00;
pDMAch->CConfig = 0x00;
/* Assign Linker List Item value */
pDMAch->CLLI = Dmalli;
switch (TransferType)
{
// Memory to memory
case GPDMA_TRANSFERTYPE_M2M:
// Assign physical source and destination address
pDMAch->CSrcAddr = SrcMemAddr;
pDMAch->CDestAddr = DstMemAddr;
pDMAch->CControl =
GPDMA_DMACCxControl_TransferSize(TransferSize) \
| GPDMA_DMACCxControl_SBSize(BurstSize) \
| GPDMA_DMACCxControl_DBSize(BurstSize) \
| GPDMA_DMACCxControl_SWidth(TransferWidth) \
| GPDMA_DMACCxControl_DWidth(TransferWidth) \
| GPDMA_DMACCxControl_SI \
| GPDMA_DMACCxControl_DI \
| GPDMA_DMACCxControl_I;
break;
// Memory to peripheral
case GPDMA_TRANSFERTYPE_M2P:
case GPDMA_TRANSFERTYPE_M2P_DEST_CTRL:
// Assign physical source
pDMAch->CSrcAddr = SrcMemAddr;
// Assign peripheral destination address
pDMAch->CDestAddr = (uint32_t)DMA_LUTPerAddr[DstPeriph];
pDMAch->CControl =
GPDMA_DMACCxControl_TransferSize((uint32_t)TransferSize) \
| GPDMA_DMACCxControl_SBSize((uint32_t)BurstSize) \
| GPDMA_DMACCxControl_DBSize((uint32_t)BurstSize) \
| GPDMA_DMACCxControl_SWidth((uint32_t)TransferWidth) \
| GPDMA_DMACCxControl_DWidth((uint32_t)TransferWidth) \
| GPDMA_DMACCxControl_SI \
| GPDMA_DMACCxControl_I;
break;
// Peripheral to memory
case GPDMA_TRANSFERTYPE_P2M:
case GPDMA_TRANSFERTYPE_P2M_SRC_CTRL:
// Assign peripheral source address
pDMAch->CSrcAddr = (uint32_t)DMA_LUTPerAddr[SrcPeriph];
// Assign memory destination address
pDMAch->CDestAddr = DstMemAddr;
pDMAch->CControl =
GPDMA_DMACCxControl_TransferSize((uint32_t)TransferSize) \
| GPDMA_DMACCxControl_SBSize((uint32_t)BurstSize) \
| GPDMA_DMACCxControl_DBSize((uint32_t)BurstSize) \
| GPDMA_DMACCxControl_SWidth((uint32_t)TransferWidth) \
| GPDMA_DMACCxControl_DWidth((uint32_t)TransferWidth) \
| GPDMA_DMACCxControl_DI \
| GPDMA_DMACCxControl_I;
break;
// Peripheral to peripheral
case GPDMA_TRANSFERTYPE_P2P:
// Assign peripheral source address
pDMAch->CSrcAddr = (uint32_t)DMA_LUTPerAddr[SrcPeriph];
// Assign peripheral destination address
pDMAch->CDestAddr = (uint32_t)DMA_LUTPerAddr[DstPeriph];
pDMAch->CControl = GPDMA_DMACCxControl_TransferSize((uint32_t)TransferSize) \
| GPDMA_DMACCxControl_SBSize((uint32_t)BurstSize) \
| GPDMA_DMACCxControl_DBSize((uint32_t)BurstSize) \
| GPDMA_DMACCxControl_SWidth((uint32_t)TransferWidth) \
| GPDMA_DMACCxControl_DWidth((uint32_t)TransferWidth) \
| GPDMA_DMACCxControl_I;
break;
}
//Configure DAM Request Select register
if((SrcPeriph != 8)&&(SrcPeriph != 9))
{
if (SrcPeriph > 15)
{
LPC_SC->DMAREQSEL |= (1<< (SrcPeriph - 16));
} else {
LPC_SC->DMAREQSEL &= ~(1<<(SrcPeriph));
}
}
if((DstPeriph != 8)&&(DstPeriph != 9))
{
if (DstPeriph > 15)
{
LPC_SC->DMAREQSEL |= (1<< (DstPeriph - 16));
} else {
LPC_SC->DMAREQSEL &= ~(1<<(DstPeriph));
}
}
/* Enable DMA channels, little endian */
LPC_GPDMA->Config = (0x01);
while (!(LPC_GPDMA->Config & 0x01));
// Calculate DMA connection
if (SrcPeriph > 15) {SrcPeriph = SrcPeriph -16;}
if (DstPeriph > 15) {DstPeriph = DstPeriph -16;}
//Configure GPDMA Config register
pDMAch->CConfig = GPDMA_DMACCxConfig_ITC
| GPDMA_DMACCxConfig_TransferType((uint32_t)TransferType) \
| GPDMA_DMACCxConfig_SrcPeripheral(SrcPeriph) \
| GPDMA_DMACCxConfig_DestPeripheral(DstPeriph);
}
void LED_init(){
GPIO_SetDir(LED_OE_PORT, LED_OE_BIT, 1);
GPIO_SetValue(LED_OE_PORT, LED_OE_BIT);//turn off leds active low
LatchIn();//reset
GPIO_SetDir(LED_LE_PORT, LED_LE_BIT, 1);
GPIO_ClearValue(LED_LE_PORT, LED_LE_BIT);
//reset all arrays
for (uint8_t tmp=0;tmp<no_SEQ_BITS;tmp++){
SEQ_BIT[tmp] = BITORDER[tmp];
SEQ_TIME[tmp] = BITTIME[BITORDER[tmp]];
}
resetLeds();
calulateLEDMIBAMBits();
// Initialize SPI pin connect
PINSEL_CFG_Type PinCfg;
/* LE1 */
PinCfg.Funcnum = PINSEL_FUNC_0;
PinCfg.OpenDrain = PINSEL_PINMODE_NORMAL;
PinCfg.Pinmode = PINSEL_PINMODE_PULLDOWN;
PinCfg.Pinnum = LED_LE_PIN;
PinCfg.Portnum = LED_LE_PORT;
PINSEL_ConfigPin(&PinCfg);
/* SSEL1 */
PinCfg.Funcnum = PINSEL_FUNC_0;
PinCfg.OpenDrain = PINSEL_PINMODE_NORMAL;
PinCfg.Pinmode = PINSEL_PINMODE_PULLDOWN;
PinCfg.Pinnum = LED_OE_PIN;
PinCfg.Portnum = LED_OE_PORT;
PINSEL_ConfigPin(&PinCfg);
/* SCK1 */
PinCfg.Funcnum = PINSEL_FUNC_2;
PinCfg.OpenDrain = PINSEL_PINMODE_NORMAL;
PinCfg.Pinmode = PINSEL_PINMODE_PULLUP;
PinCfg.Pinnum = LED_SCK_PIN;
PinCfg.Portnum = LED_SCK_PORT;
PINSEL_ConfigPin(&PinCfg);
/* MISO1 */
PinCfg.Funcnum = PINSEL_FUNC_2;
PinCfg.OpenDrain = PINSEL_PINMODE_NORMAL;
PinCfg.Pinmode = PINSEL_PINMODE_PULLUP;
PinCfg.Pinnum = LED_MISO_PIN;
PinCfg.Portnum = LED_MISO_PORT;
PINSEL_ConfigPin(&PinCfg);
PinCfg.Funcnum = PINSEL_FUNC_2;
/* MOSI1 */
PinCfg.Funcnum = PINSEL_FUNC_2;
PinCfg.OpenDrain = PINSEL_PINMODE_NORMAL;
PinCfg.Pinmode = PINSEL_PINMODE_PULLUP;
PinCfg.Pinnum = LED_MOSI_PIN;
PinCfg.Portnum = LED_MOSI_PORT;
PINSEL_ConfigPin(&PinCfg);
/* initialize SSP configuration structure */
SSP_CFG_Type SSP_ConfigStruct;
SSP_ConfigStruct.CPHA = SSP_CPHA_SECOND;
SSP_ConfigStruct.CPOL = SSP_CPOL_LO;
SSP_ConfigStruct.ClockRate = SSP_SPEED; // TLC5927 max freq = 30Mhz
SSP_ConfigStruct.FrameFormat = SSP_FRAME_SPI;
SSP_ConfigStruct.Databit = SSP_DATABIT_16;
SSP_ConfigStruct.Mode = SSP_MASTER_MODE;
SSP_Init(LED_SPI_CHN, &SSP_ConfigStruct);
SSP_Cmd(LED_SPI_CHN, ENABLE); // Enable SSP peripheral
// Setup LED interupt
// xprintf(INFO "LED TIM0_ConfigMatch");FFL_();
TIM_TIMERCFG_Type TIM0_ConfigStruct;
TIM_MATCHCFG_Type TIM0_MatchConfigStruct;
TIM0_ConfigStruct.PrescaleOption = TIM_PRESCALE_USVAL; // Initialize timer 0, prescale count time of 1us //1000000uS = 1S
TIM0_ConfigStruct.PrescaleValue = 1;
TIM0_MatchConfigStruct.MatchChannel = 0; // use channel 0, MR0
TIM0_MatchConfigStruct.IntOnMatch = TRUE; // Enable interrupt when MR0 matches the value in TC register
TIM0_MatchConfigStruct.ResetOnMatch = TRUE; //Enable reset on MR0: TIMER will reset if MR0 matches it
TIM0_MatchConfigStruct.StopOnMatch = FALSE; //Stop on MR0 if MR0 matches it
TIM0_MatchConfigStruct.ExtMatchOutputType = TIM_EXTMATCH_NOTHING;
TIM0_MatchConfigStruct.MatchValue = BITTIME[0]; // Set Match value, count value of 1000000 (1000000 * 1uS = 1000000us = 1s --> 1 Hz)
TIM_Init(LPC_TIM0, TIM_TIMER_MODE,&TIM0_ConfigStruct); // Set configuration for Tim_config and Tim_MatchConfig
TIM_ConfigMatch(LPC_TIM0,&TIM0_MatchConfigStruct);
NVIC_SetPriority(TIMER0_IRQn, 0);
NVIC_EnableIRQ(TIMER0_IRQn);
// xprintf(OK "LED TIM0_ConfigMatch");FFL_();
// Setup LED Latch interupt
// xprintf(INFO "LED TIM1_ConfigMatch");FFL_();
TIM_TIMERCFG_Type TIM1_ConfigStruct;
TIM_MATCHCFG_Type TIM1_MatchConfigStruct;
TIM1_ConfigStruct.PrescaleOption = TIM_PRESCALE_TICKVAL; // Initialize timer 0, prescale count time of 1us //1000000uS = 1S
TIM1_ConfigStruct.PrescaleValue = 1;
TIM1_MatchConfigStruct.MatchChannel = 0; // use channel 0, MR0
TIM1_MatchConfigStruct.IntOnMatch = TRUE; // Enable interrupt when MR0 matches the value in TC register
TIM1_MatchConfigStruct.ResetOnMatch = TRUE; //Enable reset on MR0: TIMER will reset if MR0 matches it
TIM1_MatchConfigStruct.StopOnMatch = TRUE; //Stop on MR0 if MR0 matches it
TIM1_MatchConfigStruct.ExtMatchOutputType = TIM_EXTMATCH_NOTHING;
TIM1_MatchConfigStruct.MatchValue = LED_Latch_interupt_delay; // Set Match value, count value of 1000000 (1000000 * 1uS = 1000000us = 1s --> 1 Hz)
TIM_Init(LPC_TIM1, TIM_TIMER_MODE,&TIM1_ConfigStruct); // Set configuration for Tim_config and Tim_MatchConfig
TIM_ConfigMatch(LPC_TIM1,&TIM1_MatchConfigStruct);
NVIC_SetPriority(TIMER1_IRQn, 0);
NVIC_EnableIRQ(TIMER1_IRQn);
// xprintf(OK "LED TIM1_ConfigMatch");FFL_();
// Speed timer
// xprintf(INFO "LED TIM2_ConfigMatch");FFL_();
TIM_TIMERCFG_Type TIM2_ConfigStruct;
TIM_MATCHCFG_Type TIM2_MatchConfigStruct;
TIM2_ConfigStruct.PrescaleOption = TIM_PRESCALE_USVAL; // Initialize timer 0, prescale count time of 1us //1000000uS = 1S
TIM2_ConfigStruct.PrescaleValue = 1000;
TIM2_MatchConfigStruct.MatchChannel = 0; // use channel 0, MR0
TIM2_MatchConfigStruct.IntOnMatch = TRUE; // Enable interrupt when MR0 matches the value in TC register
TIM2_MatchConfigStruct.ResetOnMatch = TRUE; //Enable reset on MR0: TIMER will reset if MR0 matches it
TIM2_MatchConfigStruct.StopOnMatch = FALSE; //Stop on MR0 if MR0 matches it
TIM2_MatchConfigStruct.ExtMatchOutputType = TIM_EXTMATCH_NOTHING;
TIM2_MatchConfigStruct.MatchValue = 256; // Set Match value, count value of 1000000 (1000000 * 1uS = 1000000us = 1s --> 1 Hz)
TIM_Init(LPC_TIM2, TIM_TIMER_MODE,&TIM2_ConfigStruct); // Set configuration for Tim_config and Tim_MatchConfig
TIM_ConfigMatch(LPC_TIM2,&TIM2_MatchConfigStruct);
NVIC_SetPriority(TIMER2_IRQn, 0);
NVIC_EnableIRQ(TIMER2_IRQn);
// xprintf(OK "LED TIM2_ConfigMatch");FFL_();
#ifdef DMA
// GPDMA_Channel_CFG_Type GPDMACfg;
NVIC_SetPriority(DMA_IRQn, 0); // set according to main.c
NVIC_EnableIRQ(DMA_IRQn);
GPDMA_Init(); // Initialize GPDMA controller */
NVIC_DisableIRQ (DMA_IRQn); // Disable interrupt for DMA
NVIC_SetPriority(DMA_IRQn, 0); // set according to main.c
GPDMACfg.ChannelNum = 0; // DMA Channel 0
GPDMACfg.SrcMemAddr = 0; // Source memory - not used - will be sent in interrupt so independent bit Linker Lists can be chosen
GPDMACfg.DstMemAddr = 0; // Destination memory - not used - only used when destination is memory
GPDMACfg.TransferSize = 1; // Transfer size
GPDMACfg.TransferWidth = GPDMA_WIDTH_HALFWORD; // Transfer width - not used
GPDMACfg.TransferType = GPDMA_TRANSFERTYPE_M2P; // Transfer type
GPDMACfg.SrcConn = 0; // Source connection - not used
GPDMACfg.DstConn = GPDMA_CONN_SSP0_Tx; // Destination connection - not used
GPDMACfg.DMALLI = (uint32_t) &LinkerList[0][0][0]; // Linker List Item - Pointer to linker list
GPDMA_Setup(&GPDMACfg); // Setup channel with given parameter
// Linker list 32bit Control
uint32_t LinkerListControl = 0;
LinkerListControl = GPDMA_DMACCxControl_TransferSize((uint32_t)GPDMACfg.TransferSize) \
| GPDMA_DMACCxControl_SBSize((uint32_t)GPDMA_BSIZE_1) \
| GPDMA_DMACCxControl_DBSize((uint32_t)GPDMA_BSIZE_1) \
| GPDMA_DMACCxControl_SWidth((uint32_t)GPDMACfg.TransferWidth) \
| GPDMA_DMACCxControl_DWidth((uint32_t)GPDMACfg.TransferWidth) \
| GPDMA_DMACCxControl_SI;
uint8_t reg, bit, linkerListNo, buf;
for (buf=0;buf<BUFFERS;buf++){
for (bit=0;bit<BITS;bit++){
linkerListNo=0;
for (reg=5; 0<reg;reg--,linkerListNo++){
// xprintf("bit:%d reg:%d SrcAddr:0x%x DstAddr:0x%x NextLLI:0x%x linkerListNo:0x%x\n",bit,reg,(uint32_t) &LED_PRECALC[reg][bit][buf],(uint32_t) &LPC_SSP0->DR,(uint32_t) &LinkerList[linkerListNo+1][bit][buf],linkerListNo);
LinkerList[linkerListNo][bit][buf].SrcAddr = (uint32_t) &LED_PRECALC[reg][bit][buf]; /**< Source Address */
LinkerList[linkerListNo][bit][buf].DstAddr = (uint32_t) &LPC_SSP0->DR; /**< Destination address */
LinkerList[linkerListNo][bit][buf].NextLLI = (uint32_t) &LinkerList[linkerListNo+1][bit][buf]; /**< Next LLI address, otherwise set to '0' */
LinkerList[linkerListNo][bit][buf].Control = LinkerListControl;
// xprintf("SrcAddr:0x%x DstAddr:0x%x NextLLI:0x%x\n",(uint32_t) &LinkerList[linkerListNo][bit][buf].SrcAddr,(uint32_t) &LinkerList[linkerListNo][bit][buf].DstAddr,(uint32_t) &LinkerList[linkerListNo][bit][buf].NextLLI,(uint32_t) &LinkerList[linkerListNo][bit][buf].Control);
}
// if (reg==0){
// xprintf("bit:%d reg:%d SrcAddr:0x%x DstAddr:0x%x NextLLI:0x%x linkerListNo:0x%x\n",bit,reg,(uint32_t) &LED_PRECALC[reg][bit][buf],(uint32_t) &LPC_SSP0->DR,(uint32_t) &LinkerList[linkerListNo+1][bit][buf],linkerListNo);
LinkerList[linkerListNo][bit][buf].SrcAddr = (uint32_t) &LED_PRECALC[reg][bit][buf]; /**< Source Address */
LinkerList[linkerListNo][bit][buf].DstAddr = (uint32_t) &LPC_SSP0->DR; /**< Destination address */
LinkerList[linkerListNo][bit][buf].NextLLI = (uint32_t) &LinkerList[linkerListNo+1][bit][buf];/**< Next LLI address, otherwise set to '0' */
LinkerList[linkerListNo][bit][buf].Control = LinkerListControl;
linkerListNo++;
// xprintf("SrcAddr:0x%x DstAddr:0x%x NextLLI:0x%x\n",(uint32_t) &LinkerList[linkerListNo][bit][buf].SrcAddr,(uint32_t) &LinkerList[linkerListNo][bit][buf].DstAddr,(uint32_t) &LinkerList[linkerListNo][bit][buf].NextLLI,(uint32_t) &LinkerList[linkerListNo][bit][buf].Control);
// }
for (reg=11; reg>6;reg--,linkerListNo++){
// xprintf("bit:%d reg:%d SrcAddr:0x%x DstAddr:0x%x NextLLI:0x%x linkerListNo:0x%x\n",bit,reg,(uint32_t) &LED_PRECALC[reg][bit][buf],(uint32_t) &LPC_SSP0->DR,(uint32_t) &LinkerList[linkerListNo+1][bit][buf],linkerListNo);
LinkerList[linkerListNo][bit][buf].SrcAddr = (uint32_t) &LED_PRECALC[reg][bit][buf]; /**< Source Address */
LinkerList[linkerListNo][bit][buf].DstAddr = (uint32_t) &LPC_SSP0->DR; /**< Destination address */
LinkerList[linkerListNo][bit][buf].NextLLI = (uint32_t) &LinkerList[linkerListNo+1][bit][buf]; /**< Next LLI address, otherwise set to '0' */
LinkerList[linkerListNo][bit][buf].Control = LinkerListControl;
// xprintf("SrcAddr:0x%x DstAddr:0x%x NextLLI:0x%x\n",(uint32_t) &LinkerList[linkerListNo][bit][buf].SrcAddr,(uint32_t) &LinkerList[linkerListNo][bit][buf].DstAddr,(uint32_t) &LinkerList[linkerListNo][bit][buf].NextLLI,(uint32_t) &LinkerList[linkerListNo][bit][buf].Control);
}
// if (reg==7){
// xprintf("bit:%d reg:%d SrcAddr:0x%x DstAddr:0x%x NextLLI:0x%x linkerListNo:0x%x\n",bit,reg,(uint32_t) &LED_PRECALC[reg][bit][buf],(uint32_t) &LPC_SSP0->DR,(uint32_t) &LinkerList[linkerListNo+1][bit][buf],linkerListNo);
LinkerList[linkerListNo][bit][buf].SrcAddr = (uint32_t) &LED_PRECALC[reg][bit][buf]; /**< Source Address */
LinkerList[linkerListNo][bit][buf].DstAddr = (uint32_t) &LPC_SSP0->DR; /**< Destination address */
LinkerList[linkerListNo][bit][buf].NextLLI = 0; /**< Next LLI address, otherwise set to '0' */
LinkerList[linkerListNo][bit][buf].Control = LinkerListControl;
linkerListNo++;
// xprintf("SrcAddr:0x%x DstAddr:0x%x NextLLI:0x%x NextLLI_V:0x%x\n",(uint32_t) &LinkerList[linkerListNo][bit][buf].SrcAddr,(uint32_t) &LinkerList[linkerListNo][bit][buf].DstAddr,(uint32_t) &LinkerList[linkerListNo][bit][buf].NextLLI,LinkerList[linkerListNo][bit][buf].NextLLI);
// }
}
}
SSP_DMACmd (LED_SPI_CHN, SSP_DMA_TX, ENABLE); // Enable Tx DMA on SSP0
// GPDMA_ChannelCmd(0, ENABLE); // Enable GPDMA channel 0
NVIC_EnableIRQ (DMA_IRQn); // Enable interrupt for DMA
xprintf(OK "DMA Setup");FFL_();
TIM_Cmd(LPC_TIM0,ENABLE); // To start timer 0
// TIM_Cmd(LPC_TIM1,ENABLE); // To start timer 1 //done at DMA end
TIM_Cmd(LPC_TIM2,ENABLE); // To start timer 2
xprintf(OK "TIM_Cmd(LPC_TIM0/2,ENABLE);");FFL_();
// Start LED Pattern
uint8_t pot = 65;
Set_LED_Pattern(1,121,pot);
xprintf(OK "LED Pattern Started");FFL_();
#endif
#ifdef RxDMA // SSP Rx DMA
GPDMA_Channel_CFG_Type GPDMACfg1;
/* Configure GPDMA channel 1 -------------------------------------------------------------*/
GPDMACfg1.ChannelNum = 1; // DMA Channel 0
GPDMACfg1.SrcMemAddr = 0; // Source memory - not used - will be sent in interrupt so independent bit Linker Lists can be chosen
GPDMACfg1.DstMemAddr = (uint32_t) &LED_PRECALC1[0][0]; // Destination memory - not used - only used when destination is memory
GPDMACfg1.TransferSize = 1; // Transfer size
GPDMACfg1.TransferWidth = GPDMA_WIDTH_HALFWORD; // Transfer width
GPDMACfg1.TransferType = GPDMA_TRANSFERTYPE_P2M; // Transfer type
GPDMACfg1.SrcConn = GPDMA_CONN_SSP0_Rx; // Source connection - not used
GPDMACfg1.DstConn = 0; // Destination connection - not used
GPDMACfg1.DMALLI = 0; // Linker List Item - Pointer to linker list
GPDMA_Setup(&GPDMACfg1); // Setup channel with given parameter
Channel1_TC = 0; // Reset terminal counter
Channel1_Err = 0; // Reset Error counter
xprintf(OK "DMA Rx Setup");FFL_();
// SSP_DMACmd (LED_SPI_CHN, SSP_DMA_RX, ENABLE); // Enable Tx DMA on SSP0
// GPDMA_ChannelCmd(1, ENABLE); // Enable GPDMA channel 0
#endif
}