void fimc_is_hw_subip_power_off(struct fimc_is *is) { fimc_is_hw_wait_intmsr0_intmsd0(is); mcuctl_write(HIC_POWER_DOWN, is, MCUCTL_REG_ISSR(0)); mcuctl_write(is->sensor_index, is, MCUCTL_REG_ISSR(1)); fimc_is_hw_set_intgr0_gd0(is); }
void fimc_is_hw_get_setfile_addr(struct fimc_is *is) { fimc_is_hw_wait_intmsr0_intmsd0(is); mcuctl_write(HIC_GET_SET_FILE_ADDR, is, MCUCTL_REG_ISSR(0)); mcuctl_write(is->sensor_index, is, MCUCTL_REG_ISSR(1)); fimc_is_hw_set_intgr0_gd0(is); }
void fimc_is_hw_stream_off(struct fimc_is *is) { fimc_is_hw_wait_intmsr0_intmsd0(is); mcuctl_write(HIC_STREAM_OFF, is, MCUCTL_REG_ISSR(0)); mcuctl_write(is->sensor_index, is, MCUCTL_REG_ISSR(1)); fimc_is_hw_set_intgr0_gd0(is); }
void fimc_is_hw_load_setfile(struct fimc_is *is) { fimc_is_hw_wait_intmsr0_intmsd0(is); mcuctl_write(HIC_LOAD_SET_FILE, is, MCUCTL_REG_ISSR(0)); mcuctl_write(is->sensor_index, is, MCUCTL_REG_ISSR(1)); fimc_is_hw_set_intgr0_gd0(is); }
static int fimc_is_hw_open_sensor(struct fimc_is *is, struct fimc_is_sensor *sensor) { struct sensor_open_extended *soe = (void *)&is->is_p_region->shared; fimc_is_hw_wait_intmsr0_intmsd0(is); soe->self_calibration_mode = 1; soe->actuator_type = 0; soe->mipi_lane_num = 0; soe->mclk = 0; soe->mipi_speed = 0; soe->fast_open_sensor = 0; soe->i2c_sclk = 88000000; fimc_is_mem_barrier(); mcuctl_write(HIC_OPEN_SENSOR, is, MCUCTL_REG_ISSR(0)); mcuctl_write(is->sensor_index, is, MCUCTL_REG_ISSR(1)); mcuctl_write(sensor->drvdata->id, is, MCUCTL_REG_ISSR(2)); mcuctl_write(sensor->i2c_bus, is, MCUCTL_REG_ISSR(3)); mcuctl_write(is->is_dma_p_region, is, MCUCTL_REG_ISSR(4)); fimc_is_hw_set_intgr0_gd0(is); return fimc_is_wait_event(is, IS_ST_OPEN_SENSOR, 1, FIMC_IS_SENSOR_OPEN_TIMEOUT); }
void fimc_is_hw_set_sensor_num(struct fimc_is *is) { pr_debug("setting sensor index to: %d\n", is->sensor_index); mcuctl_write(IH_REPLY_DONE, is, MCUCTL_REG_ISSR(0)); mcuctl_write(is->sensor_index, is, MCUCTL_REG_ISSR(1)); mcuctl_write(IHC_GET_SENSOR_NUM, is, MCUCTL_REG_ISSR(2)); mcuctl_write(FIMC_IS_SENSOR_NUM, is, MCUCTL_REG_ISSR(3)); }
void fimc_isp_irq_handler(struct fimc_is *is) { is->i2h_cmd.args[0] = mcuctl_read(is, MCUCTL_REG_ISSR(20)); is->i2h_cmd.args[1] = mcuctl_read(is, MCUCTL_REG_ISSR(21)); fimc_is_fw_clear_irq1(is, FIMC_IS_INT_FRAME_DONE_ISP); /* TODO: Complete ISP DMA interrupt handler */ wake_up(&is->irq_queue); }
void fimc_isp_irq_handler(struct fimc_is *is) { is->i2h_cmd.args[0] = mcuctl_read(is, MCUCTL_REG_ISSR(20)); is->i2h_cmd.args[1] = mcuctl_read(is, MCUCTL_REG_ISSR(21)); fimc_is_fw_clear_irq1(is, FIMC_IS_INT_FRAME_DONE_ISP); fimc_isp_video_irq_handler(is); wake_up(&is->irq_queue); }
int fimc_is_hw_set_tune(struct fimc_is *is) { fimc_is_hw_wait_intmsr0_intmsd0(is); mcuctl_write(HIC_SET_TUNE, is, MCUCTL_REG_ISSR(0)); mcuctl_write(is->sensor_index, is, MCUCTL_REG_ISSR(1)); mcuctl_write(is->h2i_cmd.entry_id, is, MCUCTL_REG_ISSR(2)); fimc_is_hw_set_intgr0_gd0(is); return 0; }
void fimc_is_hw_close_sensor(struct fimc_is *is, unsigned int index) { if (is->sensor_index != index) return; fimc_is_hw_wait_intmsr0_intmsd0(is); mcuctl_write(HIC_CLOSE_SENSOR, is, MCUCTL_REG_ISSR(0)); mcuctl_write(is->sensor_index, is, MCUCTL_REG_ISSR(1)); mcuctl_write(is->sensor_index, is, MCUCTL_REG_ISSR(2)); fimc_is_hw_set_intgr0_gd0(is); }
int fimc_is_hw_change_mode(struct fimc_is *is) { const u8 cmd[] = { HIC_PREVIEW_STILL, HIC_PREVIEW_VIDEO, HIC_CAPTURE_STILL, HIC_CAPTURE_VIDEO, }; if (WARN_ON(is->config_index > ARRAY_SIZE(cmd))) return -EINVAL; mcuctl_write(cmd[is->config_index], is, MCUCTL_REG_ISSR(0)); mcuctl_write(is->sensor_index, is, MCUCTL_REG_ISSR(1)); mcuctl_write(is->setfile.sub_index, is, MCUCTL_REG_ISSR(2)); fimc_is_hw_set_intgr0_gd0(is); return 0; }
int fimc_is_hw_get_params(struct fimc_is *is, unsigned int num_args) { int i; if (num_args > FIMC_IS_MAX_PARAMS) return -EINVAL; is->i2h_cmd.num_args = num_args; for (i = 0; i < FIMC_IS_MAX_PARAMS; i++) { if (i < num_args) is->i2h_cmd.args[i] = mcuctl_read(is, MCUCTL_REG_ISSR(12 + i)); else is->i2h_cmd.args[i] = 0; } return 0; }
int fimc_is_hw_set_param(struct fimc_is *is) { struct chain_config *config = &is->config[is->config_index]; unsigned int param_count = __get_pending_param_count(is); fimc_is_hw_wait_intmsr0_intmsd0(is); mcuctl_write(HIC_SET_PARAMETER, is, MCUCTL_REG_ISSR(0)); mcuctl_write(is->sensor_index, is, MCUCTL_REG_ISSR(1)); mcuctl_write(is->config_index, is, MCUCTL_REG_ISSR(2)); mcuctl_write(param_count, is, MCUCTL_REG_ISSR(3)); mcuctl_write(config->p_region_index1, is, MCUCTL_REG_ISSR(4)); mcuctl_write(config->p_region_index2, is, MCUCTL_REG_ISSR(5)); fimc_is_hw_set_intgr0_gd0(is); return 0; }
/* General IS interrupt handler */ static void fimc_is_general_irq_handler(struct fimc_is *is) { is->i2h_cmd.cmd = mcuctl_read(is, MCUCTL_REG_ISSR(10)); switch (is->i2h_cmd.cmd) { case IHC_GET_SENSOR_NUM: fimc_is_hw_get_params(is, 1); fimc_is_hw_wait_intmsr0_intmsd0(is); fimc_is_hw_set_sensor_num(is); pr_debug("ISP FW version: %#x\n", is->i2h_cmd.args[0]); break; case IHC_SET_FACE_MARK: case IHC_FRAME_DONE: fimc_is_hw_get_params(is, 2); break; case IHC_SET_SHOT_MARK: case IHC_AA_DONE: case IH_REPLY_DONE: fimc_is_hw_get_params(is, 3); break; case IH_REPLY_NOT_DONE: fimc_is_hw_get_params(is, 4); break; case IHC_NOT_READY: break; default: pr_info("unknown command: %#x\n", is->i2h_cmd.cmd); } fimc_is_fw_clear_irq1(is, FIMC_IS_INT_GENERAL); switch (is->i2h_cmd.cmd) { case IHC_GET_SENSOR_NUM: fimc_is_hw_set_intgr0_gd0(is); set_bit(IS_ST_A5_PWR_ON, &is->state); break; case IHC_SET_SHOT_MARK: break; case IHC_SET_FACE_MARK: is->fd_header.count = is->i2h_cmd.args[0]; is->fd_header.index = is->i2h_cmd.args[1]; is->fd_header.offset = 0; break; case IHC_FRAME_DONE: break; case IHC_AA_DONE: pr_debug("AA_DONE - %d, %d, %d\n", is->i2h_cmd.args[0], is->i2h_cmd.args[1], is->i2h_cmd.args[2]); break; case IH_REPLY_DONE: pr_debug("ISR_DONE: args[0]: %#x\n", is->i2h_cmd.args[0]); switch (is->i2h_cmd.args[0]) { case HIC_PREVIEW_STILL...HIC_CAPTURE_VIDEO: /* Get CAC margin */ set_bit(IS_ST_CHANGE_MODE, &is->state); is->isp.cac_margin_x = is->i2h_cmd.args[1]; is->isp.cac_margin_y = is->i2h_cmd.args[2]; pr_debug("CAC margin (x,y): (%d,%d)\n", is->isp.cac_margin_x, is->isp.cac_margin_y); break; case HIC_STREAM_ON: clear_bit(IS_ST_STREAM_OFF, &is->state); set_bit(IS_ST_STREAM_ON, &is->state); break; case HIC_STREAM_OFF: clear_bit(IS_ST_STREAM_ON, &is->state); set_bit(IS_ST_STREAM_OFF, &is->state); break; case HIC_SET_PARAMETER: is->config[is->config_index].p_region_index1 = 0; is->config[is->config_index].p_region_index2 = 0; set_bit(IS_ST_BLOCK_CMD_CLEARED, &is->state); pr_debug("HIC_SET_PARAMETER\n"); break; case HIC_GET_PARAMETER: break; case HIC_SET_TUNE: break; case HIC_GET_STATUS: break; case HIC_OPEN_SENSOR: set_bit(IS_ST_OPEN_SENSOR, &is->state); pr_debug("data lanes: %d, settle line: %d\n", is->i2h_cmd.args[2], is->i2h_cmd.args[1]); break; case HIC_CLOSE_SENSOR: clear_bit(IS_ST_OPEN_SENSOR, &is->state); is->sensor_index = 0; break; case HIC_MSG_TEST: pr_debug("config MSG level completed\n"); break; case HIC_POWER_DOWN: clear_bit(IS_ST_PWR_SUBIP_ON, &is->state); break; case HIC_GET_SET_FILE_ADDR: is->setfile.base = is->i2h_cmd.args[1]; set_bit(IS_ST_SETFILE_LOADED, &is->state); break; case HIC_LOAD_SET_FILE: set_bit(IS_ST_SETFILE_LOADED, &is->state); break; } break; case IH_REPLY_NOT_DONE: pr_err("ISR_NDONE: %d: %#x, %s\n", is->i2h_cmd.args[0], is->i2h_cmd.args[1], fimc_is_strerr(is->i2h_cmd.args[1])); if (is->i2h_cmd.args[1] & IS_ERROR_TIME_OUT_FLAG) pr_err("IS_ERROR_TIME_OUT\n"); switch (is->i2h_cmd.args[1]) { case IS_ERROR_SET_PARAMETER: fimc_is_mem_barrier(); } switch (is->i2h_cmd.args[0]) { case HIC_SET_PARAMETER: is->config[is->config_index].p_region_index1 = 0; is->config[is->config_index].p_region_index2 = 0; set_bit(IS_ST_BLOCK_CMD_CLEARED, &is->state); break; } break; case IHC_NOT_READY: pr_err("IS control sequence error: Not Ready\n"); break; } wake_up(&is->irq_queue); }