/* Restore SCLK/SDA pins connected to the product ID chip */
static void gpio_i2c_restore_pins(void)
{
/* Restore I2C3_SCL/I2C_DATA into safe mode; kernel repsonsible
* for muxing I2C3 */
MUX_VAL(CP(I2C3_SCL), (IEN | PTD | EN | M7)); /*I2C3_SCL*/
MUX_VAL(CP(I2C3_SDA), (IEN | PTD | EN | M7)); /*I2C3_SDA*/
}
/*
* Routine: board_init
* Description: Early hardware init.
*/
int board_init(void)
{
gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
/* boot param addr */
gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
mt_ventoux_init_fpga();
/* GPIO_140: speaker #mute */
MUX_VAL(CP(MCBSP3_DX), (IEN | PTU | EN | M4))
/* GPIO_141: Buzz Hi */
MUX_VAL(CP(MCBSP3_DR), (IEN | PTU | EN | M4))
/* Turning off the buzzer */
gpio_request(BUZZER, "BUZZER_MUTE");
gpio_request(SPEAKER, "SPEAKER");
gpio_direction_output(BUZZER, 0);
gpio_direction_output(SPEAKER, 0);
/* Activate USB power */
gpio_request(USB1_PWR, "USB1_PWR");
gpio_request(USB2_PWR, "USB2_PWR");
gpio_direction_output(USB1_PWR, 1);
gpio_direction_output(USB2_PWR, 1);
return 0;
}
void lcd_enable(void)
{
if (lcd_disabled) {
lcd_ctrl_init(lcd_set_base);
}
gpio_pin_init(36, GPIO_OUTPUT, 1);
// Wait one ms before sending down SPI init sequence
udelay(1000);
MUX_VAL(CP(McBSP1_CLKR), (OFF_IN_PD | IEN | PTD | DIS | M4)) /*McSPI4-CLK*/ \
MUX_VAL(CP(McBSP1_DX), (OFF_IN_PD | IDIS | PTD | DIS | M4)) /*McSPI4-SIMO*/ \
MUX_VAL(CP(McBSP1_DR), (OFF_IN_PD | IEN | PTD | DIS | M4)) /*McSPI4-SOMI*/\
MUX_VAL(CP(McBSP1_FSX), (OFF_IN_PD | IEN | PTU | DIS | M4)) /*McSPI4-CS0*/
gpio_pin_init(GPIO_SPI_CLK,GPIO_OUTPUT,1);
gpio_pin_init(GPIO_SPI_SIMO,GPIO_OUTPUT,1);
gpio_pin_init(GPIO_SPI_CS,GPIO_OUTPUT,1);
gpio_pin_init(GPIO_SPI_SOMI,GPIO_INPUT,1);
boxer_init_panel();
omap3_dss_enable();
enable_backlight();
lcd_disabled = 0;
}
/*
** Routine to configure PIN MULTIPLEXING.
** This function sets up the system control muxes to route mcbsp.
*/
void mux_setup_mcbsp(void)
{
/*
** Pin and Pad settings for McBSP.
*/
MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | DIS | M0));
MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTD | DIS | M0));
MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | DIS | M0));
MUX_VAL(CP(MCBSP2_DX), (IDIS | PTD | DIS | M0));
}
void lcd_disable(void)
{
disable_backlight();
sr32(CM_FCLKEN_DSS, 0, 32, 0x0);
sr32(CM_ICLKEN_DSS, 0, 32, 0x0);
gpio_pin_write(36, 0);
// Restore SPI registers
MUX_VAL(CP(McBSP1_CLKR), (IEN | PTD | DIS | M1)) /*McSPI4-CLK*/ \
MUX_VAL(CP(McBSP1_DX), (IDIS | PTD | DIS | M1)) /*McSPI4-SIMO*/ \
MUX_VAL(CP(McBSP1_DR), (IEN | PTD | DIS | M1)) /*McSPI4-SOMI*/\
MUX_VAL(CP(McBSP1_FSX), (IDIS | PTD | DIS | M1)) /*McSPI4-CS0*/
lcd_disabled = 1;
}
int tao3530_revision(void)
{
int ret = 0;
/* char *label argument is unused in gpio_request() */
ret = gpio_request(65, "");
if (ret) {
puts("Error: GPIO 65 not available\n");
goto out;
}
MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M4));
ret = gpio_request(1, "");
if (ret) {
puts("Error: GPIO 1 not available\n");
goto out2;
}
MUX_VAL(CP(SYS_CLKREQ), (IEN | PTU | EN | M4));
ret = gpio_direction_input(65);
if (ret) {
puts("Error: GPIO 65 not available for input\n");
goto out3;
}
ret = gpio_direction_input(1);
if (ret) {
puts("Error: GPIO 1 not available for input\n");
goto out3;
}
ret = gpio_get_value(65) << 1 | gpio_get_value(1);
out3:
MUX_VAL(CP(SYS_CLKREQ), (IEN | PTU | EN | M0));
gpio_free(1);
out2:
MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0));
gpio_free(65);
out:
return ret;
}
void reset_smscChip(void)
{
int i = 0;
/* do a hard reset */
//GPIO 7 configuration in CONTROL_PADCONF_SYS_BOOT5 register mux mode is 4.
MUX_VAL(CP(SYS_BOOT5), (IEN | PTU | EN | M4))
// Enable Clock for GPIO 1-6 module in CM_FCLKEN_PER and CM_ICLKEN_PER registers
writel(readl(CM_FCLKEN_PER) | 0x0003E800, CM_FCLKEN_PER);
writel(readl(CM_ICLKEN_PER) | 0x0003E800, CM_ICLKEN_PER);
// Make GPIO 7 as output pin
writel(readl(OMAP34XX_GPIO1_BASE + GPIO_OE) & ~BIT(7), OMAP34XX_GPIO3_BASE + GPIO_OE);
// Now send a pulse on the GPIO pin
writel(readl(OMAP34XX_GPIO1_BASE + GPIO_DATAOUT) | BIT(7), OMAP34XX_GPIO3_BASE + GPIO_DATAOUT);
for (i = 0; i < 99; i++) ;
writel(readl(OMAP34XX_GPIO1_BASE + GPIO_DATAOUT) & ~BIT(7), OMAP34XX_GPIO3_BASE + GPIO_DATAOUT);
mdelay(100);
for (i = 0; i < 99; i++) ;
writel(readl(OMAP34XX_GPIO1_BASE + GPIO_DATAOUT) | BIT(7), OMAP34XX_GPIO3_BASE + GPIO_DATAOUT);
mdelay(100);
}
static void cm_t35_set_muxconf(void)
{
/* DSS */
MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)); /*DSS_DATA0*/
MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)); /*DSS_DATA1*/
MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)); /*DSS_DATA2*/
MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)); /*DSS_DATA3*/
MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)); /*DSS_DATA4*/
MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)); /*DSS_DATA5*/
MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)); /*DSS_DATA18*/
MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)); /*DSS_DATA19*/
MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)); /*DSS_DATA20*/
MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)); /*DSS_DATA21*/
MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)); /*DSS_DATA22*/
MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)); /*DSS_DATA23*/
/* MMC1 */
MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M0)); /*MMC1_DAT4*/
MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M0)); /*MMC1_DAT5*/
MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M0)); /*MMC1_DAT6*/
MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M0)); /*MMC1_DAT7*/
}
/*
* Routine: set_muxconf_regs
* Description: Setting up the configuration Mux registers specific to the
* hardware. Many pins need to be moved from protect to primary
* mode.
*/
static void cm_t3x_set_common_muxconf(void)
{
/* SDRC */
MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)); /*SDRC_D0*/
MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)); /*SDRC_D1*/
MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)); /*SDRC_D2*/
MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)); /*SDRC_D3*/
MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)); /*SDRC_D4*/
MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)); /*SDRC_D5*/
MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)); /*SDRC_D6*/
MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)); /*SDRC_D7*/
MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)); /*SDRC_D8*/
MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)); /*SDRC_D9*/
MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)); /*SDRC_D10*/
MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)); /*SDRC_D11*/
MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)); /*SDRC_D12*/
MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)); /*SDRC_D13*/
MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)); /*SDRC_D14*/
MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)); /*SDRC_D15*/
MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)); /*SDRC_D16*/
MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)); /*SDRC_D17*/
MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)); /*SDRC_D18*/
MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)); /*SDRC_D19*/
MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)); /*SDRC_D20*/
MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)); /*SDRC_D21*/
MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)); /*SDRC_D22*/
MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)); /*SDRC_D23*/
MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)); /*SDRC_D24*/
MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)); /*SDRC_D25*/
MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)); /*SDRC_D26*/
MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)); /*SDRC_D27*/
MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)); /*SDRC_D28*/
MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)); /*SDRC_D29*/
MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)); /*SDRC_D30*/
MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)); /*SDRC_D31*/
MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)); /*SDRC_CLK*/
MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)); /*SDRC_DQS0*/
MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)); /*SDRC_DQS1*/
MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)); /*SDRC_DQS2*/
MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)); /*SDRC_DQS3*/
MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)); /*SDRC_CKE0*/
MUX_VAL(CP(SDRC_CKE1), (IDIS | PTD | DIS | M7)); /*SDRC_CKE1*/
/* GPMC */
MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)); /*GPMC_A1*/
MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)); /*GPMC_A2*/
MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)); /*GPMC_A3*/
MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)); /*GPMC_A4*/
MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)); /*GPMC_A5*/
MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)); /*GPMC_A6*/
MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)); /*GPMC_A7*/
MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)); /*GPMC_A8*/
MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)); /*GPMC_A9*/
MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)); /*GPMC_A10*/
MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)); /*GPMC_D0*/
MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)); /*GPMC_D1*/
MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)); /*GPMC_D2*/
MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)); /*GPMC_D3*/
MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)); /*GPMC_D4*/
MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)); /*GPMC_D5*/
MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)); /*GPMC_D6*/
MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)); /*GPMC_D7*/
MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)); /*GPMC_D8*/
MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)); /*GPMC_D9*/
MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)); /*GPMC_D10*/
MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)); /*GPMC_D11*/
MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)); /*GPMC_D12*/
MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)); /*GPMC_D13*/
MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)); /*GPMC_D14*/
MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)); /*GPMC_D15*/
MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)); /*GPMC_nCS0*/
/* SB-T35 Ethernet */
MUX_VAL(CP(GPMC_NCS4), (IEN | PTU | EN | M0)); /*GPMC_nCS4*/
/* CM-T3x Ethernet */
MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | DIS | M0)); /*GPMC_nCS5*/
MUX_VAL(CP(GPMC_CLK), (IEN | PTD | DIS | M4)); /*GPIO_59*/
MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)); /*nADV_ALE*/
MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)); /*nOE*/
MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)); /*nWE*/
MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0)); /*nBE0_CLE*/
MUX_VAL(CP(GPMC_NBE1), (IDIS | PTD | DIS | M4)); /*GPIO_61*/
MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)); /*nWP*/
MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)); /*WAIT0*/
/* DSS */
MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)); /*DSS_PCLK*/
MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)); /*DSS_HSYNC*/
MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)); /*DSS_VSYNC*/
MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)); /*DSS_ACBIAS*/
MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)); /*DSS_DATA6*/
MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)); /*DSS_DATA7*/
MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)); /*DSS_DATA8*/
MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)); /*DSS_DATA9*/
MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)); /*DSS_DATA10*/
MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)); /*DSS_DATA11*/
MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)); /*DSS_DATA12*/
MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)); /*DSS_DATA13*/
MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)); /*DSS_DATA14*/
MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)); /*DSS_DATA15*/
MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)); /*DSS_DATA16*/
MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)); /*DSS_DATA17*/
/* serial interface */
MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)); /*UART3_RX*/
MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)); /*UART3_TX*/
/* mUSB */
MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)); /*HSUSB0_CLK*/
MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)); /*HSUSB0_STP*/
MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)); /*HSUSB0_DIR*/
MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)); /*HSUSB0_NXT*/
MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA0*/
MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA1*/
MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA2*/
MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA3*/
MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA4*/
MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA5*/
MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA6*/
MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA7*/
/* I2C1 */
MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)); /*I2C1_SCL*/
MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)); /*I2C1_SDA*/
/* I2C2 */
MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)); /*I2C2_SCL*/
MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)); /*I2C2_SDA*/
/* I2C3 */
MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)); /*I2C3_SCL*/
MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)); /*I2C3_SDA*/
/* control and debug */
MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)); /*SYS_32K*/
MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)); /*SYS_CLKREQ*/
MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)); /*SYS_nIRQ*/
MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)); /*OFF_MODE*/
MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)); /*CLKOUT1*/
MUX_VAL(CP(SYS_CLKOUT2), (IDIS | PTU | DIS | M4)); /*green LED*/
MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0)); /*JTAG_nTRST*/
MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)); /*JTAG_TCK*/
MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)); /*JTAG_TMS*/
MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)); /*JTAG_TDI*/
/* MMC1 */
MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)); /*MMC1_CLK*/
MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)); /*MMC1_CMD*/
MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)); /*MMC1_DAT0*/
MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)); /*MMC1_DAT1*/
MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)); /*MMC1_DAT2*/
MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)); /*MMC1_DAT3*/
}
/**
* @brief Do the necessary pin muxing required for OMAP3EVM. Some pins in OMAP3
* do not have alternate modes. We don't program these pins.
*
* See @ref MUX_VAL for description of the muxing mode.
*
* @return void
*/
static void mux_config(void)
{
/*
* SDRC
* - SDRC_D0-SDRC_D31: Default MUX mode is mode0.
*/
/*
* GPMC
* - GPMC_D0-GPMC_D7: Default MUX mode is mode0.
* - GPMC_NADV_ALE: Default MUX mode is mode0.
* - GPMC_NOE: Default MUX mode is mode0.
* - GPMC_NWE: Default MUX mode is mode0.
* - GPMC_WAIT0: Default MUX mode is mode0.
*/
MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0));
MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0));
MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0));
MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0));
MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0));
MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0));
MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0));
MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0));
MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0));
MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0));
MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0));
MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0));
MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0));
MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0));
MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0));
MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0));
MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0));
MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0));
MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0));
MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTD | DIS | M0));
MUX_VAL(CP(GPMC_NBE1), (IEN | PTD | DIS | M0));
MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0));
MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0));
/*
* Serial Interface
*/
#if defined(CONFIG_OMAP_UART1)
MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0));
MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0));
MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0));
MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0));
#elif defined(CONFIG_OMAP_UART3)
MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M0));
MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0));
MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0));
MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0));
#endif
}
/*
* Routine: set_muxconf_regs
* Description: Setting up the configuration Mux registers specific to the
* hardware. Many pins need to be moved from protect to primary
* mode.
*/
static void cm_t3x_set_common_muxconf(void)
{
/* SDRC */
MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)); /*SDRC_D0*/
MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)); /*SDRC_D1*/
MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)); /*SDRC_D2*/
MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)); /*SDRC_D3*/
MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)); /*SDRC_D4*/
MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)); /*SDRC_D5*/
MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)); /*SDRC_D6*/
MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)); /*SDRC_D7*/
MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)); /*SDRC_D8*/
MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)); /*SDRC_D9*/
MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)); /*SDRC_D10*/
MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)); /*SDRC_D11*/
MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)); /*SDRC_D12*/
MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)); /*SDRC_D13*/
MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)); /*SDRC_D14*/
MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)); /*SDRC_D15*/
MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)); /*SDRC_D16*/
MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)); /*SDRC_D17*/
MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)); /*SDRC_D18*/
MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)); /*SDRC_D19*/
MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)); /*SDRC_D20*/
MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)); /*SDRC_D21*/
MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)); /*SDRC_D22*/
MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)); /*SDRC_D23*/
MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)); /*SDRC_D24*/
MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)); /*SDRC_D25*/
MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)); /*SDRC_D26*/
MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)); /*SDRC_D27*/
MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)); /*SDRC_D28*/
MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)); /*SDRC_D29*/
MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)); /*SDRC_D30*/
MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)); /*SDRC_D31*/
MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)); /*SDRC_CLK*/
MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)); /*SDRC_DQS0*/
MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)); /*SDRC_DQS1*/
MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)); /*SDRC_DQS2*/
MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)); /*SDRC_DQS3*/
MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)); /*SDRC_CKE0*/
MUX_VAL(CP(SDRC_CKE1), (IDIS | PTD | DIS | M7)); /*SDRC_CKE1*/
/* GPMC */
MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)); /*GPMC_A1*/
MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)); /*GPMC_A2*/
MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)); /*GPMC_A3*/
MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)); /*GPMC_A4*/
MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)); /*GPMC_A5*/
MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)); /*GPMC_A6*/
MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)); /*GPMC_A7*/
MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)); /*GPMC_A8*/
MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)); /*GPMC_A9*/
MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)); /*GPMC_A10*/
MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)); /*GPMC_D0*/
MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)); /*GPMC_D1*/
MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)); /*GPMC_D2*/
MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)); /*GPMC_D3*/
MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)); /*GPMC_D4*/
MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)); /*GPMC_D5*/
MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)); /*GPMC_D6*/
MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)); /*GPMC_D7*/
MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)); /*GPMC_D8*/
MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)); /*GPMC_D9*/
MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)); /*GPMC_D10*/
MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)); /*GPMC_D11*/
MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)); /*GPMC_D12*/
MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)); /*GPMC_D13*/
MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)); /*GPMC_D14*/
MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)); /*GPMC_D15*/
MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)); /*GPMC_nCS0*/
/* SB-T35 Ethernet */
MUX_VAL(CP(GPMC_NCS4), (IEN | PTU | EN | M0)); /*GPMC_nCS4*/
/* DVI enable */
MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | DIS | M4));/*GPMC_nCS3*/
/* DataImage backlight */
MUX_VAL(CP(GPMC_NCS7), (IDIS | PTU | DIS | M4));/*GPIO_58*/
/* CM-T3x Ethernet */
MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | DIS | M0)); /*GPMC_nCS5*/
MUX_VAL(CP(GPMC_CLK), (IEN | PTD | DIS | M4)); /*GPIO_59*/
MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)); /*nADV_ALE*/
MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)); /*nOE*/
MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)); /*nWE*/
MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0)); /*nBE0_CLE*/
MUX_VAL(CP(GPMC_NBE1), (IDIS | PTD | DIS | M4)); /*GPIO_61*/
MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)); /*nWP*/
MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)); /*WAIT0*/
/* DSS */
MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)); /*DSS_PCLK*/
MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)); /*DSS_HSYNC*/
MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)); /*DSS_VSYNC*/
MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)); /*DSS_ACBIAS*/
MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)); /*DSS_DATA6*/
MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)); /*DSS_DATA7*/
MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)); /*DSS_DATA8*/
MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)); /*DSS_DATA9*/
MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)); /*DSS_DATA10*/
MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)); /*DSS_DATA11*/
MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)); /*DSS_DATA12*/
MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)); /*DSS_DATA13*/
MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)); /*DSS_DATA14*/
MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)); /*DSS_DATA15*/
MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)); /*DSS_DATA16*/
MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)); /*DSS_DATA17*/
/* serial interface */
MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)); /*UART3_RX*/
MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)); /*UART3_TX*/
/* mUSB */
MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)); /*HSUSB0_CLK*/
MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)); /*HSUSB0_STP*/
MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)); /*HSUSB0_DIR*/
MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)); /*HSUSB0_NXT*/
MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA0*/
MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA1*/
MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA2*/
MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA3*/
MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA4*/
MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA5*/
MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA6*/
MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA7*/
/* USB EHCI */
MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT0*/
MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT1*/
MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT2*/
MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT3*/
MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT4*/
MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT5*/
MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT6*/
MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT7*/
MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DIR*/
MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_NXT*/
MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M3)); /*HSUSB1_CLK*/
MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | DIS | M3)); /*HSUSB1_STP*/
MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_DT0*/
MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_DT1*/
MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M3)); /*HSUSB2_DT2*/
MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M3)); /*HSUSB2_DT3*/
MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | EN | M3)); /*HSUSB2_DT4*/
MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | EN | M3)); /*HSUSB2_DT5*/
MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M3)); /*HSUSB2_DT6*/
MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | EN | M3)); /*HSUSB2_DT7*/
MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_DIR*/
MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_NXT*/
MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTD | DIS | M3)); /*HSUSB2_CLK*/
MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTU | DIS | M3)); /*HSUSB2_STP*/
/* SB_T35_USB_HUB_RESET_GPIO */
MUX_VAL(CP(CAM_WEN), (IDIS | PTD | DIS | M4)); /*GPIO_167*/
/* I2C1 */
MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)); /*I2C1_SCL*/
MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)); /*I2C1_SDA*/
/* I2C2 */
MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)); /*I2C2_SCL*/
MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)); /*I2C2_SDA*/
/* I2C3 */
MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)); /*I2C3_SCL*/
MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)); /*I2C3_SDA*/
/* control and debug */
MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)); /*SYS_32K*/
MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)); /*SYS_CLKREQ*/
MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)); /*SYS_nIRQ*/
MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)); /*OFF_MODE*/
MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)); /*CLKOUT1*/
MUX_VAL(CP(SYS_CLKOUT2), (IDIS | PTU | DIS | M4)); /*green LED*/
MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0)); /*JTAG_nTRST*/
MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)); /*JTAG_TCK*/
MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)); /*JTAG_TMS*/
MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)); /*JTAG_TDI*/
/* MMC1 */
MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)); /*MMC1_CLK*/
MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)); /*MMC1_CMD*/
MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)); /*MMC1_DAT0*/
MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)); /*MMC1_DAT1*/
MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)); /*MMC1_DAT2*/
MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)); /*MMC1_DAT3*/
/* SPI */
MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M1)); /*MCSPI4_CLK*/
MUX_VAL(CP(MCBSP1_DX), (IEN | PTD | DIS | M1)); /*MCSPI4_SIMO*/
MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M1)); /*MCSPI4_SOMI*/
MUX_VAL(CP(MCBSP1_FSX), (IEN | PTU | EN | M1)); /*MCSPI4_CS0*/
/* display controls */
MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | DIS | M4)); /*GPIO_157*/
}
int status_init(void)
{
isXM = (get_board_revision() == REVISION_XM);
i2c_set_bus_num(TWL4030_I2C_BUS);
if(isXM) {
/* Set VAUX1 to 3.3V for GTA04E display board */
twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VAUX1_DEDICATED,
/*TWL4030_PM_RECEIVER_VAUX1_VSEL_33*/ 0x07,
TWL4030_PM_RECEIVER_VAUX1_DEV_GRP,
TWL4030_PM_RECEIVER_DEV_GRP_P1);
udelay(5000);
}
#if !defined(CONFIG_OMAP3_GTA04) // we assume that a GTA04 always has a TCA6507
if(i2c_set_bus_num(TCA6507_BUS))
{
printf ("could not select I2C2\n");
return 1;
}
hasTCA6507 = !i2c_probe(TCA6507_ADDRESS);
#endif
if(!hasTCA6507) {
if(isXM) { // XM has scrambled dss assignment with respect to default ball names
MUX_VAL(CP(DSS_DATA18), (IEN | PTD | EN | M4)); /*GPIO */
MUX_VAL(CP(DSS_DATA19), (IEN | PTD | EN | M4)); /*GPIO */
MUX_VAL(CP(DSS_DATA8), (IEN | PTD | EN | M4)); /*GPIO */
MUX_VAL(CP(DSS_DATA9), (IEN | PTD | EN | M4)); /*GPIO */
MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | EN | M4)); /*GPIO */
MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | EN | M4)); /*GPIO */
}
else {
MUX_VAL(CP(DSS_DATA0), (IEN | PTD | EN | M4)); /*GPIO */
MUX_VAL(CP(DSS_DATA1), (IEN | PTD | EN | M4)); /*GPIO */
MUX_VAL(CP(DSS_DATA8), (IEN | PTD | EN | M4)); /*GPIO */
MUX_VAL(CP(DSS_DATA9), (IEN | PTD | EN | M4)); /*GPIO */
MUX_VAL(CP(DSS_DATA16), (IEN | PTD | EN | M4)); /*GPIO */
MUX_VAL(CP(DSS_DATA17), (IEN | PTD | EN | M4)); /*GPIO */
}
omap_request_gpio(GPIO_LED_AUX_GREEN);
omap_request_gpio(GPIO_LED_AUX_RED);
omap_request_gpio(GPIO_LED_POWER_GREEN);
omap_request_gpio(GPIO_LED_POWER_RED);
omap_request_gpio(GPIO_LED_VIBRA);
omap_request_gpio(GPIO_LED_UNUSED);
if(GPIO_POWER >= 0)
omap_request_gpio(GPIO_POWER);
}
else {
// initialize I2C controller
}
if(GPIO_AUX >= 0)
omap_request_gpio(GPIO_AUX);
if(GPIO_POWER >= 0)
omap_request_gpio(GPIO_POWER);
if(GPIO_GPSEXT >= 0)
omap_request_gpio(GPIO_GPSEXT);
if(GPIO_PENIRQ >= 0)
omap_request_gpio(GPIO_PENIRQ);
if(GPIO_KEYIRQ >= 0)
omap_request_gpio(GPIO_KEYIRQ);
if(!hasTCA6507) {
omap_set_gpio_direction(GPIO_LED_AUX_GREEN, 0); // output
omap_set_gpio_direction(GPIO_LED_AUX_RED, 0); // output
omap_set_gpio_direction(GPIO_LED_POWER_GREEN, 0); // output
omap_set_gpio_direction(GPIO_LED_POWER_RED, 0); // output
omap_set_gpio_direction(GPIO_LED_VIBRA, 0); // output
omap_set_gpio_direction(GPIO_LED_UNUSED, 0); // output
}
if(GPIO_AUX >= 0)
omap_set_gpio_direction(GPIO_AUX, 1); // input
if(GPIO_POWER >= 0)
omap_set_gpio_direction(GPIO_POWER, 1); // input
if(GPIO_GPSEXT >= 0)
omap_set_gpio_direction(GPIO_GPSEXT, 1); // input
if(GPIO_PENIRQ >= 0)
omap_set_gpio_direction(GPIO_PENIRQ, 1); // input
if(GPIO_KEYIRQ >= 0)
omap_set_gpio_direction(GPIO_KEYIRQ, 1); // input
// when sould we do omap_free_gpio(GPIO_LED_AUX_GREEN); ?
printf("did init LED driver for %s\n", hasTCA6507?"TCA6507":"GPIOs");
return 0;
}
/**
* @brief Do the pin muxing required for Board operation.
* We enable ONLY the pins we require to set. OMAP provides pins which do not
* have alternate modes. Such pins done need to be set.
*
* See @ref MUX_VAL for description of the muxing mode.
*
* @return void
*/
static void mux_config(void)
{
/* SDRC_D0 - SDRC_D31 default mux mode is mode0 */
/* GPMC */
MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0));
MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0));
MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0));
MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0));
MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0));
MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0));
MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0));
MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0));
MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0));
MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0));
/* D0-D7 default mux mode is mode0 */
MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0));
MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0));
MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0));
MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0));
MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0));
MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0));
MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0));
MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0));
MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0));
/* GPMC_NADV_ALE default mux mode is mode0 */
/* GPMC_NOE default mux mode is mode0 */
/* GPMC_NWE default mux mode is mode0 */
/* GPMC_NBE0_CLE default mux mode is mode0 */
MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTD | DIS | M0));
MUX_VAL(CP(GPMC_NBE1), (IEN | PTD | DIS | M0));
MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0));
/* GPMC_WAIT0 default mux mode is mode0 */
MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0));
/* SERIAL INTERFACE */
MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M0));
MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0));
MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0));
MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0));
MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0));
MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0));
MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0));
MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0));
MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0));
MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0));
MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0));
MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0));
MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0));
MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0));
MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0));
MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0));
/* I2C1_SCL default mux mode is mode0 */
/* I2C1_SDA default mux mode is mode0 */
/* USB EHCI (port 2) */
MUX_VAL(CP(MCSPI1_CS3), (IEN | PTU | DIS | M3));
MUX_VAL(CP(MCSPI2_CLK), (IEN | PTU | DIS | M3));
MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTU | DIS | M3));
MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTU | DIS | M3));
MUX_VAL(CP(MCSPI2_CS0), (IEN | PTU | DIS | M3));
MUX_VAL(CP(MCSPI2_CS1), (IEN | PTU | DIS | M3));
MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTU | DIS | M3));
MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTU | DIS | M3));
MUX_VAL(CP(ETK_D12_ES2), (IEN | PTU | DIS | M3));
MUX_VAL(CP(ETK_D13_ES2), (IEN | PTU | DIS | M3));
MUX_VAL(CP(ETK_D14_ES2), (IEN | PTU | DIS | M3));
MUX_VAL(CP(ETK_D15_ES2), (IEN | PTU | DIS | M3));
MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M4)) /*GPIO_147*/;
/* Expansion card */
MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)); /* MMC1_CLK */
MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)); /* MMC1_CMD */
MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)); /* MMC1_DAT0 */
MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)); /* MMC1_DAT1 */
MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)); /* MMC1_DAT2 */
MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)); /* MMC1_DAT3 */
MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M0)); /* MMC1_DAT4 */
MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M0)); /* MMC1_DAT5 */
MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M0)); /* MMC1_DAT6 */
MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M0)); /* MMC1_DAT7 */
}
static void cm_t3730_set_muxconf(void)
{
/* DSS */
MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M3)); /*DSS_DATA0*/
MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M3)); /*DSS_DATA1*/
MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M3)); /*DSS_DATA2*/
MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M3)); /*DSS_DATA3*/
MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M3)); /*DSS_DATA4*/
MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M3)); /*DSS_DATA5*/
MUX_VAL(CP(SYS_BOOT0), (IDIS | PTD | DIS | M3)); /*DSS_DATA18*/
MUX_VAL(CP(SYS_BOOT1), (IDIS | PTD | DIS | M3)); /*DSS_DATA19*/
MUX_VAL(CP(SYS_BOOT3), (IDIS | PTD | DIS | M3)); /*DSS_DATA20*/
MUX_VAL(CP(SYS_BOOT4), (IDIS | PTD | DIS | M3)); /*DSS_DATA21*/
MUX_VAL(CP(SYS_BOOT5), (IDIS | PTD | DIS | M3)); /*DSS_DATA22*/
MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M3)); /*DSS_DATA23*/
}
int status_init(void)
{
extern int isXM(void);
i2c_set_bus_num(TWL4030_I2C_BUS);
thisIsXM = isXM();
if(thisIsXM) {
/* Set VAUX1 to 3.3V for GTA04E display board */
twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VAUX1_DEDICATED,
/*TWL4030_PM_RECEIVER_VAUX1_VSEL_33*/ 0x07,
TWL4030_PM_RECEIVER_VAUX1_DEV_GRP,
TWL4030_PM_RECEIVER_DEV_GRP_P1);
udelay(5000);
}
#if CHECK_TCA6507
if(i2c_set_bus_num(TCA6507_BUS))
{ // check if we have a tca
printf ("could not select I2C2 to probe for TCA6507\n");
return 1;
}
hasTCA6507 = !i2c_probe(TCA6507_ADDRESS);
#endif
if(!hasTCA6507) { // reuse DSS pins
if(thisIsXM) { // XM has scrambled dss assignment with respect to default ball names
MUX_VAL(CP(DSS_DATA18), (IEN | PTD | EN | M4)); /*GPIO */
MUX_VAL(CP(DSS_DATA19), (IEN | PTD | EN | M4)); /*GPIO */
MUX_VAL(CP(DSS_DATA8), (IEN | PTD | EN | M4)); /*GPIO */
MUX_VAL(CP(DSS_DATA9), (IEN | PTD | EN | M4)); /*GPIO */
MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | EN | M4)); /*GPIO */
MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | EN | M4)); /*GPIO */
}
else {
MUX_VAL(CP(DSS_DATA0), (IEN | PTD | EN | M4)); /*GPIO */
MUX_VAL(CP(DSS_DATA1), (IEN | PTD | EN | M4)); /*GPIO */
MUX_VAL(CP(DSS_DATA8), (IEN | PTD | EN | M4)); /*GPIO */
MUX_VAL(CP(DSS_DATA9), (IEN | PTD | EN | M4)); /*GPIO */
MUX_VAL(CP(DSS_DATA16), (IEN | PTD | EN | M4)); /*GPIO */
MUX_VAL(CP(DSS_DATA17), (IEN | PTD | EN | M4)); /*GPIO */
}
gpio_request(GPIO_LED_AUX_GREEN, "green-aux");
gpio_request(GPIO_LED_AUX_RED, "red-aux");
gpio_request(GPIO_LED_POWER_GREEN, "green-power");
gpio_request(GPIO_LED_POWER_RED, "red-power");
gpio_request(GPIO_LED_VIBRA, "vibra");
gpio_request(GPIO_LED_UNUSED, "unused");
if(GPIO_POWER >= 0)
gpio_request(GPIO_POWER, "power");
}
else {
// initialize I2C controller
}
if(GPIO_AUX >= 0)
gpio_request(GPIO_AUX, "aus");
if(GPIO_POWER >= 0)
gpio_request(GPIO_POWER, "power");
if(GPIO_GPSEXT >= 0)
gpio_request(GPIO_GPSEXT, "ext-gps");
if(GPIO_PENIRQ >= 0)
gpio_request(GPIO_PENIRQ, "penirq");
if(GPIO_KEYIRQ >= 0)
gpio_request(GPIO_KEYIRQ, "keyirq");
if(!hasTCA6507) {
gpio_direction_output(GPIO_LED_AUX_GREEN, 0); // output
gpio_direction_output(GPIO_LED_AUX_RED, 0); // output
gpio_direction_output(GPIO_LED_POWER_GREEN, 0); // output
gpio_direction_output(GPIO_LED_POWER_RED, 0); // output
gpio_direction_output(GPIO_LED_VIBRA, 0); // output
gpio_direction_output(GPIO_LED_UNUSED, 0); // output
}
if(GPIO_AUX >= 0)
gpio_direction_input(GPIO_AUX); // input
if(GPIO_POWER >= 0)
gpio_direction_input(GPIO_POWER); // input
if(GPIO_GPSEXT >= 0)
gpio_direction_input(GPIO_GPSEXT); // input
if(GPIO_PENIRQ >= 0)
gpio_direction_input(GPIO_PENIRQ); // input
if(GPIO_KEYIRQ >= 0)
gpio_direction_input(GPIO_KEYIRQ); // input
// when sould we do omap_free_gpio(GPIO_LED_AUX_GREEN); ?
printf("did init LED driver for %s\n", hasTCA6507?"TCA6507":"GPIOs");
return 0;
}
/* Put SCLK/SDA pins connected to the product ID into GPIO mode */
static void gpio_i2c_config_pins(void)
{
MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M4)); /*I2C3_SCL*/
MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M4)); /*I2C3_SDA*/
}
/**
* @brief Do the pin muxing required for Board operation.
*
* See @ref MUX_VAL for description of the muxing mode. Since some versions
* of Linux depend on all pin muxing being done at barebox level, we may need to
* enable CONFIG_MACH_OMAP_ADVANCED_MUX to enable the full fledged pin muxing.
*
* @return void
*/
static void mux_config(void)
{
/* Essential MUX Settings */
MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)); /* SDRC_D0 */
MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)); /* SDRC_D1 */
MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)); /* SDRC_D2 */
MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)); /* SDRC_D3 */
MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)); /* SDRC_D4 */
MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)); /* SDRC_D5 */
MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)); /* SDRC_D6 */
MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)); /* SDRC_D7 */
MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)); /* SDRC_D8 */
MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)); /* SDRC_D9 */
MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)); /* SDRC_D10 */
MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)); /* SDRC_D11 */
MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)); /* SDRC_D12 */
MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)); /* SDRC_D13 */
MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)); /* SDRC_D14 */
MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)); /* SDRC_D15 */
MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)); /* SDRC_D16 */
MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)); /* SDRC_D17 */
MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)); /* SDRC_D18 */
MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)); /* SDRC_D19 */
MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)); /* SDRC_D20 */
MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)); /* SDRC_D21 */
MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)); /* SDRC_D22 */
MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)); /* SDRC_D23 */
MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)); /* SDRC_D24 */
MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)); /* SDRC_D25 */
MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)); /* SDRC_D26 */
MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)); /* SDRC_D27 */
MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)); /* SDRC_D28 */
MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)); /* SDRC_D29 */
MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)); /* SDRC_D30 */
MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)); /* SDRC_D31 */
MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)); /* SDRC_CLK */
MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)); /* SDRC_DQS0 */
MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)); /* SDRC_DQS1 */
MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)); /* SDRC_DQS2 */
MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)); /* SDRC_DQS3 */
/* GPMC */
MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)); /* GPMC_A1 */
MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)); /* GPMC_A2 */
MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)); /* GPMC_A3 */
MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)); /* GPMC_A4 */
MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)); /* GPMC_A5 */
MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)); /* GPMC_A6 */
MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)); /* GPMC_A7 */
MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)); /* GPMC_A8 */
MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0)); /* GPMC_A9 */
MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)); /* GPMC_A10 */
MUX_VAL(CP(GPMC_D0), (IEN | PTD | DIS | M0)); /* GPMC_D0 */
MUX_VAL(CP(GPMC_D1), (IEN | PTD | DIS | M0)); /* GPMC_D1 */
MUX_VAL(CP(GPMC_D2), (IEN | PTD | DIS | M0)); /* GPMC_D2 */
MUX_VAL(CP(GPMC_D3), (IEN | PTD | DIS | M0)); /* GPMC_D3 */
MUX_VAL(CP(GPMC_D4), (IEN | PTD | DIS | M0)); /* GPMC_D4 */
MUX_VAL(CP(GPMC_D5), (IEN | PTD | DIS | M0)); /* GPMC_D5 */
MUX_VAL(CP(GPMC_D6), (IEN | PTD | DIS | M0)); /* GPMC_D6 */
MUX_VAL(CP(GPMC_D7), (IEN | PTD | DIS | M0)); /* GPMC_D7 */
MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0)); /* GPMC_D8 */
MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0)); /* GPMC_D9 */
MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0)); /* GPMC_D10 */
MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0)); /* GPMC_D11 */
MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0)); /* GPMC_D12 */
MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0)); /* GPMC_D13 */
MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0)); /* GPMC_D14 */
MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0)); /* GPMC_D15 */
MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)); /* GPMC_NCS0 */
MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)); /* GPMC_NCS1 */
MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)); /* GPMC_NCS2 */
MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M0)); /* GPMC_NCS3 */
/* GPIO_55 - FLASH_DIS */
MUX_VAL(CP(GPMC_NCS4), (IEN | PTU | EN | M4));
/* GPIO_56 - TORCH_EN */
MUX_VAL(CP(GPMC_NCS5), (IDIS | PTD | DIS | M4));
/* GPIO_57 - AGPS SLP */
MUX_VAL(CP(GPMC_NCS6), (IEN | PTD | DIS | M4));
/* GPMC_58 - WLAN_IRQ */
MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M4));
MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0)); /* GPMC_CLK */
/* GPMC_NADV_ALE */
MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0));
MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)); /* GPMC_NOE */
MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)); /* GPMC_NWE */
/* GPMC_NBE0_CLE */
MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTD | DIS | M0));
MUX_VAL(CP(GPMC_NBE1), (IEN | PTD | DIS | M4)); /* GPIO_61 -BT_SHUTDN */
MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)); /* GPMC_NWP */
MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)); /* GPMC_WAIT0 */
MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)); /* GPMC_WAIT1 */
MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4)); /* GPIO_64 */
MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M4)); /* GPIO_65 */
/* SERIAL INTERFACE */
/* UART3_CTS_RCTX */
MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M0));
/* UART3_RTS_SD */
MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0));
/* UART3_RX_IRRX */
MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0));
/* UART3_TX_IRTX */
MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0));
/* HSUSB0_CLK */
MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0));
/* HSUSB0_STP */
MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0));
/* HSUSB0_DIR */
MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0));
/* HSUSB0_NXT */
MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0));
/* HSUSB0_DATA0 */
MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0));
/* HSUSB0_DATA1 */
MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0));
/* HSUSB0_DATA2 */
MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0));
/* HSUSB0_DATA3 */
MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0));
/* HSUSB0_DATA4 */
MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0));
/* HSUSB0_DATA5 */
MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0));
/* HSUSB0_DATA6 */
MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0));
/* HSUSB0_DATA7 */
MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0));
MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)); /* I2C1_SCL */
MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)); /* I2C1_SDA */
#ifdef CONFIG_MACH_OMAP_ADVANCED_MUX
/* DSS */
MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)); /* DSS_PCLK */
MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)); /* DSS_HSYNC */
MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)); /* DSS_VSYNC */
MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)); /* DSS_ACBIAS */
MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)); /* DSS_DATA0 */
MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)); /* DSS_DATA1 */
MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)); /* DSS_DATA2 */
MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)); /* DSS_DATA3 */
MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)); /* DSS_DATA4 */
MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)); /* DSS_DATA5 */
MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)); /* DSS_DATA6 */
MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)); /* DSS_DATA7 */
MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)); /* DSS_DATA8 */
MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)); /* DSS_DATA9 */
MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)); /* DSS_DATA10 */
MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)); /* DSS_DATA11 */
MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)); /* DSS_DATA12 */
MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)); /* DSS_DATA13 */
MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)); /* DSS_DATA14 */
MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)); /* DSS_DATA15 */
MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)); /* DSS_DATA16 */
MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)); /* DSS_DATA17 */
MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)); /* DSS_DATA18 */
MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)); /* DSS_DATA19 */
MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)); /* DSS_DATA20 */
MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)); /* DSS_DATA21 */
MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)); /* DSS_DATA22 */
MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)); /* DSS_DATA23 */
/* CAMERA */
MUX_VAL(CP(CAM_HS), (IEN | PTU | EN | M0)); /* CAM_HS */
MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M0)); /* CAM_VS */
MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0)); /* CAM_XCLKA */
MUX_VAL(CP(CAM_PCLK), (IEN | PTU | EN | M0)); /* CAM_PCLK */
/* GPIO_98 - CAM_RESET */
MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4));
MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M0)); /* CAM_D0 */
MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M0)); /* CAM_D1 */
MUX_VAL(CP(CAM_D2), (IEN | PTD | DIS | M0)); /* CAM_D2 */
MUX_VAL(CP(CAM_D3), (IEN | PTD | DIS | M0)); /* CAM_D3 */
MUX_VAL(CP(CAM_D4), (IEN | PTD | DIS | M0)); /* CAM_D4 */
MUX_VAL(CP(CAM_D5), (IEN | PTD | DIS | M0)); /* CAM_D5 */
MUX_VAL(CP(CAM_D6), (IEN | PTD | DIS | M0)); /* CAM_D6 */
MUX_VAL(CP(CAM_D7), (IEN | PTD | DIS | M0)); /* CAM_D7 */
MUX_VAL(CP(CAM_D8), (IEN | PTD | DIS | M0)); /* CAM_D8 */
MUX_VAL(CP(CAM_D9), (IEN | PTD | DIS | M0)); /* CAM_D9 */
MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M0)); /* CAM_D10 */
MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M0)); /* CAM_D11 */
MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M0)); /* CAM_XCLKB */
MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)); /* GPIO_167 */
MUX_VAL(CP(CAM_STROBE), (IDIS | PTD | DIS | M0)); /* CAM_STROBE */
MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)); /* CSI2_DX0 */
MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)); /* CSI2_DY0 */
MUX_VAL(CP(CSI2_DX1), (IEN | PTD | DIS | M0)); /* CSI2_DX1 */
MUX_VAL(CP(CSI2_DY1), (IEN | PTD | DIS | M0)); /* CSI2_DY1 */
/* AUDIO INTERFACE */
MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | DIS | M0)); /* MCBSP2_FSX */
/* MCBSP2_CLKX */
MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTD | DIS | M0));
MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | DIS | M0)); /* MCBSP2_DR */
MUX_VAL(CP(MCBSP2_DX), (IDIS | PTD | DIS | M0)); /* MCBSP2_DX */
/* EXPANSION CARD */
MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)); /* MMC1_CLK */
MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)); /* MMC1_CMD */
MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)); /* MMC1_DAT0 */
MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)); /* MMC1_DAT1 */
MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)); /* MMC1_DAT2 */
MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)); /* MMC1_DAT3 */
MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M0)); /* MMC1_DAT4 */
MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M0)); /* MMC1_DAT5 */
MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M0)); /* MMC1_DAT6 */
MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M0)); /* MMC1_DAT7 */
/* WIRELESS LAN */
MUX_VAL(CP(MMC2_CLK), (IEN | PTD | DIS | M0)); /* MMC2_CLK */
MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M0)); /* MMC2_CMD */
MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M0)); /* MMC2_DAT0 */
MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M0)); /* MMC2_DAT1 */
MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M0)); /* MMC2_DAT2 */
MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M0)); /* MMC2_DAT3 */
/* MMC2_DIR_DAT0 */
MUX_VAL(CP(MMC2_DAT4), (IDIS | PTD | DIS | M1));
/* MMC2_DIR_DAT1 */
MUX_VAL(CP(MMC2_DAT5), (IDIS | PTD | DIS | M1));
/* MMC2_DIR_CMD */
MUX_VAL(CP(MMC2_DAT6), (IDIS | PTD | DIS | M1));
/* MMC2_CLKIN */
MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M1));
/* BLUETOOTH */
/* MCBSP3_DX */
MUX_VAL(CP(MCBSP3_DX), (IDIS | PTD | DIS | M0));
/* MCBSP3_DR */
MUX_VAL(CP(MCBSP3_DR), (IEN | PTD | DIS | M0));
/* MCBSP3_CLKX */
MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTD | DIS | M0));
/* MCBSP3_FSX */
MUX_VAL(CP(MCBSP3_FSX), (IEN | PTD | DIS | M0));
MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M0)); /* UART2_CTS */
MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)); /* UART2_RTS */
MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)); /* UART2_TX */
MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M0)); /* UART2_RX */
/* MODEM INTERFACE */
MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)); /* UART1_TX */
MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)); /* UART1_RTS */
MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0)); /* UART1_CTS */
MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)); /* UART1_RX */
/* SSI1_DAT_RX */
MUX_VAL(CP(MCBSP4_CLKX), (IEN | PTD | DIS | M1));
MUX_VAL(CP(MCBSP4_DR), (IEN | PTD | DIS | M1)); /* SSI1_FLAG_RX */
MUX_VAL(CP(MCBSP4_DX), (IEN | PTD | DIS | M1)); /* SSI1_RDY_RX */
MUX_VAL(CP(MCBSP4_FSX), (IEN | PTD | DIS | M1)); /* SSI1_WAKE */
/* MCBSP1_CLKR */
MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M0));
/* GPIO_157 - BT_WKUP */
MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | EN | M4));
/* MCBSP1_DX */
MUX_VAL(CP(MCBSP1_DX), (IDIS | PTD | DIS | M0));
MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M0)); /* MCBSP1_DR */
/* MCBSP_CLKS */
MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0));
/* MCBSP1_FSX */
MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | DIS | M0));
/* MCBSP1_CLKX */
MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTD | DIS | M0));
/* SERIAL INTERFACE */
MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)); /* I2C2_SCL */
MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)); /* I2C2_SDA */
MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)); /* I2C3_SCL */
MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)); /* I2C3_SDA */
MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)); /* I2C4_SCL */
MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)); /* I2C4_SDA */
MUX_VAL(CP(HDQ_SIO), (IEN | PTU | EN | M0)); /* HDQ_SIO */
/* MCSPI1_CLK */
MUX_VAL(CP(MCSPI1_CLK), (IEN | PTD | DIS | M0));
/* MCSPI1_SIMO */
MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTD | DIS | M0));
/* MCSPI1_SOMI */
MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | DIS | M0));
/* MCSPI1_CS0 */
MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M0));
/* MCSPI1_CS1 */
MUX_VAL(CP(MCSPI1_CS1), (IDIS | PTD | EN | M0));
/* GPIO_176-NOR_DPD */
MUX_VAL(CP(MCSPI1_CS2), (IDIS | PTD | DIS | M4));
/* MCSPI1_CS3 */
MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M0));
/* MCSPI2_CLK */
MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | DIS | M0));
/* MCSPI2_SIMO */
MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | DIS | M0));
/* MCSPI2_SOMI */
MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M0));
/* MCSPI2_CS0 */
MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M0));
/* MCSPI2_CS1 */
MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M0));
/* CONTROL AND DEBUG */
MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)); /* SYS_32K */
MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)); /* SYS_CLKREQ */
MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)); /* SYS_NIRQ */
MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)); /* GPIO_2 - PEN_IRQ */
MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)); /* GPIO_3 */
MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)); /* GPIO_4 - MMC1_WP */
MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)); /* GPIO_5 - LCD_ENVDD */
MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)); /* GPIO_6 - LAN_INTR0 */
MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)); /* GPIO_7 - MMC2_WP */
/* GPIO_8-LCD_ENBKL */
MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M4));
/* SYS_OFF_MODE */
MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0));
/* SYS_CLKOUT1 */
MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0));
MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M4)); /* GPIO_186 */
MUX_VAL(CP(JTAG_NTRST), (IEN | PTD | DIS | M0)); /* JTAG_NTRST */
MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)); /* JTAG_TCK */
MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)); /* JTAG_TMS */
MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)); /* JTAG_TDI */
MUX_VAL(CP(JTAG_EMU0), (IEN | PTD | DIS | M0)); /* JTAG_EMU0 */
MUX_VAL(CP(JTAG_EMU1), (IEN | PTD | DIS | M0)); /* JTAG_EMU1 */
/* HSUSB1_TLL_STP */
MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | EN | M0));
/* HSUSB1_TLL_CLK */
MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M0));
/* HSUSB1_TLL_DATA0 */
MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | DIS | M1));
/* MCSPI3_CS0 */
MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | DIS | M1));
/* HSUSB1_TLL_DATA2 */
MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | EN | M1));
/* HSUSB1_TLL_DATA7 */
MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | DIS | M1));
/* HSUSB1_TLL_DATA4 */
MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | DIS | M0));
/* HSUSB1_TLL_DATA5 */
MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | DIS | M0));
/* HSUSB1_TLL_DATA6 */
MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | DIS | M0));
/* HSUSB1_TLL_DATA3 */
MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | DIS | M0));
/* HSUSB1_TLL_DIR */
MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | DIS | M0));
/* HSUSB1_TLL_NXT */
MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | DIS | M0));
/* HSUSB2_TLL_CLK */
MUX_VAL(CP(ETK_D10_ES2), (IEN | PTD | DIS | M0));
/* HSUSB2_TLL_STP */
MUX_VAL(CP(ETK_D11_ES2), (IEN | PTD | DIS | M0));
/* HSUSB2_TLL_DIR */
MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | DIS | M0));
/* HSUSB2_TLL_NXT */
MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | DIS | M0));
/* HSUSB2_TLL_DATA0 */
MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | DIS | M0));
/* HSUSB2_TLL_DATA1 */
MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | DIS | M0));
/* DIE TO DIE */
MUX_VAL(CP(D2D_MCAD0), (IEN | PTD | EN | M0)); /* D2D_MCAD0 */
MUX_VAL(CP(D2D_MCAD1), (IEN | PTD | EN | M0)); /* D2D_MCAD1 */
MUX_VAL(CP(D2D_MCAD2), (IEN | PTD | EN | M0)); /* D2D_MCAD2 */
MUX_VAL(CP(D2D_MCAD3), (IEN | PTD | EN | M0)); /* D2D_MCAD3 */
MUX_VAL(CP(D2D_MCAD4), (IEN | PTD | EN | M0)); /* D2D_MCAD4 */
MUX_VAL(CP(D2D_MCAD5), (IEN | PTD | EN | M0)); /* D2D_MCAD5 */
MUX_VAL(CP(D2D_MCAD6), (IEN | PTD | EN | M0)); /* D2D_MCAD6 */
MUX_VAL(CP(D2D_MCAD7), (IEN | PTD | EN | M0)); /* D2D_MCAD7 */
MUX_VAL(CP(D2D_MCAD8), (IEN | PTD | EN | M0)); /* D2D_MCAD8 */
MUX_VAL(CP(D2D_MCAD9), (IEN | PTD | EN | M0)); /* D2D_MCAD9 */
MUX_VAL(CP(D2D_MCAD10), (IEN | PTD | EN | M0)); /* D2D_MCAD10 */
MUX_VAL(CP(D2D_MCAD11), (IEN | PTD | EN | M0)); /* D2D_MCAD11 */
MUX_VAL(CP(D2D_MCAD12), (IEN | PTD | EN | M0)); /* D2D_MCAD12 */
MUX_VAL(CP(D2D_MCAD13), (IEN | PTD | EN | M0)); /* D2D_MCAD13 */
MUX_VAL(CP(D2D_MCAD14), (IEN | PTD | EN | M0)); /* D2D_MCAD14 */
MUX_VAL(CP(D2D_MCAD15), (IEN | PTD | EN | M0)); /* D2D_MCAD15 */
MUX_VAL(CP(D2D_MCAD16), (IEN | PTD | EN | M0)); /* D2D_MCAD16 */
MUX_VAL(CP(D2D_MCAD17), (IEN | PTD | EN | M0)); /* D2D_MCAD17 */
MUX_VAL(CP(D2D_MCAD18), (IEN | PTD | EN | M0)); /* D2D_MCAD18 */
MUX_VAL(CP(D2D_MCAD19), (IEN | PTD | EN | M0)); /* D2D_MCAD19 */
MUX_VAL(CP(D2D_MCAD20), (IEN | PTD | EN | M0)); /* D2D_MCAD20 */
MUX_VAL(CP(D2D_MCAD21), (IEN | PTD | EN | M0)); /* D2D_MCAD21 */
MUX_VAL(CP(D2D_MCAD22), (IEN | PTD | EN | M0)); /* D2D_MCAD22 */
MUX_VAL(CP(D2D_MCAD23), (IEN | PTD | EN | M0)); /* D2D_MCAD23 */
MUX_VAL(CP(D2D_MCAD24), (IEN | PTD | EN | M0)); /* D2D_MCAD24 */
MUX_VAL(CP(D2D_MCAD25), (IEN | PTD | EN | M0)); /* D2D_MCAD25 */
MUX_VAL(CP(D2D_MCAD26), (IEN | PTD | EN | M0)); /* D2D_MCAD26 */
MUX_VAL(CP(D2D_MCAD27), (IEN | PTD | EN | M0)); /* D2D_MCAD27 */
MUX_VAL(CP(D2D_MCAD28), (IEN | PTD | EN | M0)); /* D2D_MCAD28 */
MUX_VAL(CP(D2D_MCAD29), (IEN | PTD | EN | M0)); /* D2D_MCAD29 */
MUX_VAL(CP(D2D_MCAD30), (IEN | PTD | EN | M0)); /* D2D_MCAD30 */
MUX_VAL(CP(D2D_MCAD31), (IEN | PTD | EN | M0)); /* D2D_MCAD31 */
MUX_VAL(CP(D2D_MCAD32), (IEN | PTD | EN | M0)); /* D2D_MCAD32 */
MUX_VAL(CP(D2D_MCAD33), (IEN | PTD | EN | M0)); /* D2D_MCAD33 */
MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)); /* D2D_MCAD34 */
MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)); /* D2D_MCAD35 */
MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)); /* D2D_MCAD36 */
/* D2D_CLK26MI */
MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0));
/* D2D_NRESPWRON */
MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0));
/* D2D_NRESWARM */
MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0));
/* D2D_ARM9NIRQ */
MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0));
/* D2D_UMA2P6FIQ */
MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0));
/* D2D_SPINT */
MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0));
/* D2D_FRINT */
MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0));
/* D2D_DMAREQ0 */
MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0));
/* D2D_DMAREQ1 */
MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0));
/* D2D_DMAREQ2 */
MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0));
/* D2D_DMAREQ3 */
MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0));
/* D2D_N3GTRST */
MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0));
/* D2D_N3GTDI */
MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0));
/* D2D_N3GTDO */
MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0));
/* D2D_N3GTMS */
MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0));
/* D2D_N3GTCK */
MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0));
/* D2D_N3GRTCK */
MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0));
/* D2D_MSTDBY */
MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0));
/* D2D_SWAKEUP */
MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0));
/* D2D_IDLEREQ */
MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0));
/* D2D_IDLEACK */
MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0));
/* D2D_MWRITE */
MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0));
/* D2D_SWRITE */
MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0));
/* D2D_MREAD */
MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0));
/* D2D_SREAD */
MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0));
/* D2D_MBUSFLAG */
MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0));
/* D2D_SBUSFLAG */
MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0));
/* SDRC_CKE0 */
MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0));
/* SDRC_CKE1 NOT USED */
MUX_VAL(CP(SDRC_CKE1), (IDIS | PTD | DIS | M7));
#endif /* CONFIG_MACH_OMAP_ADVANCED_MUX */
}
/*
* Routine: misc_init_r
* Description: Configure board specific parts
*/
int misc_init_r(void)
{
int err;
hw_boot_status status_bits;
unsigned short reg;
unsigned char val;
u8 data;
/*
* Configure drive strength for IO cells
*/
// already pulled up on board
//*(ulong *)(CONTROL_PROG_IO1) &= ~(PRG_I2C2_PULLUPRESX);
_board_revision();
printf("%s: initialize TPS65950 voltages\n", __func__);
twl4030_power_init();
printf("%s: select TPS65950 power-on HW transitions(PWRON and RTC)\n", __func__);
twl4030_set_px_transition(0x07, 0x49);
printf("%s: select 1-GHz MPU clock\n", __func__);
// 26 MHz * 500 / (12 + 1)
select_mpu_clock(500, 12);
lcd_config();
printf("%s: initialize all peripherals\n", __func__);
omap_request_gpio(27); // Enable periph 3V
omap_request_gpio(34); // reset USBHUB
omap_request_gpio(38); // disable CAN
omap_request_gpio(40); // reset modem
omap_request_gpio(41); // disable modem
omap_request_gpio(42); // reset CAP touch
omap_request_gpio(43); // off CAN
omap_request_gpio(61); // off modem
omap_request_gpio(64); // off GPS
omap_request_gpio(65); // off USB PHY
omap_request_gpio(94); // automotive out high
omap_request_gpio(95); // Wireless module VIO 1.8 V
omap_request_gpio(98); // DEVICE_EN
omap_request_gpio(111); // off USB PHY
omap_request_gpio(136); // Wireless module VDD 3.6 V
omap_request_gpio(137); // BT_EN
omap_request_gpio(138); // WL_EN
omap_request_gpio(144); // disable GPS
omap_request_gpio(145); // reset GPS
omap_request_gpio(146); // disable GPS boot
omap_request_gpio(161); // select microphone
omap_request_gpio(162); // serial transmitter force on
omap_request_gpio(175); // shutdown internal speaker amplifier
omap_request_gpio(176); // shutdown external speaker amplifier
omap_request_gpio(177); // enable external I2C device
omap_request_gpio(186); // PWR_ON generator
// Enable serial ports transceiver
omap_set_gpio_dataout(162, 1);
omap_set_gpio_direction(162, 0);
omap_set_gpio_dataout(98, 0);
omap_set_gpio_direction(98, 0);
omap_set_gpio_dataout(94, 0);
omap_set_gpio_direction(94, 0);
// enable peripheral 3.3 V
omap_set_gpio_dataout(27, 1);
omap_set_gpio_direction(27, 0);
// PWR_ON generator will off
omap_set_gpio_dataout(186, 1);
omap_set_gpio_direction(186, 0);
// disable BT
omap_set_gpio_dataout(137, 0);
omap_set_gpio_direction(137, 0);
// disable WL
omap_set_gpio_dataout(138, 0);
omap_set_gpio_direction(138, 0);
// wireless VIO 1.8V off
omap_set_gpio_dataout(95, 0);
omap_set_gpio_direction(95, 0);
// remove wireless VDD 3.6 V
omap_set_gpio_dataout(136, 0);
omap_set_gpio_direction(136, 0);
udelay(100000);
// Supply VDD and VIO to WiFi
omap_set_gpio_dataout(136, 1);
omap_set_gpio_dataout(95, 1);
udelay(100000);
// enable digital PADs
// MMC2
MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M0))
MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M0))
MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M0))
MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M0))
MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M0))
MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M0))
// UART2
MUX_VAL(CP(MCBSP3_FSX), (IEN | PTD | DIS | M1))
MUX_VAL(CP(MCBSP3_CLKX),(IDIS | PTD | DIS | M1))
MUX_VAL(CP(MCBSP3_DR), (IDIS | PTD | DIS | M1))
MUX_VAL(CP(MCBSP3_DX), (IEN | PTD | DIS | M1))
udelay(200000);
// pulse enable pins
// enable WL
omap_set_gpio_dataout(138, 1);
// enable BT
omap_set_gpio_dataout(137, 1);
udelay(200000);
// Valdimir: temporary enabled
// disable BT
//omap_set_gpio_dataout(137, 0);
// disable WL
//omap_set_gpio_dataout(138, 0);
omap_set_gpio_dataout(41, 0);
omap_set_gpio_direction(41, 0);
omap_set_gpio_dataout(40, 0);
omap_set_gpio_direction(40, 0);
omap_set_gpio_dataout(61, 0);
omap_set_gpio_direction(61, 0);
omap_set_gpio_dataout(144, 0);
omap_set_gpio_direction(144, 0);
omap_set_gpio_dataout(145, 0);
omap_set_gpio_direction(145, 0);
omap_set_gpio_dataout(146, 0);
omap_set_gpio_direction(146, 0);
omap_set_gpio_dataout(64, 0);
omap_set_gpio_direction(64, 0);
omap_set_gpio_dataout(38, 0);
omap_set_gpio_direction(38, 0);
omap_set_gpio_dataout(43, 0);
omap_set_gpio_direction(43, 0);
omap_set_gpio_dataout(42, 0);
omap_set_gpio_direction(42, 0);
omap_set_gpio_dataout(34, 0);
omap_set_gpio_direction(34, 0);
omap_set_gpio_dataout(111, 1);
omap_set_gpio_direction(111, 0);
omap_set_gpio_dataout(65, 0);
omap_set_gpio_direction(65, 0);
// enable internal speaker amplifier
omap_set_gpio_dataout(175, 0);
omap_set_gpio_direction(175, 0);
// shutdown external speaker amplifier
omap_set_gpio_dataout(176, 0);
omap_set_gpio_direction(176, 0);
// select internal microphone
omap_set_gpio_dataout(161, 0);
omap_set_gpio_direction(161, 0);
// External I2C Bus enable
omap_set_gpio_dataout(177, 0);
omap_set_gpio_direction(177, 0);
omap_free_gpio(27);
omap_free_gpio(34);
omap_free_gpio(38);
omap_free_gpio(40);
omap_free_gpio(41);
omap_free_gpio(42);
omap_free_gpio(43);
omap_free_gpio(61);
omap_free_gpio(64);
omap_free_gpio(65);
omap_free_gpio(94);
omap_free_gpio(95);
omap_free_gpio(98);
omap_free_gpio(111);
omap_free_gpio(136);
omap_free_gpio(137);
omap_free_gpio(138);
omap_free_gpio(144);
omap_free_gpio(145);
omap_free_gpio(146);
omap_free_gpio(161);
omap_free_gpio(162);
omap_free_gpio(175);
omap_free_gpio(177);
omap_free_gpio(186);
printf("%s: initialize all peripherals done\n", __func__);
twl4030_keypad_init();
// TODO: thermal shutdown and dynamic frequency scaling
// TPS659XX PHY 3.3 V recovery workaround
// Status bits read from companion chip and OMAP
twl4030_i2c_read_u8(TWL4030_CHIP_RTC, &data, TWL_BACKUP_REG_G); //TWL_BACKUP_REG_G - set in thermal driver
status_bits.thermal = data;
twl4030_i2c_read_u8(TWL4030_CHIP_RTC, &data, TWL_RTC_STATUS_REG); //TWL_RTC_STATUS_REG
status_bits.rtc_power_up = (data & TWL_RTC_STATUS_POWER_UP) ? 1 : 0;
status_bits.rtc_alarm = (data & TWL_RTC_STATUS_ALARM) ? 1 : 0;
status_bits.rtc_event = (data & (TWL_RTC_STATUS_ONE_D_EVENT | TWL_RTC_STATUS_ONE_H_EVENT |
TWL_RTC_STATUS_ONE_M_EVENT | TWL_RTC_STATUS_ONE_S_EVENT))? 1 : 0;
twl4030_i2c_read_u8(TWL4030_CHIP_RTC, &data, TWL_RTC_INTERRUPTS_REG); //TWL_RTC_INTERRUPTS_REG
status_bits.rtc_it_timer = (data & TWL_RTC_INTERRUPTS_IT_TIMER) ? 1 : 0;
status_bits.rtc_it_alarm = (data & TWL_RTC_INTERRUPTS_IT_ALARM) ? 1 : 0;
twl4030_i2c_read_u8(TWL4030_CHIP_RTC, &data, TWL_STS_BOOT); //TWL_STS_BOOT
status_bits.watchdog_reset = (data & (1<<5)) ? 1 : 0;//TWL_WATCHDOG_RESET
twl4030_i2c_read_u8(TWL4030_CHIP_RTC, &data, TWL_STS_HW_CONDITIONS); //TWL_STS_HW_CONDITIONS
status_bits.sts_pwon = (data & 1) ? 1 : 0; //STS_PWON
status_bits.sts_warmreset = (data & (1<<3)) ? 1 : 0; //STS_WARMRESET
twl4030_i2c_read_u8(TWL4030_CHIP_RTC, &data, TWL_PWR_ISR1); //TWL_PWR_ISR1
status_bits.isr_pwron = (data & STARTON_RTC) ? 1 : 0;
status_bits.isr_rtc_it = (data & STARTON_PWON) ? 1 : 0;
status_bits.prm_rstst = readl(OMAP_PRCM_PRM_RSTST);
char str[9];
sprintf(str, "%d", status_bits.bits);
setenv("hw_stat", str);
printf("Status bits [0x%x] [%s]\n", status_bits.bits, str);
printf("Board Revision A317 (%d)\n", board_revision);
sprintf(str, "%s", "A-317");
setenv("product", str);
dieid_num_r();
return 0;
}
void set_muxconf_regs(void)
{
/* SDRC */
MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0));
MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0));
MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0));
MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0));
MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0));
MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0));
MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0));
MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0));
MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0));
MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0));
MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0));
MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0));
MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0));
MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0));
MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0));
MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0));
MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0));
MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0));
MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0));
MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0));
MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0));
MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0));
MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0));
MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0));
MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0));
MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0));
MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0));
MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0));
MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0));
MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0));
MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0));
MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0));
MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0));
MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0));
MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0));
MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0));
MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0));
MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0));
MUX_VAL(CP(SDRC_CKE1), (IDIS | PTD | DIS | M7));
/* GPMC */
MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0));
MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0));
MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0));
MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0));
MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0));
MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0));
MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0));
MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0));
MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0));
MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0));
MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0));
MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0));
MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0));
MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0));
MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0));
MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0));
MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0));
MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0));
MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0));
MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0));
MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0));
MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0));
MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0));
MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0));
MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0));
MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0));
MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0));
/* SB-T35 Ethernet */
MUX_VAL(CP(GPMC_NCS4), (IEN | PTU | EN | M0));
/* DVI enable */
MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | DIS | M4));/*GPIO_54*/
/* DataImage backlight */
MUX_VAL(CP(GPMC_NCS7), (IDIS | PTU | DIS | M4));/*GPIO_58*/
/* SB-T35 SD/MMC WP GPIO59 */
MUX_VAL(CP(GPMC_CLK), (IEN | PTU | EN | M4)); /*GPIO_59*/
MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0));
MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0));
MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0));
MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0));
/* SB-T35 Audio Enable GPIO61 */
MUX_VAL(CP(GPMC_NBE1), (IDIS | PTU | EN | M4)); /*GPIO_61*/
MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0));
MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0));
/* SB-T35 Ethernet IRQ GPIO65 */
MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M4)); /*GPIO_65*/
/* UART3 Console */
MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0));
MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0));
/* RTC V3020 nCS GPIO163 */
MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTU | EN | M4)); /*GPIO_163*/
/* SB-T35 Ethernet nRESET GPIO164 */
MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTU | EN | M4)); /*GPIO_164*/
/* SB-T35 SD/MMC CD GPIO144 */
MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M4)); /*GPIO_144*/
/* WIFI nRESET GPIO145 */
MUX_VAL(CP(UART2_RTS), (IEN | PTD | EN | M4)); /*GPIO_145*/
/* USB1 PHY Reset GPIO 146 */
MUX_VAL(CP(UART2_TX), (IEN | PTD | EN | M4)); /*GPIO_146*/
/* USB2 PHY Reset GPIO 147 */
MUX_VAL(CP(UART2_RX), (IEN | PTD | EN | M4)); /*GPIO_147*/
/* MMC1 */
MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0));
MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0));
MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0));
MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0));
MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0));
MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0));
/* DSS */
MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0));
MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0));
MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0));
MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0));
MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0));
MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0));
MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0));
MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0));
MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0));
MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0));
MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0));
MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0));
MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0));
MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0));
MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0));
MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0));
MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0));
MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0));
MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0));
MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0));
MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0));
MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0));
MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0));
MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0));
MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0));
MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0));
MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0));
MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0));
/* I2C */
MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0));
MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0));
MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0));
MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0));
/* SB-T35 USB HUB Reset GPIO98 */
MUX_VAL(CP(CCDC_WEN), (IDIS | PTU | EN | M4)); /*GPIO_98*/
/* CM-T3517 USB HUB Reset GPIO152 */
MUX_VAL(CP(MCBSP4_CLKX), (IDIS | PTD | DIS | M4)); /*GPIO_152*/
/* RMII */
MUX_VAL(CP(RMII_MDIO_DATA), (IEN | PTU | EN | M0));
MUX_VAL(CP(RMII_MDIO_CLK), (M0));
MUX_VAL(CP(RMII_RXD0), (IEN | PTD | DIS | M0));
MUX_VAL(CP(RMII_RXD1), (IEN | PTD | DIS | M0));
MUX_VAL(CP(RMII_CRS_DV), (IEN | PTD | DIS | M0));
MUX_VAL(CP(RMII_RXER), (IEN | PTD | DIS | M0));
MUX_VAL(CP(RMII_TXD0), (IDIS | M0));
MUX_VAL(CP(RMII_TXD1), (IDIS | M0));
MUX_VAL(CP(RMII_TXEN), (IDIS | M0));
MUX_VAL(CP(RMII_50MHZ_CLK), (IEN | PTU | DIS | M0));
/* Green LED GPIO186 */
MUX_VAL(CP(SYS_CLKOUT2), (IDIS | PTU | DIS | M4)); /*GPIO_186*/
/* SPI */
MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M1)); /*MCSPI4_CLK*/
MUX_VAL(CP(MCBSP1_DX), (IEN | PTD | DIS | M1)); /*MCSPI4_SIMO*/
MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M1)); /*MCSPI4_SOMI*/
MUX_VAL(CP(MCBSP1_FSX), (IEN | PTU | EN | M1)); /*MCSPI4_CS0*/
/* LCD reset GPIO157 */
MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | DIS | M4)); /*GPIO_157*/
/* RTC V3020 CS Enable GPIO160 */
MUX_VAL(CP(MCBSP_CLKS), (IEN | PTD | EN | M4)); /*GPIO_160*/
/* SB-T35 LVDS Transmitter SHDN GPIO162 */
MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTU | DIS | M4)); /*GPIO_162*/
/* USB0 - mUSB */
MUX_VAL(CP(USB0_DRVBUS), (IEN | PTD | EN | M0));
/* USB1 EHCI */
MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT0*/
MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT1*/
MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT2*/
MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT3*/
MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT4*/
MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT5*/
MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT6*/
MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT7*/
MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DIR*/
MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_NXT*/
MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M3)); /*HSUSB1_CLK*/
MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | DIS | M3)); /*HSUSB1_STP*/
/* USB2 EHCI */
MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_DT0*/
MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_DT1*/
MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M3)); /*HSUSB2_DT2*/
MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M3)); /*HSUSB2_DT3*/
MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | EN | M3)); /*HSUSB2_DT4*/
MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | EN | M3)); /*HSUSB2_DT5*/
MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M3)); /*HSUSB2_DT6*/
MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | EN | M3)); /*HSUSB2_DT7*/
MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_DIR*/
MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_NXT*/
MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTD | DIS | M3)); /*HSUSB2_CLK*/
MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTU | DIS | M3)); /*HSUSB2_STP*/
/* SYS_BOOT */
MUX_VAL(CP(SYS_BOOT0), (IEN | PTU | DIS | M4)); /*GPIO_2*/
MUX_VAL(CP(SYS_BOOT1), (IEN | PTU | DIS | M4)); /*GPIO_3*/
MUX_VAL(CP(SYS_BOOT2), (IEN | PTU | DIS | M4)); /*GPIO_4*/
MUX_VAL(CP(SYS_BOOT3), (IEN | PTU | DIS | M4)); /*GPIO_5*/
MUX_VAL(CP(SYS_BOOT4), (IEN | PTU | DIS | M4)); /*GPIO_6*/
MUX_VAL(CP(SYS_BOOT5), (IEN | PTU | DIS | M4)); /*GPIO_7*/
}