status_t PHY_EnableLoopback(ENET_Type *base, uint32_t phyAddr, phy_loop_t mode, phy_speed_t speed, bool enable) { status_t result; uint32_t data = 0; /* Set the loop mode. */ if (enable) { if (mode == kPHY_LocalLoop) { if (speed == kPHY_Speed100M) { data = PHY_BCTL_SPEED_100M_MASK | PHY_BCTL_DUPLEX_MASK | PHY_BCTL_LOOP_MASK; } else { data = PHY_BCTL_DUPLEX_MASK | PHY_BCTL_LOOP_MASK; } return PHY_Write(base, phyAddr, PHY_BASICCONTROL_REG, data); } else { /* First read the current status in control register. */ result = PHY_Read(base, phyAddr, PHY_CONTROL2_REG, &data); if (result == kStatus_Success) { return PHY_Write(base, phyAddr, PHY_CONTROL2_REG, (data | PHY_CTL2_REMOTELOOP_MASK)); } } } else { /* Disable the loop mode. */ if (mode == kPHY_LocalLoop) { /* First read the current status in control register. */ result = PHY_Read(base, phyAddr, PHY_BASICCONTROL_REG, &data); if (result == kStatus_Success) { data &= ~PHY_BCTL_LOOP_MASK; return PHY_Write(base, phyAddr, PHY_BASICCONTROL_REG, (data | PHY_BCTL_RESTART_AUTONEG_MASK)); } } else { /* First read the current status in control one register. */ result = PHY_Read(base, phyAddr, PHY_CONTROL2_REG, &data); if (result == kStatus_Success) { return PHY_Write(base, phyAddr, PHY_CONTROL2_REG, (data & ~PHY_CTL2_REMOTELOOP_MASK)); } } } return result; }
status_t PHY_EnableLoopback(ENET_Type *base, uint32_t phyAddr, phy_loop_t mode, bool enable) { status_t result; uint32_t data = 0; /* Set the loop mode. */ if (enable) { if (mode == kPHY_LocalLoop) { /* First read the current status in control register. */ result = PHY_Read(base, phyAddr, PHY_BASICCONTROL_REG, &data); if (result == kStatus_Success) { return PHY_Write(base, phyAddr, PHY_BASICCONTROL_REG, (data | PHY_BCTL_LOOP_MASK)); } } else { /* First read the current status in control register. */ result = PHY_Read(base, phyAddr, PHY_CONTROL2_REG, &data); if (result == kStatus_Success) { return PHY_Write(base, phyAddr, PHY_CONTROL2_REG, (data | PHY_CTL2_REMOTELOOP_MASK)); } } } else { /* Disable the loop mode. */ if (mode == kPHY_LocalLoop) { /* First read the current status in the basic control register. */ result = PHY_Read(base, phyAddr, PHY_BASICCONTROL_REG, &data); if (result == kStatus_Success) { return PHY_Write(base, phyAddr, PHY_BASICCONTROL_REG, (data & ~PHY_BCTL_LOOP_MASK)); } } else { /* First read the current status in control one register. */ result = PHY_Read(base, phyAddr, PHY_CONTROL2_REG, &data); if (result == kStatus_Success) { return PHY_Write(base, phyAddr, PHY_CONTROL2_REG, (data & ~PHY_CTL2_REMOTELOOP_MASK)); } } } return result; }
status_t PHY_Init(ENET_Type *base, uint32_t phyAddr, uint32_t srcClock_Hz) { uint32_t counter = PHY_TIMEOUT_COUNT; uint32_t idReg = 0; status_t result = kStatus_Success; uint32_t instance = ENET_GetInstance(base); #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) /* Set SMI first. */ CLOCK_EnableClock(s_enetClock[instance]); #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ ENET_SetSMI(base, srcClock_Hz, false); /* Initialization after PHY stars to work. */ while ((idReg != PHY_CONTROL_ID1) && (counter != 0)) { PHY_Read(base, phyAddr, PHY_ID1_REG, &idReg); counter --; } if (!counter) { return kStatus_Fail; } /* Reset PHY. */ result = PHY_Write(base, phyAddr, PHY_BASICCONTROL_REG, PHY_BCTL_RESET_MASK); if (result == kStatus_Success) { #if defined(FSL_FEATURE_PHYKSZ8081_USE_RMII50M_MODE) uint32_t data = 0; result = PHY_Read(base, phyAddr, PHY_CONTROL2_REG, &data); if ( result != kStatus_Success) { return result; } result = PHY_Write(base, phyAddr, PHY_CONTROL2_REG, (data | PHY_CTL2_REFCLK_SELECT_MASK)); if (result != kStatus_Success) { return result; } #endif /* FSL_FEATURE_PHYKSZ8081_USE_RMII50M_MODE */ } return result; }
status_t PHY_AutoNegotiation(ENET_Type *base, uint32_t phyAddr) { status_t result = kStatus_Success; uint32_t bssReg; uint32_t counter = PHY_TIMEOUT_COUNT; uint32_t timeDelay; uint32_t ctlReg = 0; /* Set the negotiation. */ result = PHY_Write(base, phyAddr, PHY_AUTONEG_ADVERTISE_REG, (PHY_100BASETX_FULLDUPLEX_MASK | PHY_100BASETX_HALFDUPLEX_MASK | PHY_10BASETX_FULLDUPLEX_MASK | PHY_10BASETX_HALFDUPLEX_MASK | 0x1U)); if (result == kStatus_Success) { result = PHY_Write(base, phyAddr, PHY_BASICCONTROL_REG, (PHY_BCTL_AUTONEG_MASK | PHY_BCTL_RESTART_AUTONEG_MASK)); if (result == kStatus_Success) { /* Check auto negotiation complete. */ while (counter --) { result = PHY_Read(base, phyAddr, PHY_BASICSTATUS_REG, &bssReg); if ( result == kStatus_Success) { PHY_Read(base, phyAddr, PHY_CONTROL1_REG, &ctlReg); if (((bssReg & PHY_BSTATUS_AUTONEGCOMP_MASK) != 0) && (ctlReg & PHY_LINK_READY_MASK)) { /* Wait a moment for Phy status stable. */ for (timeDelay = 0; timeDelay < PHY_TIMEOUT_COUNT; timeDelay ++) { __ASM("nop"); } break; } } if (!counter) { return kStatus_PHY_AutoNegotiateFail; } } } } return result; }
status_t PHY_GetLinkSpeedDuplex(ENET_Type *base, uint32_t phyAddr, phy_speed_t *speed, phy_duplex_t *duplex) { assert(duplex); status_t result = kStatus_Success; uint32_t data, ctlReg; /* Read the control two register. */ #if defined(BOARD_RT1050_FIRE) || defined(BOARD_RT1050_ATK) result = PHY_Read(base, phyAddr, PHY_CONTROL2_REG, &ctlReg); #endif #if defined(BOARD_RT1050_EVK) || defined(BOARD_RT1050_SeeedStudio) result = PHY_Read(base, phyAddr, PHY_CONTROL1_REG, &ctlReg); #endif if (result == kStatus_Success) { data = ctlReg & PHY_CTL1_SPEEDUPLX_MASK; if ((PHY_CTL1_10FULLDUPLEX_MASK == data) || (PHY_CTL1_100FULLDUPLEX_MASK == data)) { /* Full duplex. */ *duplex = kPHY_FullDuplex; } else { /* Half duplex. */ *duplex = kPHY_HalfDuplex; } data = ctlReg & PHY_CTL1_SPEEDUPLX_MASK; if ((PHY_CTL1_100HALFDUPLEX_MASK == data) || (PHY_CTL1_100FULLDUPLEX_MASK == data)) { /* 100M speed. */ *speed = kPHY_Speed100M; } else { /* 10M speed. */ *speed = kPHY_Speed10M; } } return result; }
status_t PHY_Init(ENET_Type *base, uint32_t phyAddr, uint32_t srcClock_Hz) { uint32_t bssReg; uint32_t counter = PHY_TIMEOUT_COUNT; status_t result = kStatus_Success; uint32_t instance = ENET_GetInstance(base); /* Set SMI first. */ CLOCK_EnableClock(s_enetClock[instance]); ENET_SetSMI(base, srcClock_Hz, false); /* Reset PHY. */ result = PHY_Write(base, phyAddr, PHY_BASICCONTROL_REG, PHY_BCTL_RESET_MASK); if (result == kStatus_Success) { /* Set the negotiation. */ result = PHY_Write(base, phyAddr, PHY_AUTONEG_ADVERTISE_REG, (PHY_100BASETX_FULLDUPLEX_MASK | PHY_100BASETX_HALFDUPLEX_MASK | PHY_10BASETX_FULLDUPLEX_MASK | PHY_10BASETX_HALFDUPLEX_MASK | 0x1U)); if (result == kStatus_Success) { result = PHY_Write(base, phyAddr, PHY_BASICCONTROL_REG, (PHY_BCTL_AUTONEG_MASK | PHY_BCTL_RESTART_AUTONEG_MASK)); if (result == kStatus_Success) { /* Check auto negotiation complete. */ while (counter --) { result = PHY_Read(base, phyAddr, PHY_BASICSTATUS_REG, &bssReg); if ( result == kStatus_Success) { if ((bssReg & PHY_BSTATUS_AUTONEGCOMP_MASK) != 0) { break; } } if (!counter) { return kStatus_PHY_AutoNegotiateFail; } } } } } return result; }
status_t PHY_GetLinkStatus(ENET_Type *base, uint32_t phyAddr, bool *status) { assert(status); status_t result = kStatus_Success; uint32_t data; /* Read the basic status register. */ result = PHY_Read(base, phyAddr, PHY_BASICSTATUS_REG, &data); if (result == kStatus_Success) { if (!(PHY_BSTATUS_LINKSTATUS_MASK & data)) { /* link down. */ *status = false; } else { /* link up. */ *status = true; } } return result; }
status_t PHY_Init(ENET_Type *base, uint32_t phyAddr, uint32_t srcClock_Hz) { uint32_t bssReg; uint32_t counter = PHY_TIMEOUT_COUNT; uint32_t idReg = 0; status_t result = kStatus_Success; uint32_t instance = ENET_GetInstance(base); #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) /* Set SMI first. */ CLOCK_EnableClock(s_enetClock[instance]); #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ ENET_SetSMI(base, srcClock_Hz, false); /* Initialization after PHY stars to work. */ while ((idReg != PHY_CONTROL_ID1) && (counter != 0)) { PHY_Read(base, phyAddr, PHY_ID1_REG, &idReg); counter --; } if (!counter) { return kStatus_Fail; } /* Reset PHY. */ counter = 6; result = PHY_Write(base, phyAddr, PHY_BASICCONTROL_REG, PHY_BCTL_RESET_MASK); if (result == kStatus_Success) { #if defined(BOARD_RT1050_FIRE) for (uint32_t i = 0x10000; i > 0; i--) { result = PHY_Read(base, phyAddr, PHY_BASICCONTROL_REG, &bssReg); if (!(bssReg & PHY_BCTL_POWER_DOWN_MASK)) { break; } } #endif #if defined(BOARD_RT1050_ATK) rt_thread_delay(RT_TICK_PER_SECOND); #endif #if defined(FSL_FEATURE_PHYKSZ8081_USE_RMII50M_MODE) uint32_t data = 0; result = PHY_Read(base, phyAddr, PHY_CONTROL2_REG, &data); if ( result != kStatus_Success) { return result; } result = PHY_Write(base, phyAddr, PHY_CONTROL2_REG, (data | PHY_CTL2_REFCLK_SELECT_MASK)); if (result != kStatus_Success) { return result; } #endif /* FSL_FEATURE_PHYKSZ8081_USE_RMII50M_MODE */ /* Set the negotiation. */ result = PHY_Write(base, phyAddr, PHY_AUTONEG_ADVERTISE_REG, (PHY_100BASETX_FULLDUPLEX_MASK | PHY_100BASETX_HALFDUPLEX_MASK | PHY_10BASETX_FULLDUPLEX_MASK | PHY_10BASETX_HALFDUPLEX_MASK | 0x1U)); if (result == kStatus_Success) { result = PHY_Write(base, phyAddr, PHY_BASICCONTROL_REG, (PHY_BCTL_AUTONEG_MASK | PHY_BCTL_RESTART_AUTONEG_MASK)); if (result == kStatus_Success) { /* Check auto negotiation complete. */ while (counter --) { result = PHY_Read(base, phyAddr, PHY_BASICSTATUS_REG, &bssReg); if ( result == kStatus_Success) { #if defined(BOARD_RT1050_FIRE) || defined(BOARD_RT1050_ATK) if (((bssReg & PHY_BSTATUS_AUTONEGCOMP_MASK) != 0)) #else uint32_t ctlReg = 0; PHY_Read(base, phyAddr, PHY_CONTROL1_REG, &ctlReg); if (((bssReg & PHY_BSTATUS_AUTONEGCOMP_MASK) != 0) && (ctlReg & PHY_LINK_READY_MASK)) #endif { rt_kprintf("auto negotiation complete success\n"); break; } else { /* Wait a moment for Phy status stable. */ __ASM("nop"); } } rt_kprintf("[PHY] wait autonegotiation complete...\n"); rt_thread_delay(RT_TICK_PER_SECOND); if (!counter) { return kStatus_PHY_AutoNegotiateFail; } } } } } return result; }