/**
* Initialize engine data
*
*
*
* @param[in] ComplexDescriptor Pointer to user defined complex descriptor
* @param[in,out] Wrapper Pointer to wrapper config descriptor
* @param[in] Pcie Pointer to global PCIe configuration
*/
VOID
PcieMapInitializeEngineData (
IN PCIe_COMPLEX_DESCRIPTOR *ComplexDescriptor,
IN OUT PCIe_WRAPPER_CONFIG *Wrapper,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
PCIe_ENGINE_CONFIG *EngineList;
PCIe_ENGINE_DESCRIPTOR *EngineDescriptor;
EngineList = PcieConfigGetChildEngine (Wrapper);
while (EngineList != NULL) {
if (PcieLibIsEngineAllocated (EngineList)) {
if (EngineList->Scratch != 0xFF) {
EngineDescriptor = PcieInputParserGetEngineDescriptor (ComplexDescriptor, EngineList->Scratch);
LibAmdMemCopy (&EngineList->EngineData, &EngineDescriptor->EngineData, sizeof (EngineDescriptor->EngineData), GnbLibGetHeader (Pcie));
if (PcieLibIsDdiEngine (EngineList)) {
LibAmdMemCopy (&EngineList->Type.Ddi, &((PCIe_DDI_DESCRIPTOR*) EngineDescriptor)->Ddi, sizeof (PCIe_DDI_DATA), GnbLibGetHeader (Pcie));
EngineList->Type.Ddi.DisplayPriorityIndex = (UINT8) EngineList->Scratch;
} else if (PcieLibIsPcieEngine (EngineList)) {
LibAmdMemCopy (&EngineList->Type.Port, &((PCIe_PORT_DESCRIPTOR*) EngineDescriptor)->Port, sizeof (PCIe_PORT_DATA), GnbLibGetHeader (Pcie));
}
}
}
EngineList = PcieLibGetNextDescriptor (EngineList);
}
}
/**
* Helper function to dump input configuration to debug out
*
*
* @param[in] ComplexDescriptor Pointer to user defined complex descriptor
*/
VOID
PcieUserConfigConfigDump (
IN PCIe_COMPLEX_DESCRIPTOR *ComplexDescriptor
)
{
PCIe_ENGINE_DESCRIPTOR *EngineDescriptor;
PCIe_COMPLEX_DESCRIPTOR *CurrentComplexDescriptor;
UINTN ComplexIndex;
UINTN Index;
UINTN NumberOfEngines;
UINTN NumberOfComplexes;
IDS_HDT_CONSOLE (PCIE_MISC, "<---------- PCIe User Config Start------------->\n");
NumberOfComplexes = PcieInputParserGetNumberOfComplexes (ComplexDescriptor);
for (ComplexIndex = 0; ComplexIndex < NumberOfComplexes; ++ComplexIndex) {
CurrentComplexDescriptor = PcieInputParserGetComplexDescriptor (ComplexDescriptor, ComplexIndex);
NumberOfEngines = PcieInputParserGetNumberOfEngines (CurrentComplexDescriptor);
IDS_HDT_CONSOLE (PCIE_MISC, " ComplexDescriptor SocketId - %d\n NumberOfEngines - %d\n",
ComplexDescriptor->SocketId,
NumberOfEngines
);
for (Index = 0; Index < NumberOfEngines; Index++) {
EngineDescriptor = PcieInputParserGetEngineDescriptor (ComplexDescriptor, Index);
PcieUserDescriptorConfigDump (EngineDescriptor);
}
}
IDS_HDT_CONSOLE (PCIE_MISC, "<---------- PCIe User Config End-------------->\n");
}
/**
* Configure engine list to support lane allocation according to configuration ID.
*
*
*
* @param[in] EngineType Engine type
* @param[in] ComplexDescriptor Pointer to used define complex descriptor
* @param[in] Wrapper Pointer to wrapper config descriptor
* @retval AGESA_SUCCESS Topology successfully mapped
* @retval AGESA_ERROR Topology can not be mapped
*/
STATIC AGESA_STATUS
PcieEnginesToWrapper (
IN PCIE_ENGINE_TYPE EngineType,
IN PCIe_COMPLEX_DESCRIPTOR *ComplexDescriptor,
IN PCIe_WRAPPER_CONFIG *Wrapper
)
{
AGESA_STATUS Status;
PCIe_ENGINE_CONFIG *EngineList;
PCIe_ENGINE_DESCRIPTOR *EngineDescriptor;
UINT8 ConfigurationId;
UINT8 Allocations;
UINTN Index;
UINTN NumberOfDescriptors;
ConfigurationId = 0;
Allocations = 0;
IDS_HDT_CONSOLE (GNB_TRACE, "PcieEnginesToWrapper Enter\n");
NumberOfDescriptors = PcieInputParserGetNumberOfEngines (ComplexDescriptor);
do {
Status = PcieFmConfigureEnginesLaneAllocation (Wrapper, EngineType, ConfigurationId++);
if (Status == AGESA_SUCCESS) {
Allocations = 0;
for (Index = 0; Index < NumberOfDescriptors; Index++) {
EngineDescriptor = PcieInputParserGetEngineDescriptor (ComplexDescriptor, Index);
if (EngineDescriptor->EngineData.EngineType == EngineType) {
// Step 1, belongs to wrapper check.
if (PcieCheckDescriptorMapsToWrapper (EngineDescriptor, Wrapper)) {
++Allocations;
EngineList = PcieConfigGetChildEngine (Wrapper);
while (EngineList != NULL) {
if (!PcieLibIsEngineAllocated (EngineList)) {
// Step 2.user descriptor less or equal to link width of engine
if (PcieCheckLanesMatch (EngineDescriptor, EngineList)) {
// Step 3, Check if link width is correct.x1, x2, x4, x8, x16.
if (!PcieIsDescriptorLinkWidthValid (EngineDescriptor)) {
PcieConfigDisableEngine (EngineList);
return AGESA_ERROR;
}
if (EngineDescriptor->EngineData.EngineType == PciePortEngine) {
// Step 4, Family specifc, port device number match engine device
if (PcieCheckPortPciDeviceMapping ((PCIe_PORT_DESCRIPTOR*) EngineDescriptor, EngineList)) {
//Step 5, Family specifc, lanes can be muxed.
if (PcieFmCheckPortPcieLaneCanBeMuxed ((PCIe_PORT_DESCRIPTOR*) EngineDescriptor, EngineList)) {
PcieAllocateEngine ((UINT8) Index, EngineList);
--Allocations;
break;
}
}
} else {
PcieAllocateEngine ((UINT8) Index, EngineList);
--Allocations;
break;
}
}
} //end if PcieLibIsEngineAllocated
EngineList = PcieLibGetNextDescriptor (EngineList);
}
} //end if PcieCheckDescriptorMapsToWrapper
} // end if EngineType
} //end for
}
} while (Status == AGESA_SUCCESS && Allocations != 0);
IDS_HDT_CONSOLE (GNB_TRACE, "PcieEnginesToWrapper Exit [%x]\n", Status);
return Status;
}
