/**
* @brief Receive data in blocking mode. Must be invoked when RXBR has been set.
* @param hcec: CEC handle
* @param pData: pointer to received data buffer.
* @param Timeout: Timeout duration.
* Note that the received data size is not known beforehand, the latter is known
* when the reception is complete and is stored in hcec->RxXferSize.
* hcec->RxXferSize is the sum of opcodes + operands (0 to 14 operands max).
* If only a header is received, hcec->RxXferSize = 0
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CEC_Receive(CEC_HandleTypeDef *hcec, uint8_t *pData, uint32_t Timeout)
{
uint32_t temp;
uint32_t tickstart = 0;
if (hcec->State == HAL_CEC_STATE_READY)
{
hcec->ErrorCode = HAL_CEC_ERROR_NONE;
if (pData == NULL )
{
hcec->State = HAL_CEC_STATE_ERROR;
return HAL_ERROR;
}
hcec->RxXferSize = 0;
/* Process Locked */
__HAL_LOCK(hcec);
/* Rx loop until CEC_ISR_RXEND is set */
while (HAL_IS_BIT_CLR(hcec->Instance->ISR, CEC_FLAG_RXEND))
{
tickstart = HAL_GetTick();
/* Wait for next byte to be received */
while (HAL_IS_BIT_CLR(hcec->Instance->ISR, CEC_FLAG_RXBR))
{
if(Timeout != HAL_MAX_DELAY)
{
if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
{
hcec->State = HAL_CEC_STATE_TIMEOUT;
__HAL_UNLOCK(hcec);
return HAL_TIMEOUT;
}
}
/* any error so far ?
* has Rx Missing Acknowledge occurred ?
* has Rx Long Bit Period error occurred ?
* has Rx Short Bit Period error occurred ?
* has Rx Bit Rising error occurred ?
* has Rx Overrun error occurred ? */
temp = (uint32_t) (hcec->Instance->ISR);
if ((temp & (CEC_FLAG_RXACKE|CEC_FLAG_LBPE|CEC_FLAG_SBPE|CEC_FLAG_BRE|CEC_FLAG_RXOVR)) != 0)
{
/* copy ISR for error handling purposes */
hcec->ErrorCode = temp;
/* clear all error flags by default */
__HAL_CEC_CLEAR_FLAG(hcec,(CEC_FLAG_RXACKE|CEC_FLAG_LBPE|CEC_FLAG_SBPE|CEC_FLAG_BRE|CEC_FLAG_RXOVR));
hcec->State = HAL_CEC_STATE_ERROR;
__HAL_UNLOCK(hcec);
return HAL_ERROR;
}
} /* while (HAL_IS_BIT_CLR(hcec->Instance->ISR, CEC_ISR_RXBR)) */
/* read received data */
*pData++ = hcec->Instance->RXDR;
temp = (uint32_t) (hcec->Instance->ISR);
/* end of message ? */
if ((temp & CEC_ISR_RXEND) != 0)
{
assert_param(IS_CEC_MSGSIZE(hcec->RxXferSize));
__HAL_CEC_CLEAR_FLAG(hcec,CEC_FLAG_RXEND);
hcec->State = HAL_CEC_STATE_READY;
__HAL_UNLOCK(hcec);
return HAL_OK;
}
/* clear Rx-Byte Received flag */
__HAL_CEC_CLEAR_FLAG(hcec,CEC_FLAG_RXBR);
/* increment payload byte counter */
hcec->RxXferSize++;
} /* while (HAL_IS_BIT_CLR(hcec->Instance->ISR, CEC_ISR_RXEND)) */
/* if the instructions below are executed, it means RXEND was set when RXBR was
* set for the first time:
* the code within the "while (HAL_IS_BIT_CLR(hcec->Instance->ISR, CEC_ISR_RXEND))"
* loop has not been executed and this means a single byte has been sent */
*pData++ = hcec->Instance->RXDR;
/* only one header is received: RxXferSize is set to 0 (no operand, no opcode) */
hcec->RxXferSize = 0;
__HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RXEND);
hcec->State = HAL_CEC_STATE_READY;
__HAL_UNLOCK(hcec);
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Open and configure an endpoint
* @param hpcd: PCD handle
* @param ep_addr: endpoint address
* @param ep_mps: endpoint max packert size
* @param ep_type: endpoint type
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type)
{
HAL_StatusTypeDef ret = HAL_OK;
PCD_EPTypeDef *ep;
if ((ep_addr & 0x80) == 0x80)
{
ep = &hpcd->IN_ep[ep_addr & 0x7F];
}
else
{
ep = &hpcd->OUT_ep[ep_addr & 0x7F];
}
ep->num = ep_addr & 0x7F;
ep->is_in = (0x80 & ep_addr) != 0;
ep->maxpacket = ep_mps;
ep->type = ep_type;
__HAL_LOCK(hpcd);
/* initialize Endpoint */
switch (ep->type)
{
case PCD_EP_TYPE_CTRL:
PCD_SET_EPTYPE(hpcd->Instance, ep->num, USB_EP_CONTROL);
break;
case PCD_EP_TYPE_BULK:
PCD_SET_EPTYPE(hpcd->Instance, ep->num, USB_EP_BULK);
break;
case PCD_EP_TYPE_INTR:
PCD_SET_EPTYPE(hpcd->Instance, ep->num, USB_EP_INTERRUPT);
break;
case PCD_EP_TYPE_ISOC:
PCD_SET_EPTYPE(hpcd->Instance, ep->num, USB_EP_ISOCHRONOUS);
break;
}
PCD_SET_EP_ADDRESS(hpcd->Instance, ep->num, ep->num);
if (ep->doublebuffer == 0)
{
if (ep->is_in)
{
/*Set the endpoint Transmit buffer address */
PCD_SET_EP_TX_ADDRESS(hpcd->Instance, ep->num, ep->pmaadress);
PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num);
/* Configure NAK status for the Endpoint*/
PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_NAK);
}
else
{
/*Set the endpoint Receive buffer address */
PCD_SET_EP_RX_ADDRESS(hpcd->Instance, ep->num, ep->pmaadress);
/*Set the endpoint Receive buffer counter*/
PCD_SET_EP_RX_CNT(hpcd->Instance, ep->num, ep->maxpacket);
PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num);
/* Configure VALID status for the Endpoint*/
PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_VALID);
}
}
/*Double Buffer*/
else
{
/*Set the endpoint as double buffered*/
PCD_SET_EP_DBUF(hpcd->Instance, ep->num);
/*Set buffer address for double buffered mode*/
PCD_SET_EP_DBUF_ADDR(hpcd->Instance, ep->num,ep->pmaaddr0, ep->pmaaddr1);
if (ep->is_in==0)
{
/* Clear the data toggle bits for the endpoint IN/OUT*/
PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num);
PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num);
/* Reset value of the data toggle bits for the endpoint out*/
PCD_TX_DTOG(hpcd->Instance, ep->num);
PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_VALID);
PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_DIS);
}
else
{
/* Clear the data toggle bits for the endpoint IN/OUT*/
PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num);
PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num);
PCD_RX_DTOG(hpcd->Instance, ep->num);
/* Configure DISABLE status for the Endpoint*/
PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_DIS);
PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_DIS);
}
}
__HAL_UNLOCK(hpcd);
return ret;
}
/**
* @brief Initiates and transmits a CAN frame message.
* @param hcan: pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @param Timeout: Specify Timeout value
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout)
{
uint32_t transmitmailbox = 5;
uint32_t tickstart = 0;
/* Check the parameters */
assert_param(IS_CAN_IDTYPE(hcan->pTxMsg->IDE));
assert_param(IS_CAN_RTR(hcan->pTxMsg->RTR));
assert_param(IS_CAN_DLC(hcan->pTxMsg->DLC));
/* Process locked */
__HAL_LOCK(hcan);
if(hcan->State == HAL_CAN_STATE_BUSY_RX)
{
/* Change CAN state */
hcan->State = HAL_CAN_STATE_BUSY_TX_RX;
}
else
{
/* Change CAN state */
hcan->State = HAL_CAN_STATE_BUSY_TX;
}
/* Select one empty transmit mailbox */
if ((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0)
{
transmitmailbox = 0;
}
else if ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1)
{
transmitmailbox = 1;
}
else if ((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2)
{
transmitmailbox = 2;
}
else
{
transmitmailbox = CAN_TXSTATUS_NOMAILBOX;
}
if (transmitmailbox != CAN_TXSTATUS_NOMAILBOX)
{
/* Set up the Id */
hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ;
if (hcan->pTxMsg->IDE == CAN_ID_STD)
{
assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId));
hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << 21) | \
hcan->pTxMsg->RTR);
}
else
{
assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId));
hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << 3) | \
hcan->pTxMsg->IDE | \
hcan->pTxMsg->RTR);
}
/* Set up the DLC */
hcan->pTxMsg->DLC &= (uint8_t)0x0000000F;
hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= (uint32_t)0xFFFFFFF0;
hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC;
/* Set up the data field */
hcan->Instance->sTxMailBox[transmitmailbox].TDLR = (((uint32_t)hcan->pTxMsg->Data[3] << 24) |
((uint32_t)hcan->pTxMsg->Data[2] << 16) |
((uint32_t)hcan->pTxMsg->Data[1] << 8) |
((uint32_t)hcan->pTxMsg->Data[0]));
hcan->Instance->sTxMailBox[transmitmailbox].TDHR = (((uint32_t)hcan->pTxMsg->Data[7] << 24) |
((uint32_t)hcan->pTxMsg->Data[6] << 16) |
((uint32_t)hcan->pTxMsg->Data[5] << 8) |
((uint32_t)hcan->pTxMsg->Data[4]));
/* Request transmission */
hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ;
/* Get tick */
tickstart = HAL_GetTick();
/* Check End of transmission flag */
while(!(__HAL_CAN_TRANSMIT_STATUS(hcan, transmitmailbox)))
{
/* Check for the Timeout */
if(Timeout != HAL_MAX_DELAY)
{
if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
{
hcan->State = HAL_CAN_STATE_TIMEOUT;
/* Process unlocked */
__HAL_UNLOCK(hcan);
return HAL_TIMEOUT;
}
}
}
if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX)
{
/* Change CAN state */
hcan->State = HAL_CAN_STATE_BUSY_RX;
/* Process unlocked */
__HAL_UNLOCK(hcan);
}
else
{
/* Change CAN state */
hcan->State = HAL_CAN_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hcan);
}
/* Return function status */
return HAL_OK;
}
else
{
/* Change CAN state */
hcan->State = HAL_CAN_STATE_ERROR;
/* Return function status */
return HAL_ERROR;
}
}
/**
* @brief Configures for the selected ADC injected channel its corresponding
* rank in the sequencer and its sample time.
* @param hadc: pointer to a ADC_HandleTypeDef structure that contains
* the configuration information for the specified ADC.
* @param sConfigInjected: ADC configuration structure for injected channel.
* @retval None
*/
HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_InjectionConfTypeDef* sConfigInjected)
{
#ifdef USE_FULL_ASSERT
uint32_t tmp = 0;
#endif /* USE_FULL_ASSERT */
/* Check the parameters */
assert_param(IS_ADC_CHANNEL(sConfigInjected->InjectedChannel));
assert_param(IS_ADC_INJECTED_RANK(sConfigInjected->InjectedRank));
assert_param(IS_ADC_SAMPLE_TIME(sConfigInjected->InjectedSamplingTime));
assert_param(IS_ADC_EXT_INJEC_TRIG(sConfigInjected->ExternalTrigInjecConv));
assert_param(IS_ADC_INJECTED_LENGTH(sConfigInjected->InjectedNbrOfConversion));
assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->AutoInjectedConv));
assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjectedDiscontinuousConvMode));
#ifdef USE_FULL_ASSERT
tmp = ADC_GET_RESOLUTION(hadc);
assert_param(IS_ADC_RANGE(tmp, sConfigInjected->InjectedOffset));
#endif /* USE_FULL_ASSERT */
if(sConfigInjected->ExternalTrigInjecConvEdge != ADC_INJECTED_SOFTWARE_START)
{
assert_param(IS_ADC_EXT_INJEC_TRIG_EDGE(sConfigInjected->ExternalTrigInjecConvEdge));
}
/* Process locked */
__HAL_LOCK(hadc);
/* if ADC_Channel_10 ... ADC_Channel_18 is selected */
if (sConfigInjected->InjectedChannel > ADC_CHANNEL_9)
{
/* Clear the old sample time */
hadc->Instance->SMPR1 &= ~ADC_SMPR1(ADC_SMPR1_SMP10, sConfigInjected->InjectedChannel);
/* Set the new sample time */
hadc->Instance->SMPR1 |= ADC_SMPR1(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel);
}
else /* ADC_Channel include in ADC_Channel_[0..9] */
{
/* Clear the old sample time */
hadc->Instance->SMPR2 &= ~ADC_SMPR2(ADC_SMPR2_SMP0, sConfigInjected->InjectedChannel);
/* Set the new sample time */
hadc->Instance->SMPR2 |= ADC_SMPR2(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel);
}
/*---------------------------- ADCx JSQR Configuration -----------------*/
hadc->Instance->JSQR &= ~(ADC_JSQR_JL);
hadc->Instance->JSQR |= ADC_SQR1(sConfigInjected->InjectedNbrOfConversion);
/* Rank configuration */
/* Clear the old SQx bits for the selected rank */
hadc->Instance->JSQR &= ~ADC_JSQR(ADC_JSQR_JSQ1, sConfigInjected->InjectedRank,sConfigInjected->InjectedNbrOfConversion);
/* Set the SQx bits for the selected rank */
hadc->Instance->JSQR |= ADC_JSQR(sConfigInjected->InjectedChannel, sConfigInjected->InjectedRank,sConfigInjected->InjectedNbrOfConversion);
/* Enable external trigger if trigger selection is different of software */
/* start. */
/* Note: This configuration keeps the hardware feature of parameter */
/* ExternalTrigConvEdge "trigger edge none" equivalent to */
/* software start. */
if(sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START)
{
/* Select external trigger to start conversion */
hadc->Instance->CR2 &= ~(ADC_CR2_JEXTSEL);
hadc->Instance->CR2 |= sConfigInjected->ExternalTrigInjecConv;
/* Select external trigger polarity */
hadc->Instance->CR2 &= ~(ADC_CR2_JEXTEN);
hadc->Instance->CR2 |= sConfigInjected->ExternalTrigInjecConvEdge;
}
else
{
/* Reset the external trigger */
hadc->Instance->CR2 &= ~(ADC_CR2_JEXTSEL);
hadc->Instance->CR2 &= ~(ADC_CR2_JEXTEN);
}
if (sConfigInjected->AutoInjectedConv != DISABLE)
{
/* Enable the selected ADC automatic injected group conversion */
hadc->Instance->CR1 |= ADC_CR1_JAUTO;
}
else
{
/* Disable the selected ADC automatic injected group conversion */
hadc->Instance->CR1 &= ~(ADC_CR1_JAUTO);
}
if (sConfigInjected->InjectedDiscontinuousConvMode != DISABLE)
{
/* Enable the selected ADC injected discontinuous mode */
hadc->Instance->CR1 |= ADC_CR1_JDISCEN;
}
else
{
/* Disable the selected ADC injected discontinuous mode */
hadc->Instance->CR1 &= ~(ADC_CR1_JDISCEN);
}
switch(sConfigInjected->InjectedRank)
{
case 1:
/* Set injected channel 1 offset */
hadc->Instance->JOFR1 &= ~(ADC_JOFR1_JOFFSET1);
hadc->Instance->JOFR1 |= sConfigInjected->InjectedOffset;
break;
case 2:
/* Set injected channel 2 offset */
hadc->Instance->JOFR2 &= ~(ADC_JOFR2_JOFFSET2);
hadc->Instance->JOFR2 |= sConfigInjected->InjectedOffset;
break;
case 3:
/* Set injected channel 3 offset */
hadc->Instance->JOFR3 &= ~(ADC_JOFR3_JOFFSET3);
hadc->Instance->JOFR3 |= sConfigInjected->InjectedOffset;
break;
default:
/* Set injected channel 4 offset */
hadc->Instance->JOFR4 &= ~(ADC_JOFR4_JOFFSET4);
hadc->Instance->JOFR4 |= sConfigInjected->InjectedOffset;
break;
}
/* if ADC1 Channel_18 is selected enable VBAT Channel */
if ((hadc->Instance == ADC1) && (sConfigInjected->InjectedChannel == ADC_CHANNEL_VBAT))
{
/* Enable the VBAT channel*/
ADC->CCR |= ADC_CCR_VBATE;
}
/* if ADC1 Channel_16 or Channel_17 is selected enable TSVREFE Channel(Temperature sensor and VREFINT) */
if ((hadc->Instance == ADC1) && ((sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR) || (sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT)))
{
/* Enable the TSVREFE channel*/
ADC->CCR |= ADC_CCR_TSVREFE;
}
/* Process unlocked */
__HAL_UNLOCK(hadc);
/* Return function status */
return HAL_OK;
}
/**
* @brief Enables DAC and starts conversion of channel.
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @param Channel: The selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_CHANNEL_1: DAC Channel1 selected
* @arg DAC_CHANNEL_2: DAC Channel2 selected
* @param pData: The destination peripheral Buffer address.
* @param Length: The length of data to be transferred from memory to DAC peripheral
* @param Alignment: Specifies the data alignment for DAC channel.
* This parameter can be one of the following values:
* @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
* @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
* @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment)
{
uint32_t tmpreg = 0;
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(Channel));
assert_param(IS_DAC_ALIGN(Alignment));
/* Process locked */
__HAL_LOCK(hdac);
/* Change DAC state */
hdac->State = HAL_DAC_STATE_BUSY;
if(Channel == DAC_CHANNEL_1)
{
/* Set the DMA transfer complete callback for channel1 */
hdac->DMA_Handle1->XferCpltCallback = DAC_DMAConvCpltCh1;
/* Set the DMA half transfer complete callback for channel1 */
hdac->DMA_Handle1->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh1;
/* Set the DMA error callback for channel1 */
hdac->DMA_Handle1->XferErrorCallback = DAC_DMAErrorCh1;
/* Enable the selected DAC channel1 DMA request */
SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN1);
/* Case of use of channel 1 */
switch(Alignment)
{
case DAC_ALIGN_12B_R:
/* Get DHR12R1 address */
tmpreg = (uint32_t)&hdac->Instance->DHR12R1;
break;
case DAC_ALIGN_12B_L:
/* Get DHR12L1 address */
tmpreg = (uint32_t)&hdac->Instance->DHR12L1;
break;
case DAC_ALIGN_8B_R:
/* Get DHR8R1 address */
tmpreg = (uint32_t)&hdac->Instance->DHR8R1;
break;
default:
break;
}
}
else
{
/* Set the DMA transfer complete callback for channel2 */
hdac->DMA_Handle2->XferCpltCallback = DAC_DMAConvCpltCh2;
/* Set the DMA half transfer complete callback for channel2 */
hdac->DMA_Handle2->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh2;
/* Set the DMA error callback for channel2 */
hdac->DMA_Handle2->XferErrorCallback = DAC_DMAErrorCh2;
/* Enable the selected DAC channel2 DMA request */
SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN2);
/* Case of use of channel 2 */
switch(Alignment)
{
case DAC_ALIGN_12B_R:
/* Get DHR12R2 address */
tmpreg = (uint32_t)&hdac->Instance->DHR12R2;
break;
case DAC_ALIGN_12B_L:
/* Get DHR12L2 address */
tmpreg = (uint32_t)&hdac->Instance->DHR12L2;
break;
case DAC_ALIGN_8B_R:
/* Get DHR8R2 address */
tmpreg = (uint32_t)&hdac->Instance->DHR8R2;
break;
default:
break;
}
}
/* Enable the DMA channel */
if(Channel == DAC_CHANNEL_1)
{
/* Enable the DAC DMA underrun interrupt */
__HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR1);
/* Enable the DMA channel */
HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, Length);
}
else
{
/* Enable the DAC DMA underrun interrupt */
__HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR2);
/* Enable the DMA channel */
HAL_DMA_Start_IT(hdac->DMA_Handle2, (uint32_t)pData, tmpreg, Length);
}
/* Process Unlocked */
__HAL_UNLOCK(hdac);
/* Enable the Peripheral */
__HAL_DAC_ENABLE(hdac, Channel);
/* Return function status */
return HAL_OK;
}
/**
* @brief Enables the interrupt and starts ADC conversion of injected channels.
* @param hadc: pointer to a ADC_HandleTypeDef structure that contains
* the configuration information for the specified ADC.
*
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc)
{
__IO uint32_t counter = 0;
uint32_t tmp1 = 0, tmp2 =0;
/* Process locked */
__HAL_LOCK(hadc);
/* Check if a regular conversion is ongoing */
if(hadc->State == HAL_ADC_STATE_BUSY_REG)
{
/* Change ADC state */
hadc->State = HAL_ADC_STATE_BUSY_INJ_REG;
}
else
{
/* Change ADC state */
hadc->State = HAL_ADC_STATE_BUSY_INJ;
}
/* Set ADC error code to none */
hadc->ErrorCode = HAL_ADC_ERROR_NONE;
/* Check if ADC peripheral is disabled in order to enable it and wait during
Tstab time the ADC's stabilization */
if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)
{
/* Enable the Peripheral */
__HAL_ADC_ENABLE(hadc);
/* Delay for temperature sensor stabilization time */
/* Compute number of CPU cycles to wait for */
counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000));
while(counter != 0)
{
counter--;
}
}
/* Enable the ADC end of conversion interrupt for injected group */
__HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
/* Enable the ADC overrun interrupt */
__HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
/* Check if Multimode enabled */
if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI))
{
tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN);
tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO);
if(tmp1 && tmp2)
{
/* Enable the selected ADC software conversion for injected group */
hadc->Instance->CR2 |= ADC_CR2_JSWSTART;
}
}
else
{
tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN);
tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO);
if((hadc->Instance == ADC1) && tmp1 && tmp2)
{
/* Enable the selected ADC software conversion for injected group */
hadc->Instance->CR2 |= ADC_CR2_JSWSTART;
}
}
/* Process unlocked */
__HAL_UNLOCK(hadc);
/* Return function status */
return HAL_OK;
}
/**
* @brief Enables the interrupt and starts ADC conversion of injected channels.
* @param hadc: pointer to a ADC_HandleTypeDef structure that contains
* the configuration information for the specified ADC.
*
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc)
{
__IO uint32_t counter = 0;
uint32_t tmp1 = 0, tmp2 = 0;
/* Process locked */
__HAL_LOCK(hadc);
/* Enable the ADC peripheral */
/* Check if ADC peripheral is disabled in order to enable it and wait during
Tstab time the ADC's stabilization */
if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)
{
/* Enable the Peripheral */
__HAL_ADC_ENABLE(hadc);
/* Delay for ADC stabilization time */
/* Compute number of CPU cycles to wait for */
counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000));
while(counter != 0)
{
counter--;
}
}
/* Start conversion if ADC is effectively enabled */
if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON))
{
/* Set ADC state */
/* - Clear state bitfield related to injected group conversion results */
/* - Set state bitfield related to injected operation */
ADC_STATE_CLR_SET(hadc->State,
HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC,
HAL_ADC_STATE_INJ_BUSY);
/* Check if a regular conversion is ongoing */
/* Note: On this device, there is no ADC error code fields related to */
/* conversions on group injected only. In case of conversion on */
/* going on group regular, no error code is reset. */
if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
{
/* Reset ADC all error code fields */
ADC_CLEAR_ERRORCODE(hadc);
}
/* Process unlocked */
/* Unlock before starting ADC conversions: in case of potential */
/* interruption, to let the process to ADC IRQ Handler. */
__HAL_UNLOCK(hadc);
/* Clear injected group conversion flag */
/* (To ensure of no unknown state from potential previous ADC operations) */
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC);
/* Enable end of conversion interrupt for injected channels */
__HAL_ADC_ENABLE_IT(hadc, (ADC_IT_JEOC | ADC_IT_OVR));
/* Check if Multimode enabled */
if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI))
{
tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN);
tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO);
if(tmp1 && tmp2)
{
/* Enable the selected ADC software conversion for injected group */
hadc->Instance->CR2 |= ADC_CR2_JSWSTART;
}
}
else
{
tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN);
tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO);
if((hadc->Instance == ADC1) && tmp1 && tmp2)
{
/* Enable the selected ADC software conversion for injected group */
hadc->Instance->CR2 |= ADC_CR2_JSWSTART;
}
}
}
/* Return function status */
return HAL_OK;
}
/**
* @brief Full-Duplex Transmit/Receive data in non-blocking mode using Interrupt
* @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
* the configuration information for I2S module
* @param pTxData: a 16-bit pointer to the Transmit data buffer.
* @param pRxData: a 16-bit pointer to the Receive data buffer.
* @param Size: number of data sample to be sent:
* @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
* configuration phase, the Size parameter means the number of 16-bit data length
* in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
* the Size parameter means the number of 16-bit data length.
* @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
* between Master and Slave(example: audio streaming).
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, uint16_t Size)
{
uint32_t tmp1 = 0, tmp2 = 0;
if(hi2s->State == HAL_I2S_STATE_READY)
{
if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0))
{
return HAL_ERROR;
}
hi2s->pTxBuffPtr = pTxData;
hi2s->pRxBuffPtr = pRxData;
tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
tmp2 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
/* Check the Data format: When a 16-bit data frame or a 16-bit data frame extended
is selected during the I2S configuration phase, the Size parameter means the number
of 16-bit data length in the transaction and when a 24-bit data frame or a 32-bit data
frame is selected the Size parameter means the number of 16-bit data length. */
if((tmp1 == I2S_DATAFORMAT_24B)||\
(tmp2 == I2S_DATAFORMAT_32B))
{
hi2s->TxXferSize = Size*2;
hi2s->TxXferCount = Size*2;
hi2s->RxXferSize = Size*2;
hi2s->RxXferCount = Size*2;
}
else
{
hi2s->TxXferSize = Size;
hi2s->TxXferCount = Size;
hi2s->RxXferSize = Size;
hi2s->RxXferCount = Size;
}
/* Process Locked */
__HAL_LOCK(hi2s);
hi2s->State = HAL_I2S_STATE_BUSY_TX_RX;
hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
tmp1 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
tmp2 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
/* Check if the I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX Mode is selected */
if((tmp1 == I2S_MODE_MASTER_TX) || (tmp2 == I2S_MODE_SLAVE_TX))
{
/* Enable I2Sext RXNE and ERR interrupts */
I2SxEXT(hi2s->Instance)->CR2 |= (I2S_IT_RXNE | I2S_IT_ERR);
/* Enable I2Sx TXE and ERR interrupts */
__HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
/* Check if the I2S is already enabled */
if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
{
/* Enable I2Sext(receiver) before enabling I2Sx peripheral */
I2SxEXT(hi2s->Instance)->I2SCFGR |= SPI_I2SCFGR_I2SE;
/* Enable I2Sx peripheral */
__HAL_I2S_ENABLE(hi2s);
}
}
/* The I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX Mode is selected */
else
{
/* Enable I2Sext TXE and ERR interrupts */
I2SxEXT(hi2s->Instance)->CR2 |= (I2S_IT_TXE |I2S_IT_ERR);
/* Enable I2Sext RXNE and ERR interrupts */
__HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
/* Check if the I2S is already enabled */
if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
{
/* Check if the I2S_MODE_MASTER_RX is selected */
if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
{
/* Prepare the First Data before enabling the I2S */
if(hi2s->TxXferCount != 0)
{
/* Transmit First data */
I2SxEXT(hi2s->Instance)->DR = (*hi2s->pTxBuffPtr++);
hi2s->TxXferCount--;
if(hi2s->TxXferCount == 0)
{
/* Disable I2Sext TXE interrupt */
I2SxEXT(hi2s->Instance)->CR2 &= ~I2S_IT_TXE;
}
}
}
/* Enable I2S peripheral */
__HAL_I2S_ENABLE(hi2s);
/* Enable I2Sext(transmitter) after enabling I2Sx peripheral */
I2SxEXT(hi2s->Instance)->I2SCFGR |= SPI_I2SCFGR_I2SE;
}
}
/* Process Unlocked */
__HAL_UNLOCK(hi2s);
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Full-Duplex Transmit/Receive data in non-blocking mode using DMA
* @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
* the configuration information for I2S module
* @param pTxData: a 16-bit pointer to the Transmit data buffer.
* @param pRxData: a 16-bit pointer to the Receive data buffer.
* @param Size: number of data sample to be sent:
* @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
* configuration phase, the Size parameter means the number of 16-bit data length
* in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
* the Size parameter means the number of 16-bit data length.
* @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
* between Master and Slave(example: audio streaming).
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, uint16_t Size)
{
uint32_t *tmp;
uint32_t tmp1 = 0, tmp2 = 0;
if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0))
{
return HAL_ERROR;
}
if(hi2s->State == HAL_I2S_STATE_READY)
{
hi2s->pTxBuffPtr = pTxData;
hi2s->pRxBuffPtr = pRxData;
tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
tmp2 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
/* Check the Data format: When a 16-bit data frame or a 16-bit data frame extended
is selected during the I2S configuration phase, the Size parameter means the number
of 16-bit data length in the transaction and when a 24-bit data frame or a 32-bit data
frame is selected the Size parameter means the number of 16-bit data length. */
if((tmp1 == I2S_DATAFORMAT_24B)||\
(tmp2 == I2S_DATAFORMAT_32B))
{
hi2s->TxXferSize = Size*2;
hi2s->TxXferCount = Size*2;
hi2s->RxXferSize = Size*2;
hi2s->RxXferCount = Size*2;
}
else
{
hi2s->TxXferSize = Size;
hi2s->TxXferCount = Size;
hi2s->RxXferSize = Size;
hi2s->RxXferCount = Size;
}
/* Process Locked */
__HAL_LOCK(hi2s);
hi2s->State = HAL_I2S_STATE_BUSY_TX_RX;
hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
/* Set the I2S Rx DMA Half transfert complete callback */
hi2s->hdmarx->XferHalfCpltCallback = I2S_DMARxHalfCplt;
/* Set the I2S Rx DMA transfert complete callback */
hi2s->hdmarx->XferCpltCallback = I2S_DMARxCplt;
/* Set the I2S Rx DMA error callback */
hi2s->hdmarx->XferErrorCallback = I2S_DMAError;
/* Set the I2S Tx DMA Half transfert complete callback */
hi2s->hdmatx->XferHalfCpltCallback = I2S_DMATxHalfCplt;
/* Set the I2S Tx DMA transfert complete callback */
hi2s->hdmatx->XferCpltCallback = I2S_DMATxCplt;
/* Set the I2S Tx DMA error callback */
hi2s->hdmatx->XferErrorCallback = I2S_DMAError;
tmp1 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
tmp2 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
/* Check if the I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX Mode is selected */
if((tmp1 == I2S_MODE_MASTER_TX) || (tmp2 == I2S_MODE_SLAVE_TX))
{
/* Enable the Rx DMA Stream */
tmp = (uint32_t*)&pRxData;
HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&I2SxEXT(hi2s->Instance)->DR, *(uint32_t*)tmp, hi2s->RxXferSize);
/* Enable Rx DMA Request */
I2SxEXT(hi2s->Instance)->CR2 |= SPI_CR2_RXDMAEN;
/* Enable the Tx DMA Stream */
tmp = (uint32_t*)&pTxData;
HAL_DMA_Start_IT(hi2s->hdmatx, *(uint32_t*)tmp, (uint32_t)&hi2s->Instance->DR, hi2s->TxXferSize);
/* Enable Tx DMA Request */
hi2s->Instance->CR2 |= SPI_CR2_TXDMAEN;
/* Check if the I2S is already enabled */
if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
{
/* Enable I2Sext(receiver) before enabling I2Sx peripheral */
I2SxEXT(hi2s->Instance)->I2SCFGR |= SPI_I2SCFGR_I2SE;
/* Enable I2S peripheral after the I2Sext */
__HAL_I2S_ENABLE(hi2s);
}
}
else
{
/* Enable the Tx DMA Stream */
tmp = (uint32_t*)&pTxData;
HAL_DMA_Start_IT(hi2s->hdmatx, *(uint32_t*)tmp, (uint32_t)&I2SxEXT(hi2s->Instance)->DR, hi2s->TxXferSize);
/* Enable Tx DMA Request */
I2SxEXT(hi2s->Instance)->CR2 |= SPI_CR2_TXDMAEN;
/* Enable the Rx DMA Stream */
tmp = (uint32_t*)&pRxData;
HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->DR, *(uint32_t*)tmp, hi2s->RxXferSize);
/* Enable Rx DMA Request */
hi2s->Instance->CR2 |= SPI_CR2_RXDMAEN;
/* Check if the I2S is already enabled */
if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
{
/* Enable I2S peripheral before the I2Sext */
__HAL_I2S_ENABLE(hi2s);
/* Enable I2Sext(transmitter) after enabling I2Sx peripheral */
I2SxEXT(hi2s->Instance)->I2SCFGR |= SPI_I2SCFGR_I2SE;
}
else
{
/* Check if Master Receiver mode is selected */
if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
{
/* Clear the Overrun Flag by a read operation on the SPI_DR register followed by a read
access to the SPI_SR register. */
__HAL_I2S_CLEAR_OVRFLAG(hi2s);
}
}
}
/* Process Unlocked */
__HAL_UNLOCK(hi2s);
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Write sector to PCCARD memory
* @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
* the configuration information for PCCARD module.
* @param pBuffer: pointer to source write buffer
* @param SectorAddress: Sector address to write
* @param pStatus: pointer to CF status
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCCARD_Write_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress, uint8_t *pStatus)
{
uint32_t timeout = PCCARD_TIMEOUT_SECTOR, index = 0;
uint8_t status = 0;
/* Process Locked */
__HAL_LOCK(hpccard);
/* Check the PCCARD controller state */
if(hpccard->State == HAL_PCCARD_STATE_BUSY)
{
return HAL_BUSY;
}
/* Update the PCCARD controller state */
hpccard->State = HAL_PCCARD_STATE_BUSY;
/* Initialize CF status */
*pStatus = PCCARD_READY;
/* Set the parameters to write a sector */
*(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_CYLINDER_HIGH) = (uint16_t)0x00;
*(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_SECTOR_COUNT) = ((uint16_t)0x0100 ) | ((uint16_t)SectorAddress);
*(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD) = (uint16_t)0x30A0;
do
{
/* Wait till the Status = PCCARD_STATUS_OK */
status = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
timeout--;
}while((status != PCCARD_STATUS_OK) && timeout);
if(timeout == 0)
{
*pStatus = PCCARD_TIMEOUT_ERROR;
}
/* Write bytes */
for(; index < PCCARD_SECTOR_SIZE; index++)
{
*(uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR) = *(uint16_t *)pBuffer++;
}
do
{
/* Wait till the Status = PCCARD_STATUS_WRITE_OK */
status = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
timeout--;
}while((status != PCCARD_STATUS_WRITE_OK) && timeout);
if(timeout == 0)
{
*pStatus = PCCARD_TIMEOUT_ERROR;
}
/* Update the PCCARD controller state */
hpccard->State = HAL_PCCARD_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hpccard);
return HAL_OK;
}
/**
* @brief Full-Duplex Transmit/Receive data in blocking mode.
* @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
* the configuration information for I2S module
* @param pTxData: a 16-bit pointer to the Transmit data buffer.
* @param pRxData: a 16-bit pointer to the Receive data buffer.
* @param Size: number of data sample to be sent:
* @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
* configuration phase, the Size parameter means the number of 16-bit data length
* in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
* the Size parameter means the number of 16-bit data length.
* @param Timeout: Timeout duration
* @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
* between Master and Slave(example: audio streaming).
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2SEx_TransmitReceive(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, uint16_t Size, uint32_t Timeout)
{
uint32_t tickstart = 0;
uint32_t tmp1 = 0, tmp2 = 0;
if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0))
{
return HAL_ERROR;
}
/* Check the I2S State */
if(hi2s->State == HAL_I2S_STATE_READY)
{
tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
tmp2 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
/* Check the Data format: When a 16-bit data frame or a 16-bit data frame extended
is selected during the I2S configuration phase, the Size parameter means the number
of 16-bit data length in the transaction and when a 24-bit data frame or a 32-bit data
frame is selected the Size parameter means the number of 16-bit data length. */
if((tmp1 == I2S_DATAFORMAT_24B)|| \
(tmp2 == I2S_DATAFORMAT_32B))
{
hi2s->TxXferSize = Size*2;
hi2s->TxXferCount = Size*2;
hi2s->RxXferSize = Size*2;
hi2s->RxXferCount = Size*2;
}
else
{
hi2s->TxXferSize = Size;
hi2s->TxXferCount = Size;
hi2s->RxXferSize = Size;
hi2s->RxXferCount = Size;
}
/* Process Locked */
__HAL_LOCK(hi2s);
/* Set the I2S State busy TX/RX */
hi2s->State = HAL_I2S_STATE_BUSY_TX_RX;
tmp1 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
tmp2 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
/* Check if the I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX Mode is selected */
if((tmp1 == I2S_MODE_MASTER_TX) || (tmp2 == I2S_MODE_SLAVE_TX))
{
/* Check if the I2S is already enabled: The I2S is kept enabled at the end of transaction
to avoid the clock de-synchronization between Master and Slave. */
if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
{
/* Enable I2Sext(receiver) before enabling I2Sx peripheral */
I2SxEXT(hi2s->Instance)->I2SCFGR |= SPI_I2SCFGR_I2SE;
/* Enable I2Sx peripheral */
__HAL_I2S_ENABLE(hi2s);
}
while(hi2s->TxXferCount > 0)
{
/* Wait until TXE flag is set */
if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, RESET, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
hi2s->Instance->DR = (*pTxData++);
/* Get tick */
tickstart = HAL_GetTick();
/* Wait until RXNE flag is set */
while((I2SxEXT(hi2s->Instance)->SR & SPI_SR_RXNE) != SPI_SR_RXNE)
{
if(Timeout != HAL_MAX_DELAY)
{
if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
{
/* Process Unlocked */
__HAL_UNLOCK(hi2s);
return HAL_TIMEOUT;
}
}
}
(*pRxData++) = I2SxEXT(hi2s->Instance)->DR;
hi2s->TxXferCount--;
hi2s->RxXferCount--;
}
}
/* The I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX Mode is selected */
else
{
/* Check if the I2S is already enabled */
if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
{
/* Enable I2S peripheral before the I2Sext*/
__HAL_I2S_ENABLE(hi2s);
/* Enable I2Sext(transmitter) after enabling I2Sx peripheral */
I2SxEXT(hi2s->Instance)->I2SCFGR |= SPI_I2SCFGR_I2SE;
}
else
{
/* Check if Master Receiver mode is selected */
if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
{
/* Clear the Overrun Flag by a read operation on the SPI_DR register followed by a read
access to the SPI_SR register. */
__HAL_I2S_CLEAR_OVRFLAG(hi2s);
}
}
while(hi2s->TxXferCount > 0)
{
/* Get tick */
tickstart = HAL_GetTick();
/* Wait until TXE flag is set */
while((I2SxEXT(hi2s->Instance)->SR & SPI_SR_TXE) != SPI_SR_TXE)
{
if(Timeout != HAL_MAX_DELAY)
{
if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
{
/* Process Unlocked */
__HAL_UNLOCK(hi2s);
return HAL_TIMEOUT;
}
}
}
I2SxEXT(hi2s->Instance)->DR = (*pTxData++);
/* Wait until RXNE flag is set */
if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_RXNE, RESET, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
(*pRxData++) = hi2s->Instance->DR;
hi2s->TxXferCount--;
hi2s->RxXferCount--;
}
}
/* Set the I2S State ready */
hi2s->State = HAL_I2S_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hi2s);
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Writes a half-word buffer to the FSMC NOR memory. This function
* must be used only with S29GL128P NOR memory.
* @param hnor: pointer to a NOR_HandleTypeDef structure that contains
* the configuration information for NOR module.
* @param uwAddress: NOR memory internal address from which the data
* @note Some NOR memory need Address aligned to xx bytes (can be aligned to
* 64 bytes boundary for example).
* @param pData: pointer to source data buffer.
* @param uwBufferSize: number of Half words to write.
* @note The maximum buffer size allowed is NOR memory dependent
* (can be 64 Bytes max for example).
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)
{
uint16_t * p_currentaddress = (uint16_t *)NULL;
uint16_t * p_endaddress = (uint16_t *)NULL;
uint32_t lastloadedaddress = 0, deviceaddress = 0;
/* Process Locked */
__HAL_LOCK(hnor);
/* Check the NOR controller state */
if(hnor->State == HAL_NOR_STATE_BUSY)
{
return HAL_BUSY;
}
/* Select the NOR device address */
if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
{
deviceaddress = NOR_MEMORY_ADRESS1;
}
else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
{
deviceaddress = NOR_MEMORY_ADRESS2;
}
else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
{
deviceaddress = NOR_MEMORY_ADRESS3;
}
else /* FSMC_NORSRAM_BANK4 */
{
deviceaddress = NOR_MEMORY_ADRESS4;
}
/* Update the NOR controller state */
hnor->State = HAL_NOR_STATE_BUSY;
/* Initialize variables */
p_currentaddress = (uint16_t*)((uint32_t)(uwAddress));
p_endaddress = p_currentaddress + (uwBufferSize-1);
lastloadedaddress = (uint32_t)(uwAddress);
/* Issue unlock command sequence */
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
/* Write Buffer Load Command */
NOR_WRITE((uint32_t)(p_currentaddress), NOR_CMD_DATA_BUFFER_AND_PROG);
NOR_WRITE((uint32_t)(p_currentaddress), (uwBufferSize-1));
/* Load Data into NOR Buffer */
while(p_currentaddress <= p_endaddress)
{
/* Store last loaded address & data value (for polling) */
lastloadedaddress = (uint32_t)p_currentaddress;
NOR_WRITE(p_currentaddress, *pData++);
p_currentaddress++;
}
NOR_WRITE((uint32_t)(lastloadedaddress), NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM);
/* Check the NOR controller state */
hnor->State = HAL_NOR_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hnor);
return HAL_OK;
}
/**
* @brief Send data in interrupt mode
* @param hcec: CEC handle.
* Function called under interruption only, once
* interruptions have been enabled by HAL_CEC_Transmit_IT()
* @retval HAL status
*/
static HAL_StatusTypeDef CEC_Transmit_IT(CEC_HandleTypeDef *hcec)
{
/* if the IP is already busy or if there is a previous transmission
already pending due to arbitration loss */
if ((hcec->State == HAL_CEC_STATE_BUSY_TX)
|| (__HAL_CEC_GET_TRANSMISSION_START_FLAG(hcec) != RESET))
{
__HAL_LOCK(hcec);
/* set state to BUSY TX, in case it wasn't set already (case
* of transmission new attempt after arbitration loss) */
if (hcec->State != HAL_CEC_STATE_BUSY_TX)
{
hcec->State = HAL_CEC_STATE_BUSY_TX;
}
/* if all data have been sent */
if(hcec->TxXferCount == 0)
{
/* Disable Peripheral to write CEC_IER register */
__HAL_CEC_DISABLE(hcec);
/* Disable the CEC Transmission Interrupts */
__HAL_CEC_DISABLE_IT(hcec, CEC_IT_TXBR|CEC_IT_TXEND);
/* Disable the CEC Transmission Error Interrupts */
__HAL_CEC_DISABLE_IT(hcec, CEC_IER_TX_ALL_ERR);
/* Enable the Peripheral */
__HAL_CEC_ENABLE(hcec);
__HAL_CEC_CLEAR_FLAG(hcec,CEC_FLAG_TXBR|CEC_FLAG_TXEND);
hcec->State = HAL_CEC_STATE_READY;
/* Call the Process Unlocked before calling the Tx call back API to give the possibility to
start again the Transmission under the Tx call back API */
__HAL_UNLOCK(hcec);
HAL_CEC_TxCpltCallback(hcec);
return HAL_OK;
}
else
{
if (hcec->TxXferCount == 1)
{
/* if this is the last byte transmission, set TX End of Message (TXEOM) bit */
__HAL_CEC_LAST_BYTE_TX_SET(hcec);
}
/* clear Tx-Byte request flag */
__HAL_CEC_CLEAR_FLAG(hcec,CEC_FLAG_TXBR);
hcec->Instance->TXDR = *hcec->pTxBuffPtr++;
hcec->TxXferCount--;
/* Process Unlocked */
__HAL_UNLOCK(hcec);
return HAL_OK;
}
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Send data in interrupt mode
* @param hcec: CEC handle
* @param DestinationAddress: destination logical address
* @param pData: pointer to input byte data buffer
* @param Size: amount of data to be sent in bytes (without counting the header).
* 0 means only the header is sent (ping operation).
* Maximum TX size is 15 bytes (1 opcode and up to 14 operands).
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t DestinationAddress, uint8_t *pData, uint32_t Size)
{
uint8_t temp = 0;
/* if the IP isn't already busy and if there is no previous transmission
already pending due to arbitration lost */
if (((hcec->State == HAL_CEC_STATE_READY) || (hcec->State == HAL_CEC_STATE_STANDBY_RX))
&& (__HAL_CEC_GET_TRANSMISSION_START_FLAG(hcec) == RESET))
{
if((pData == NULL ) && (Size > 0))
{
hcec->State = HAL_CEC_STATE_ERROR;
return HAL_ERROR;
}
assert_param(IS_CEC_ADDRESS(DestinationAddress));
assert_param(IS_CEC_MSGSIZE(Size));
/* Process Locked */
__HAL_LOCK(hcec);
hcec->pTxBuffPtr = pData;
hcec->State = HAL_CEC_STATE_BUSY_TX;
hcec->ErrorCode = HAL_CEC_ERROR_NONE;
/* Disable Peripheral to write CEC_IER register */
__HAL_CEC_DISABLE(hcec);
/* Enable the following two CEC Transmission interrupts as
* well as the following CEC Transmission Errors interrupts:
* Tx Byte Request IT
* End of Transmission IT
* Tx Missing Acknowledge IT
* Tx-Error IT
* Tx-Buffer Underrun IT
* Tx arbitration lost */
__HAL_CEC_ENABLE_IT(hcec, CEC_IT_TXBR|CEC_IT_TXEND|CEC_IER_TX_ALL_ERR);
/* Enable the Peripheral */
__HAL_CEC_ENABLE(hcec);
/* initialize the number of bytes to send,
* 0 means only one header is sent (ping operation) */
hcec->TxXferCount = Size;
/* Process Unlocked */
__HAL_UNLOCK(hcec);
/* in case of no payload (Size = 0), sender is only pinging the system;
* Set TX End of Message (TXEOM) bit, must be set before writing data to TXDR */
if (Size == 0)
{
__HAL_CEC_LAST_BYTE_TX_SET(hcec);
}
/* send header block */
temp = ((uint32_t)hcec->Init.InitiatorAddress << CEC_INITIATOR_LSB_POS) | DestinationAddress;
hcec->Instance->TXDR = temp;
/* Set TX Start of Message (TXSOM) bit */
__HAL_CEC_FIRST_BYTE_TX_SET(hcec);
return HAL_OK;
}
/* if the IP is already busy or if there is a previous transmission
already pending due to arbitration loss */
else if ((hcec->State == HAL_CEC_STATE_BUSY_TX)
|| (__HAL_CEC_GET_TRANSMISSION_START_FLAG(hcec) != RESET))
{
__HAL_LOCK(hcec);
/* set state to BUSY TX, in case it wasn't set already (case
* of transmission new attempt after arbitration loss) */
if (hcec->State != HAL_CEC_STATE_BUSY_TX)
{
hcec->State = HAL_CEC_STATE_BUSY_TX;
}
/* if all data have been sent */
if(hcec->TxXferCount == 0)
{
/* Disable Peripheral to write CEC_IER register */
__HAL_CEC_DISABLE(hcec);
/* Disable the CEC Transmission Interrupts */
__HAL_CEC_DISABLE_IT(hcec, CEC_IT_TXBR|CEC_IT_TXEND);
/* Disable the CEC Transmission Error Interrupts */
__HAL_CEC_DISABLE_IT(hcec, CEC_IER_TX_ALL_ERR);
/* Enable the Peripheral */
__HAL_CEC_ENABLE(hcec);
__HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXBR|CEC_FLAG_TXEND);
hcec->State = HAL_CEC_STATE_READY;
/* Call the Process Unlocked before calling the Tx call back API to give the possibility to
start again the Transmission under the Tx call back API */
__HAL_UNLOCK(hcec);
HAL_CEC_TxCpltCallback(hcec);
return HAL_OK;
}
else
{
if (hcec->TxXferCount == 1)
{
/* if this is the last byte transmission, set TX End of Message (TXEOM) bit */
__HAL_CEC_LAST_BYTE_TX_SET(hcec);
}
/* clear Tx-Byte request flag */
__HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXBR);
hcec->Instance->TXDR = *hcec->pTxBuffPtr++;
hcec->TxXferCount--;
/* Process Unlocked */
__HAL_UNLOCK(hcec);
return HAL_OK;
}
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Enables the interrupt and starts ADC conversion of regular channels.
* @param hadc: pointer to a ADC_HandleTypeDef structure that contains
* the configuration information for the specified ADC.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc)
{
uint16_t i = 0;
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
/* Process locked */
__HAL_LOCK(hadc);
/* Check if an injected conversion is ongoing */
if(hadc->State == HAL_ADC_STATE_BUSY_INJ)
{
/* Change ADC state */
hadc->State = HAL_ADC_STATE_BUSY_INJ_REG;
}
else
{
/* Change ADC state */
hadc->State = HAL_ADC_STATE_BUSY_REG;
}
/* Set ADC error code to none */
hadc->ErrorCode = HAL_ADC_ERROR_NONE;
/* Check if ADC peripheral is disabled in order to enable it and wait during
Tstab time the ADC's stabilization */
if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)
{
/* Enable the Peripheral */
__HAL_ADC_ENABLE(hadc);
/* Delay inserted to wait during Tstab time the ADC's stabilization */
for(; i <= 540; i++)
{
__NOP();
}
}
/* Enable the ADC overrun interrupt */
__HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
/* Enable the ADC end of conversion interrupt for regular group */
__HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOC);
/* Check if Multimode enabled */
if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI))
{
/* if no external trigger present enable software conversion of regular channels */
if (hadc->Init.ExternalTrigConvEdge == ADC_EXTERNALTRIGCONVEDGE_NONE)
{
/* Enable the selected ADC software conversion for regular group */
hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
}
}
else
{
/* if instance of handle correspond to ADC1 and no external trigger present enable software conversion of regular channels */
if ((hadc->Instance == (ADC_TypeDef*)0x40012000) && (hadc->Init.ExternalTrigConvEdge == ADC_EXTERNALTRIGCONVEDGE_NONE))
{
/* Enable the selected ADC software conversion for regular group */
hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
}
}
/* Process unlocked */
__HAL_UNLOCK(hadc);
/* Return function status */
return HAL_OK;
}
/**
* @brief Full-Duplex Transmit/Receive data in non-blocking mode using Interrupt
* @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
* the configuration information for I2S module
* @retval HAL status
*/
HAL_StatusTypeDef I2SEx_TransmitReceive_IT(I2S_HandleTypeDef *hi2s)
{
uint32_t tmp1 = 0, tmp2 = 0;
if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
{
/* Process Locked */
__HAL_LOCK(hi2s);
tmp1 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
tmp2 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
/* Check if the I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX Mode is selected */
if((tmp1 == I2S_MODE_MASTER_TX) || (tmp2 == I2S_MODE_SLAVE_TX))
{
if(hi2s->TxXferCount != 0)
{
if(__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_TXE) != RESET)
{
/* Transmit data */
hi2s->Instance->DR = (*hi2s->pTxBuffPtr++);
hi2s->TxXferCount--;
if(hi2s->TxXferCount == 0)
{
/* Disable TXE interrupt */
__HAL_I2S_DISABLE_IT(hi2s, I2S_IT_TXE);
}
}
}
if(hi2s->RxXferCount != 0)
{
if((I2SxEXT(hi2s->Instance)->SR & SPI_SR_RXNE) == SPI_SR_RXNE)
{
/* Receive data */
(*hi2s->pRxBuffPtr++) = I2SxEXT(hi2s->Instance)->DR;
hi2s->RxXferCount--;
if(hi2s->RxXferCount == 0)
{
/* Disable I2Sext RXNE interrupt */
I2SxEXT(hi2s->Instance)->CR2 &= ~I2S_IT_RXNE;
}
}
}
}
/* The I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX Mode is selected */
else
{
if(hi2s->TxXferCount != 0)
{
if((I2SxEXT(hi2s->Instance)->SR & SPI_SR_TXE) == SPI_SR_TXE)
{
/* Transmit data */
I2SxEXT(hi2s->Instance)->DR = (*hi2s->pTxBuffPtr++);
hi2s->TxXferCount--;
if(hi2s->TxXferCount == 0)
{
/* Disable I2Sext TXE interrupt */
I2SxEXT(hi2s->Instance)->CR2 &= ~I2S_IT_TXE;
HAL_I2S_TxCpltCallback(hi2s);
}
}
}
if(hi2s->RxXferCount != 0)
{
if(__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_RXNE) != RESET)
{
/* Receive data */
(*hi2s->pRxBuffPtr++) = hi2s->Instance->DR;
hi2s->RxXferCount--;
if(hi2s->RxXferCount == 0)
{
/* Disable RXNE interrupt */
__HAL_I2S_DISABLE_IT(hi2s, I2S_IT_RXNE);
HAL_I2S_RxCpltCallback(hi2s);
}
}
}
}
tmp1 = hi2s->RxXferCount;
tmp2 = hi2s->TxXferCount;
if((tmp1 == 0) && (tmp2 == 0))
{
/* Disable I2Sx ERR interrupt */
__HAL_I2S_DISABLE_IT(hi2s, I2S_IT_ERR);
/* Disable I2Sext ERR interrupt */
I2SxEXT(hi2s->Instance)->CR2 &= ~I2S_IT_ERR;
hi2s->State = HAL_I2S_STATE_READY;
}
/* Process Unlocked */
__HAL_UNLOCK(hi2s);
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Configures for the selected ADC regular channel its corresponding
* rank in the sequencer and its sample time.
* @param hadc: pointer to a ADC_HandleTypeDef structure that contains
* the configuration information for the specified ADC.
* @param sConfig: ADC configuration structure.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig)
{
/* Check the parameters */
assert_param(IS_ADC_CHANNEL(sConfig->Channel));
assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank));
assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime));
/* Process locked */
__HAL_LOCK(hadc);
/* if ADC_Channel_10 ... ADC_Channel_18 is selected */
if (sConfig->Channel > ADC_CHANNEL_9)
{
/* Clear the old sample time */
hadc->Instance->SMPR1 &= ~ADC_SMPR1(ADC_SMPR1_SMP10, sConfig->Channel);
/* Set the new sample time */
hadc->Instance->SMPR1 |= ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel);
}
else /* ADC_Channel include in ADC_Channel_[0..9] */
{
/* Clear the old sample time */
hadc->Instance->SMPR2 &= ~ADC_SMPR2(ADC_SMPR2_SMP0, sConfig->Channel);
/* Set the new sample time */
hadc->Instance->SMPR2 |= ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel);
}
/* For Rank 1 to 6 */
if (sConfig->Rank < 7)
{
/* Clear the old SQx bits for the selected rank */
hadc->Instance->SQR3 &= ~ADC_SQR3_RK(ADC_SQR3_SQ1, sConfig->Rank);
/* Set the SQx bits for the selected rank */
hadc->Instance->SQR3 |= ADC_SQR3_RK(sConfig->Channel, sConfig->Rank);
}
/* For Rank 7 to 12 */
else if (sConfig->Rank < 13)
{
/* Clear the old SQx bits for the selected rank */
hadc->Instance->SQR2 &= ~ADC_SQR2_RK(ADC_SQR2_SQ7, sConfig->Rank);
/* Set the SQx bits for the selected rank */
hadc->Instance->SQR2 |= ADC_SQR2_RK(sConfig->Channel, sConfig->Rank);
}
/* For Rank 13 to 16 */
else
{
/* Clear the old SQx bits for the selected rank */
hadc->Instance->SQR1 &= ~ADC_SQR1_RK(ADC_SQR1_SQ13, sConfig->Rank);
/* Set the SQx bits for the selected rank */
hadc->Instance->SQR1 |= ADC_SQR1_RK(sConfig->Channel, sConfig->Rank);
}
/* if ADC1 Channel_18 is selected enable VBAT Channel */
if ((hadc->Instance == ADC1) && (sConfig->Channel == ADC_CHANNEL_VBAT))
{
/* Enable the VBAT channel*/
ADC->CCR |= ADC_CCR_VBATE;
}
/* if ADC1 Channel_16 or Channel_17 is selected enable TSVREFE Channel(Temperature sensor and VREFINT) */
if ((hadc->Instance == ADC1) && ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) || (sConfig->Channel == ADC_CHANNEL_VREFINT)))
{
/* Enable the TSVREFE channel*/
ADC->CCR |= ADC_CCR_TSVREFE;
}
/* Process unlocked */
__HAL_UNLOCK(hadc);
/* Return function status */
return HAL_OK;
}
/**
* @brief Read Spare area(s) from NAND memory
* @param hnand: pointer to a NAND_HandleTypeDef structure that contains
* the configuration information for NAND module.
* @param pAddress : pointer to NAND address structure
* @param pBuffer: pointer to source buffer to write
* @param NumSpareAreaToRead: Number of spare area to read
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NAND_Read_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead)
{
__IO uint32_t index = 0;
uint32_t deviceaddress = 0, size = 0, num_spare_area_read = 0, addressstatus = NAND_VALID_ADDRESS;
NAND_AddressTypeDef nandaddress;
uint32_t addressoffset = 0;
/* Process Locked */
__HAL_LOCK(hnand);
/* Check the NAND controller state */
if(hnand->State == HAL_NAND_STATE_BUSY)
{
return HAL_BUSY;
}
/* Identify the device address */
if(hnand->Init.NandBank == FMC_NAND_BANK2)
{
deviceaddress = NAND_DEVICE1;
}
else
{
deviceaddress = NAND_DEVICE2;
}
/* Update the NAND controller state */
hnand->State = HAL_NAND_STATE_BUSY;
/* Save the content of pAddress as it will be modified */
nandaddress.Block = pAddress->Block;
nandaddress.Page = pAddress->Page;
nandaddress.Zone = pAddress->Zone;
/* Spare area(s) read loop */
while((NumSpareAreaToRead != 0) && (addressstatus == NAND_VALID_ADDRESS))
{
/* update the buffer size */
size = (hnand->Info.SpareAreaSize) + ((hnand->Info.SpareAreaSize) * num_spare_area_read);
/* Get the address offset */
addressoffset = ARRAY_ADDRESS(&nandaddress, hnand);
/* Send read spare area command sequence */
*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C;
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(addressoffset);
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(addressoffset);
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(addressoffset);
/* for 512 and 1 GB devices, 4th cycle is required */
if(hnand->Info.BlockNbr >= 1024)
{
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_4TH_CYCLE(addressoffset);
}
*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
/* Get Data into Buffer */
for (index = size ;index != 0; index--)
{
*(uint8_t *)pBuffer++ = *(uint8_t *)deviceaddress;
}
/* Increment read spare areas number */
num_spare_area_read++;
/* Decrement spare areas to read */
NumSpareAreaToRead--;
/* Increment the NAND address */
addressstatus = HAL_NAND_Address_Inc(hnand, &nandaddress);
}
/* Update the NAND controller state */
hnand->State = HAL_NAND_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hnand);
return HAL_OK;
}
/**
* @brief Enables ADC DMA request after last transfer (Multi-ADC mode) and enables ADC peripheral
*
* @note Caution: This function must be used only with the ADC master.
*
* @param hadc: pointer to a ADC_HandleTypeDef structure that contains
* the configuration information for the specified ADC.
* @param pData: Pointer to buffer in which transferred from ADC peripheral to memory will be stored.
* @param Length: The length of data to be transferred from ADC peripheral to memory.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
{
__IO uint32_t counter = 0;
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests));
/* Process locked */
__HAL_LOCK(hadc);
/* Enable ADC overrun interrupt */
__HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
if (hadc->Init.DMAContinuousRequests != DISABLE)
{
/* Enable the selected ADC DMA request after last transfer */
ADC->CCR |= ADC_CCR_DDS;
}
else
{
/* Disable the selected ADC EOC rising on each regular channel conversion */
ADC->CCR &= ~ADC_CCR_DDS;
}
/* Set the DMA transfer complete callback */
hadc->DMA_Handle->XferCpltCallback = ADC_MultiModeDMAConvCplt;
/* Set the DMA half transfer complete callback */
hadc->DMA_Handle->XferHalfCpltCallback = ADC_MultiModeDMAHalfConvCplt;
/* Set the DMA error callback */
hadc->DMA_Handle->XferErrorCallback = ADC_MultiModeDMAError ;
/* Enable the DMA Stream */
HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&ADC->CDR, (uint32_t)pData, Length);
/* Change ADC state */
hadc->State = HAL_ADC_STATE_BUSY_REG;
/* Check if ADC peripheral is disabled in order to enable it and wait during
Tstab time the ADC's stabilization */
if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)
{
/* Enable the Peripheral */
__HAL_ADC_ENABLE(hadc);
/* Delay for temperature sensor stabilization time */
/* Compute number of CPU cycles to wait for */
counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000));
while(counter != 0)
{
counter--;
}
}
/* if no external trigger present enable software conversion of regular channels */
if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)
{
/* Enable the selected ADC software conversion for regular group */
hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
}
/* Process unlocked */
__HAL_UNLOCK(hadc);
/* Return function status */
return HAL_OK;
}
/**
* @brief Write Spare area(s) to NAND memory
* @param hnand: pointer to a NAND_HandleTypeDef structure that contains
* the configuration information for NAND module.
* @param pAddress : pointer to NAND address structure
* @param pBuffer : pointer to source buffer to write
* @param NumSpareAreaTowrite : number of spare areas to write to block
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NAND_Write_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite)
{
__IO uint32_t index = 0;
uint32_t tickstart = 0;
uint32_t deviceaddress = 0, size = 0, num_spare_area_written = 0, addressstatus = NAND_VALID_ADDRESS;
NAND_AddressTypeDef nandaddress;
uint32_t addressoffset = 0;
/* Process Locked */
__HAL_LOCK(hnand);
/* Check the NAND controller state */
if(hnand->State == HAL_NAND_STATE_BUSY)
{
return HAL_BUSY;
}
/* Identify the device address */
if(hnand->Init.NandBank == FMC_NAND_BANK2)
{
deviceaddress = NAND_DEVICE1;
}
else
{
deviceaddress = NAND_DEVICE2;
}
/* Update the FMC_NAND controller state */
hnand->State = HAL_NAND_STATE_BUSY;
/* Save the content of pAddress as it will be modified */
nandaddress.Block = pAddress->Block;
nandaddress.Page = pAddress->Page;
nandaddress.Zone = pAddress->Zone;
/* Spare area(s) write loop */
while((NumSpareAreaTowrite != 0) && (addressstatus == NAND_VALID_ADDRESS))
{
/* update the buffer size */
size = (hnand->Info.SpareAreaSize) + ((hnand->Info.SpareAreaSize) * num_spare_area_written);
/* Get the address offset */
addressoffset = ARRAY_ADDRESS(&nandaddress, hnand);
/* Send write Spare area command sequence */
*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C;
*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(addressoffset);
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(addressoffset);
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(addressoffset);
/* for 512 and 1 GB devices, 4th cycle is required */
if(hnand->Info.BlockNbr >= 1024)
{
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_4TH_CYCLE(addressoffset);
}
/* Write data to memory */
for(; index < size; index++)
{
*(__IO uint8_t *)deviceaddress = *(uint8_t *)pBuffer++;
}
*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
/* Get tick */
tickstart = HAL_GetTick();
/* Read status until NAND is ready */
while(HAL_NAND_Read_Status(hnand) != NAND_READY)
{
if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
{
return HAL_TIMEOUT;
}
}
/* Increment written spare areas number */
num_spare_area_written++;
/* Decrement spare areas to write */
NumSpareAreaTowrite--;
/* Increment the NAND address */
addressstatus = HAL_NAND_Address_Inc(hnand, &nandaddress);
}
/* Update the NAND controller state */
hnand->State = HAL_NAND_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hnand);
return HAL_OK;
}
/**
* @brief Enables ADC DMA request after last transfer (Multi-ADC mode) and enables ADC peripheral
*
* @note Caution: This function must be used only with the ADC master.
*
* @param hadc: pointer to a ADC_HandleTypeDef structure that contains
* the configuration information for the specified ADC.
* @param pData: Pointer to buffer in which transferred from ADC peripheral to memory will be stored.
* @param Length: The length of data to be transferred from ADC peripheral to memory.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
{
__IO uint32_t counter = 0;
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests));
/* Process locked */
__HAL_LOCK(hadc);
/* Check if ADC peripheral is disabled in order to enable it and wait during
Tstab time the ADC's stabilization */
if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)
{
/* Enable the Peripheral */
__HAL_ADC_ENABLE(hadc);
/* Delay for temperature sensor stabilization time */
/* Compute number of CPU cycles to wait for */
counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000));
while(counter != 0)
{
counter--;
}
}
/* Start conversion if ADC is effectively enabled */
if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON))
{
/* Set ADC state */
/* - Clear state bitfield related to regular group conversion results */
/* - Set state bitfield related to regular group operation */
ADC_STATE_CLR_SET(hadc->State,
HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR,
HAL_ADC_STATE_REG_BUSY);
/* If conversions on group regular are also triggering group injected, */
/* update ADC state. */
if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)
{
ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
}
/* State machine update: Check if an injected conversion is ongoing */
if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
{
/* Reset ADC error code fields related to conversions on group regular */
CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
}
else
{
/* Reset ADC all error code fields */
ADC_CLEAR_ERRORCODE(hadc);
}
/* Process unlocked */
/* Unlock before starting ADC conversions: in case of potential */
/* interruption, to let the process to ADC IRQ Handler. */
__HAL_UNLOCK(hadc);
/* Set the DMA transfer complete callback */
hadc->DMA_Handle->XferCpltCallback = ADC_MultiModeDMAConvCplt;
/* Set the DMA half transfer complete callback */
hadc->DMA_Handle->XferHalfCpltCallback = ADC_MultiModeDMAHalfConvCplt;
/* Set the DMA error callback */
hadc->DMA_Handle->XferErrorCallback = ADC_MultiModeDMAError ;
/* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */
/* start (in case of SW start): */
/* Clear regular group conversion flag and overrun flag */
/* (To ensure of no unknown state from potential previous ADC operations) */
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC);
/* Enable ADC overrun interrupt */
__HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
if (hadc->Init.DMAContinuousRequests != DISABLE)
{
/* Enable the selected ADC DMA request after last transfer */
ADC->CCR |= ADC_CCR_DDS;
}
else
{
/* Disable the selected ADC EOC rising on each regular channel conversion */
ADC->CCR &= ~ADC_CCR_DDS;
}
/* Enable the DMA Stream */
HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&ADC->CDR, (uint32_t)pData, Length);
/* if no external trigger present enable software conversion of regular channels */
if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)
{
/* Enable the selected ADC software conversion for regular group */
hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
}
}
/* Return function status */
return HAL_OK;
}
/**
* @brief NAND memory Block erase
* @param hnand: pointer to a NAND_HandleTypeDef structure that contains
* the configuration information for NAND module.
* @param pAddress : pointer to NAND address structure
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)
{
uint32_t deviceaddress = 0;
uint32_t tickstart = 0;
/* Process Locked */
__HAL_LOCK(hnand);
/* Check the NAND controller state */
if(hnand->State == HAL_NAND_STATE_BUSY)
{
return HAL_BUSY;
}
/* Identify the device address */
if(hnand->Init.NandBank == FMC_NAND_BANK2)
{
deviceaddress = NAND_DEVICE1;
}
else
{
deviceaddress = NAND_DEVICE2;
}
/* Update the NAND controller state */
hnand->State = HAL_NAND_STATE_BUSY;
/* Send Erase block command sequence */
*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_ERASE0;
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
/* for 512 and 1 GB devices, 4th cycle is required */
if(hnand->Info.BlockNbr >= 1024)
{
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_4TH_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
}
*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_ERASE1;
/* Update the NAND controller state */
hnand->State = HAL_NAND_STATE_READY;
/* Get tick */
tickstart = HAL_GetTick();
/* Read status until NAND is ready */
while(HAL_NAND_Read_Status(hnand) != NAND_READY)
{
if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
{
/* Process unlocked */
__HAL_UNLOCK(hnand);
return HAL_TIMEOUT;
}
}
/* Process unlocked */
__HAL_UNLOCK(hnand);
return HAL_OK;
}
/**
* @brief Enables DCMI DMA request and enables DCMI capture
* @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
* the configuration information for DCMI.
* @param DCMI_Mode: DCMI capture mode snapshot or continuous grab.
* @param pData: The destination memory Buffer address (LCD Frame buffer).
* @param Length: The length of capture to be transferred.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef* hdcmi, uint32_t DCMI_Mode, uint32_t pData, uint32_t Length)
{
/* Initialize the second memory address */
uint32_t SecondMemAddress = 0;
/* Check function parameters */
assert_param(IS_DCMI_CAPTURE_MODE(DCMI_Mode));
/* Process Locked */
__HAL_LOCK(hdcmi);
/* Lock the DCMI peripheral state */
hdcmi->State = HAL_DCMI_STATE_BUSY;
/* Check the parameters */
assert_param(IS_DCMI_CAPTURE_MODE(DCMI_Mode));
/* Configure the DCMI Mode */
hdcmi->Instance->CR &= ~(DCMI_CR_CM);
hdcmi->Instance->CR |= (uint32_t)(DCMI_Mode);
/* Set the DMA memory0 conversion complete callback */
hdcmi->DMA_Handle->XferCpltCallback = DCMI_DMAConvCplt;
/* Set the DMA error callback */
hdcmi->DMA_Handle->XferErrorCallback = DCMI_DMAError;
if(Length <= 0xFFFF)
{
/* Enable the DMA Stream */
HAL_DMA_Start_IT(hdcmi->DMA_Handle, (uint32_t)&hdcmi->Instance->DR, (uint32_t)pData, Length);
}
else /* DCMI_DOUBLE_BUFFER Mode */
{
/* Set the DMA memory1 conversion complete callback */
hdcmi->DMA_Handle->XferM1CpltCallback = DCMI_DMAConvCplt;
/* Initialize transfer parameters */
hdcmi->XferCount = 1;
hdcmi->XferSize = Length;
hdcmi->pBuffPtr = pData;
/* Get the number of buffer */
while(hdcmi->XferSize > 0xFFFF)
{
hdcmi->XferSize = (hdcmi->XferSize/2);
hdcmi->XferCount = hdcmi->XferCount*2;
}
/* Update DCMI counter and transfer number*/
hdcmi->XferCount = (hdcmi->XferCount - 2);
hdcmi->XferTransferNumber = hdcmi->XferCount;
/* Update second memory address */
SecondMemAddress = (uint32_t)(pData + (4*hdcmi->XferSize));
/* Start DMA multi buffer transfer */
HAL_DMAEx_MultiBufferStart_IT(hdcmi->DMA_Handle, (uint32_t)&hdcmi->Instance->DR, (uint32_t)pData, SecondMemAddress, hdcmi->XferSize);
}
/* Enable Capture */
DCMI->CR |= DCMI_CR_CAPTURE;
/* Return function status */
return HAL_OK;
}
/**
* @brief Writes a half-word buffer to the NOR memory. This function must be used
only with S29GL128P NOR memory.
* @param hnor: pointer to the NOR handle
* @param uwAddress: NOR memory internal start write address
* @param pData: pointer to source data buffer.
* @param uwBufferSize: Size of the buffer to write
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)
{
uint32_t lastloadedaddress = 0;
uint32_t currentaddress = 0;
uint32_t endaddress = 0;
uint32_t deviceAddress = 0;
/* Process Locked */
__HAL_LOCK(hnor);
/* Check the NOR controller state */
if(hnor->State == HAL_NOR_STATE_BUSY)
{
return HAL_BUSY;
}
/* Select the NOR device address */
if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
{
deviceAddress = NOR_MEMORY_ADRESS1;
}
else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
{
deviceAddress = NOR_MEMORY_ADRESS2;
}
else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
{
deviceAddress = NOR_MEMORY_ADRESS3;
}
else /* FMC_NORSRAM_BANK4 */
{
deviceAddress = NOR_MEMORY_ADRESS4;
}
/* Update the NOR controller state */
hnor->State = HAL_NOR_STATE_BUSY;
/* Initialize variables */
currentaddress = uwAddress;
endaddress = uwAddress + uwBufferSize - 1;
lastloadedaddress = uwAddress;
/* Issue unlock command sequence */
__NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x0555), 0x00AA);
__NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x02AA), 0x0055);
/* Write Buffer Load Command */
__NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, uwAddress), 0x25);
__NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, uwAddress), (uwBufferSize - 1));
/* Load Data into NOR Buffer */
while(currentaddress <= endaddress)
{
/* Store last loaded address & data value (for polling) */
lastloadedaddress = currentaddress;
__NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, currentaddress), *pData++);
currentaddress += 1;
}
__NOR_WRITE(__NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, lastloadedaddress), 0x29);
/* Check the NOR controller state */
hnor->State = HAL_NOR_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hnor);
return HAL_OK;
}
/**
* @brief Configures the selected DAC channel.
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @param sConfig: DAC configuration structure.
* @param Channel: The selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_CHANNEL_1: DAC Channel1 selected
* @arg DAC_CHANNEL_2: DAC Channel2 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel)
{
uint32_t tmpreg1 = 0, tmpreg2 = 0;
uint32_t tickstart = 0;
/* Check the DAC parameters */
assert_param(IS_DAC_TRIGGER(sConfig->DAC_Trigger));
assert_param(IS_DAC_OUTPUT_BUFFER_STATE(sConfig->DAC_OutputBuffer));
assert_param(IS_DAC_CHIP_CONNECTION(sConfig->DAC_ConnectOnChipPeripheral));
assert_param(IS_DAC_TRIMMING(sConfig->DAC_UserTrimming));
if ((sConfig->DAC_UserTrimming) == DAC_TRIMMING_USER)
{
assert_param(IS_DAC_TRIMMINGVALUE(sConfig->DAC_TrimmingValue));
}
assert_param(IS_DAC_SAMPLEANDHOLD(sConfig->DAC_SampleAndHold));
if ((sConfig->DAC_SampleAndHold) == DAC_SAMPLEANDHOLD_ENABLE)
{
assert_param(IS_DAC_SAMPLETIME(sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime));
assert_param(IS_DAC_HOLDTIME(sConfig->DAC_SampleAndHoldConfig.DAC_HoldTime));
assert_param(IS_DAC_REFRESHTIME(sConfig->DAC_SampleAndHoldConfig.DAC_RefreshTime));
}
assert_param(IS_DAC_CHANNEL(Channel));
/* Process locked */
__HAL_LOCK(hdac);
/* Change DAC state */
hdac->State = HAL_DAC_STATE_BUSY;
if(sConfig->DAC_SampleAndHold == DAC_SAMPLEANDHOLD_ENABLE)
/* Sample on old configuration */
{
/* SampleTime */
if (Channel == DAC_CHANNEL_1)
{
/* Get timeout */
tickstart = HAL_GetTick();
/* SHSR1 can be written when BWST1 equals RESET */
while (((hdac->Instance->SR) & DAC_SR_BWST1)!= RESET)
{
/* Check for the Timeout */
if((HAL_GetTick() - tickstart) > TIMEOUT_DAC_CALIBCONFIG)
{
/* Update error code */
SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_TIMEOUT);
/* Change the DMA state */
hdac->State = HAL_DAC_STATE_TIMEOUT;
return HAL_TIMEOUT;
}
}
HAL_Delay(1);
hdac->Instance->SHSR1 = sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime;
}
else /* Channel 2 */
{
/* SHSR2 can be written when BWST2 equals RESET */
while (((hdac->Instance->SR) & DAC_SR_BWST2)!= RESET)
{
/* Check for the Timeout */
if((HAL_GetTick() - tickstart) > TIMEOUT_DAC_CALIBCONFIG)
{
/* Update error code */
SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_TIMEOUT);
/* Change the DMA state */
hdac->State = HAL_DAC_STATE_TIMEOUT;
return HAL_TIMEOUT;
}
}
HAL_Delay(1);
hdac->Instance->SHSR2 = sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime;
}
/* HoldTime */
hdac->Instance->SHHR = (sConfig->DAC_SampleAndHoldConfig.DAC_HoldTime)<<Channel;
/* RefreshTime */
hdac->Instance->SHRR = (sConfig->DAC_SampleAndHoldConfig.DAC_RefreshTime)<<Channel;
}
if(sConfig->DAC_UserTrimming == DAC_TRIMMING_USER)
/* USER TRIMMING */
{
/* Get the DAC CCR value */
tmpreg1 = hdac->Instance->CCR;
/* Clear trimming value */
tmpreg1 &= ~(((uint32_t)(DAC_CCR_OTRIM1)) << Channel);
/* Configure for the selected trimming offset */
tmpreg2 = sConfig->DAC_TrimmingValue;
/* Calculate CCR register value depending on DAC_Channel */
tmpreg1 |= tmpreg2 << Channel;
/* Write to DAC CCR */
hdac->Instance->CCR = tmpreg1;
}
/* else factory trimming is used (factory setting are available at reset)*/
/* SW Nothing has nothing to do */
/* Get the DAC MCR value */
tmpreg1 = hdac->Instance->MCR;
/* Clear DAC_MCR_MODE2_0, DAC_MCR_MODE2_1 and DAC_MCR_MODE2_2 bits */
tmpreg1 &= ~(((uint32_t)(DAC_MCR_MODE1)) << Channel);
/* Configure for the selected DAC channel: mode, buffer output & on chip peripheral connect */
tmpreg2 = (sConfig->DAC_SampleAndHold | sConfig->DAC_OutputBuffer | sConfig->DAC_ConnectOnChipPeripheral);
/* Calculate MCR register value depending on DAC_Channel */
tmpreg1 |= tmpreg2 << Channel;
/* Write to DAC MCR */
hdac->Instance->MCR = tmpreg1;
/* DAC in normal operating mode hence clear DAC_CR_CENx bit */
CLEAR_BIT (hdac->Instance->CR, DAC_CR_CEN1 << Channel);
/* Get the DAC CR value */
tmpreg1 = hdac->Instance->CR;
/* Clear TENx, TSELx, WAVEx and MAMPx bits */
tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1)) << Channel);
/* Configure for the selected DAC channel: trigger */
/* Set TSELx and TENx bits according to DAC_Trigger value */
tmpreg2 = (sConfig->DAC_Trigger);
/* Calculate CR register value depending on DAC_Channel */
tmpreg1 |= tmpreg2 << Channel;
/* Write to DAC CR */
hdac->Instance->CR = tmpreg1;
/* Disable wave generation */
hdac->Instance->CR &= ~(DAC_CR_WAVE1 << Channel);
/* Change DAC state */
hdac->State = HAL_DAC_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hdac);
/* Return function status */
return HAL_OK;
}
/**
* @brief Receive an amount of data (Control Flow) with Interrupt
* @param hspdif: SPDIFRX handle
* @param pData: a 32-bit pointer to the Receive data buffer.
* @param Size: number of data sample (Control Flow) to be received :
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow_IT(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size)
{
uint32_t tickstart = 0U;
if((hspdif->State == HAL_SPDIFRX_STATE_READY) || (hspdif->State == HAL_SPDIFRX_STATE_BUSY_RX))
{
if((pData == NULL ) || (Size == 0U))
{
return HAL_ERROR;
}
/* Process Locked */
__HAL_LOCK(hspdif);
hspdif->pCsBuffPtr = pData;
hspdif->CsXferSize = Size;
hspdif->CsXferCount = Size;
hspdif->ErrorCode = HAL_SPDIFRX_ERROR_NONE;
/* Check if a receive process is ongoing or not */
hspdif->State = HAL_SPDIFRX_STATE_BUSY_CX;
/* Enable the SPDIFRX PE Error Interrupt */
__HAL_SPDIFRX_ENABLE_IT(hspdif, SPDIFRX_IT_PERRIE);
/* Enable the SPDIFRX OVR Error Interrupt */
__HAL_SPDIFRX_ENABLE_IT(hspdif, SPDIFRX_IT_OVRIE);
/* Process Unlocked */
__HAL_UNLOCK(hspdif);
/* Enable the SPDIFRX CSRNE interrupt */
__HAL_SPDIFRX_ENABLE_IT(hspdif, SPDIFRX_IT_CSRNE);
if (((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != SPDIFRX_STATE_SYNC) || ((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != 0x00U))
{
/* Start synchronization */
__HAL_SPDIFRX_SYNC(hspdif);
/* Get tick */
tickstart = HAL_GetTick();
/* Wait until SYNCD flag is set */
if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_SYNCD, RESET, SPDIFRX_TIMEOUT_VALUE, tickstart) != HAL_OK)
{
return HAL_TIMEOUT;
}
/* Start reception */
__HAL_SPDIFRX_RCV(hspdif);
}
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Deactivate an endpoint
* @param hpcd: PCD handle
* @param ep_addr: endpoint address
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
{
PCD_EPTypeDef *ep;
if ((ep_addr & 0x80) == 0x80)
{
ep = &hpcd->IN_ep[ep_addr & 0x7F];
}
else
{
ep = &hpcd->OUT_ep[ep_addr & 0x7F];
}
ep->num = ep_addr & 0x7F;
ep->is_in = (0x80 & ep_addr) != 0;
__HAL_LOCK(hpcd);
if (ep->doublebuffer == 0)
{
if (ep->is_in)
{
PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num);
/* Configure DISABLE status for the Endpoint*/
PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_DIS);
}
else
{
PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num);
/* Configure DISABLE status for the Endpoint*/
PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_DIS);
}
}
/*Double Buffer*/
else
{
if (ep->is_in==0)
{
/* Clear the data toggle bits for the endpoint IN/OUT*/
PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num);
PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num);
/* Reset value of the data toggle bits for the endpoint out*/
PCD_TX_DTOG(hpcd->Instance, ep->num);
PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_DIS);
PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_DIS);
}
else
{
/* Clear the data toggle bits for the endpoint IN/OUT*/
PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num);
PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num);
PCD_RX_DTOG(hpcd->Instance, ep->num);
/* Configure DISABLE status for the Endpoint*/
PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_DIS);
PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_DIS);
}
}
__HAL_UNLOCK(hpcd);
return HAL_OK;
}
/**
* @brief Receive an amount of data (Control Flow) with DMA
* @param hspdif: SPDIFRX handle
* @param pData: a 32-bit pointer to the Receive data buffer.
* @param Size: number of data (Control Flow) sample to be received :
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow_DMA(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size)
{
uint32_t tickstart = 0U;
if((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
if((hspdif->State == HAL_SPDIFRX_STATE_READY) || (hspdif->State == HAL_SPDIFRX_STATE_BUSY_RX))
{
hspdif->pCsBuffPtr = pData;
hspdif->CsXferSize = Size;
hspdif->CsXferCount = Size;
/* Process Locked */
__HAL_LOCK(hspdif);
hspdif->ErrorCode = HAL_SPDIFRX_ERROR_NONE;
hspdif->State = HAL_SPDIFRX_STATE_BUSY_CX;
/* Set the SPDIFRX Rx DMA Half transfer complete callback */
hspdif->hdmaCsRx->XferHalfCpltCallback = SPDIFRX_DMACxHalfCplt;
/* Set the SPDIFRX Rx DMA transfer complete callback */
hspdif->hdmaCsRx->XferCpltCallback = SPDIFRX_DMACxCplt;
/* Set the DMA error callback */
hspdif->hdmaCsRx->XferErrorCallback = SPDIFRX_DMAError;
/* Enable the DMA request */
HAL_DMA_Start_IT(hspdif->hdmaCsRx, (uint32_t)&hspdif->Instance->CSR, (uint32_t)hspdif->pCsBuffPtr, Size);
/* Enable CBDMAEN bit in SPDIFRX CR register for control flow reception*/
hspdif->Instance->CR |= SPDIFRX_CR_CBDMAEN;
if (((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != SPDIFRX_STATE_SYNC) || ((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != 0x00U))
{
/* Start synchronization */
__HAL_SPDIFRX_SYNC(hspdif);
/* Get tick */
tickstart = HAL_GetTick();
/* Wait until SYNCD flag is set */
if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_SYNCD, RESET, SPDIFRX_TIMEOUT_VALUE, tickstart) != HAL_OK)
{
return HAL_TIMEOUT;
}
/* Start reception */
__HAL_SPDIFRX_RCV(hspdif);
}
/* Process Unlocked */
__HAL_UNLOCK(hspdif);
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Initiates and transmits a CAN frame message.
* @param hcan: pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef* hcan)
{
uint32_t transmitmailbox = 5;
uint32_t tmp = 0;
/* Check the parameters */
assert_param(IS_CAN_IDTYPE(hcan->pTxMsg->IDE));
assert_param(IS_CAN_RTR(hcan->pTxMsg->RTR));
assert_param(IS_CAN_DLC(hcan->pTxMsg->DLC));
tmp = hcan->State;
if((tmp == HAL_CAN_STATE_READY) || (tmp == HAL_CAN_STATE_BUSY_RX))
{
/* Process Locked */
__HAL_LOCK(hcan);
/* Select one empty transmit mailbox */
if((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0)
{
transmitmailbox = 0;
}
else if((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1)
{
transmitmailbox = 1;
}
else if((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2)
{
transmitmailbox = 2;
}
else
{
transmitmailbox = CAN_TXSTATUS_NOMAILBOX;
}
if(transmitmailbox != CAN_TXSTATUS_NOMAILBOX)
{
/* Set up the Id */
hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ;
if(hcan->pTxMsg->IDE == CAN_ID_STD)
{
assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId));
hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << 21) | \
hcan->pTxMsg->RTR);
}
else
{
assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId));
hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << 3) | \
hcan->pTxMsg->IDE | \
hcan->pTxMsg->RTR);
}
/* Set up the DLC */
hcan->pTxMsg->DLC &= (uint8_t)0x0000000F;
hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= (uint32_t)0xFFFFFFF0;
hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC;
/* Set up the data field */
hcan->Instance->sTxMailBox[transmitmailbox].TDLR = (((uint32_t)hcan->pTxMsg->Data[3] << 24) |
((uint32_t)hcan->pTxMsg->Data[2] << 16) |
((uint32_t)hcan->pTxMsg->Data[1] << 8) |
((uint32_t)hcan->pTxMsg->Data[0]));
hcan->Instance->sTxMailBox[transmitmailbox].TDHR = (((uint32_t)hcan->pTxMsg->Data[7] << 24) |
((uint32_t)hcan->pTxMsg->Data[6] << 16) |
((uint32_t)hcan->pTxMsg->Data[5] << 8) |
((uint32_t)hcan->pTxMsg->Data[4]));
if(hcan->State == HAL_CAN_STATE_BUSY_RX)
{
/* Change CAN state */
hcan->State = HAL_CAN_STATE_BUSY_TX_RX;
}
else
{
/* Change CAN state */
hcan->State = HAL_CAN_STATE_BUSY_TX;
}
/* Set CAN error code to none */
hcan->ErrorCode = HAL_CAN_ERROR_NONE;
/* Process Unlocked */
__HAL_UNLOCK(hcan);
/* Enable Error warning Interrupt */
__HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG);
/* Enable Error passive Interrupt */
__HAL_CAN_ENABLE_IT(hcan, CAN_IT_EPV);
/* Enable Bus-off Interrupt */
__HAL_CAN_ENABLE_IT(hcan, CAN_IT_BOF);
/* Enable Last error code Interrupt */
__HAL_CAN_ENABLE_IT(hcan, CAN_IT_LEC);
/* Enable Error Interrupt */
__HAL_CAN_ENABLE_IT(hcan, CAN_IT_ERR);
/* Enable Transmit mailbox empty Interrupt */
__HAL_CAN_ENABLE_IT(hcan, CAN_IT_TME);
/* Request transmission */
hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ;
}
}
else
{
return HAL_BUSY;
}
return HAL_OK;
}
/**
* @brief Send data in blocking mode
* @param hcec: CEC handle
* @param DestinationAddress: destination logical address
* @param pData: pointer to input byte data buffer
* @param Size: amount of data to be sent in bytes (without counting the header).
* 0 means only the header is sent (ping operation).
* Maximum TX size is 15 bytes (1 opcode and up to 14 operands).
* @param Timeout: Timeout duration.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CEC_Transmit(CEC_HandleTypeDef *hcec, uint8_t DestinationAddress, uint8_t *pData, uint32_t Size, uint32_t Timeout)
{
uint8_t temp = 0;
uint32_t tempisr = 0;
uint32_t tickstart = 0;
if((hcec->State == HAL_CEC_STATE_READY) && (__HAL_CEC_GET_TRANSMISSION_START_FLAG(hcec) == RESET))
{
hcec->ErrorCode = HAL_CEC_ERROR_NONE;
if((pData == NULL ) && (Size > 0))
{
hcec->State = HAL_CEC_STATE_ERROR;
return HAL_ERROR;
}
assert_param(IS_CEC_ADDRESS(DestinationAddress));
assert_param(IS_CEC_MSGSIZE(Size));
/* Process Locked */
__HAL_LOCK(hcec);
hcec->State = HAL_CEC_STATE_BUSY_TX;
hcec->TxXferCount = Size;
/* case no data to be sent, sender is only pinging the system */
if (Size == 0)
{
/* Set TX End of Message (TXEOM) bit, must be set before writing data to TXDR */
__HAL_CEC_LAST_BYTE_TX_SET(hcec);
}
/* send header block */
temp = ((uint32_t)hcec->Init.InitiatorAddress << CEC_INITIATOR_LSB_POS) | DestinationAddress;
hcec->Instance->TXDR = temp;
/* Set TX Start of Message (TXSOM) bit */
__HAL_CEC_FIRST_BYTE_TX_SET(hcec);
while (hcec->TxXferCount > 0)
{
hcec->TxXferCount--;
tickstart = HAL_GetTick();
while(HAL_IS_BIT_CLR(hcec->Instance->ISR, CEC_FLAG_TXBR))
{
if(Timeout != HAL_MAX_DELAY)
{
if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
{
hcec->State = HAL_CEC_STATE_TIMEOUT;
/* Process Unlocked */
__HAL_UNLOCK(hcec);
return HAL_TIMEOUT;
}
}
/* check whether error occurred while waiting for TXBR to be set:
* has Tx underrun occurred ?
* has Tx error occurred ?
* has Tx Missing Acknowledge error occurred ?
* has Arbitration Loss error occurred ? */
tempisr = hcec->Instance->ISR;
if ((tempisr & (CEC_FLAG_TXUDR|CEC_FLAG_TXERR|CEC_FLAG_TXACKE|CEC_FLAG_ARBLST)) != 0)
{
/* copy ISR for error handling purposes */
hcec->ErrorCode = tempisr;
/* clear all error flags by default */
__HAL_CEC_CLEAR_FLAG(hcec, (CEC_FLAG_TXUDR|CEC_FLAG_TXERR|CEC_FLAG_TXACKE|CEC_FLAG_ARBLST));
hcec->State = HAL_CEC_STATE_ERROR;
__HAL_UNLOCK(hcec);
return HAL_ERROR;
}
}
/* TXBR to clear BEFORE writing TXDR register */
__HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXBR);
if (hcec->TxXferCount == 0)
{
/* if last byte transmission, set TX End of Message (TXEOM) bit */
__HAL_CEC_LAST_BYTE_TX_SET(hcec);
}
hcec->Instance->TXDR = *pData++;
/* error check after TX byte write up */
tempisr = hcec->Instance->ISR;
if ((tempisr & (CEC_FLAG_TXUDR|CEC_FLAG_TXERR|CEC_FLAG_TXACKE|CEC_FLAG_ARBLST)) != 0)
{
/* copy ISR for error handling purposes */
hcec->ErrorCode = tempisr;
/* clear all error flags by default */
__HAL_CEC_CLEAR_FLAG(hcec, (CEC_FLAG_TXUDR|CEC_FLAG_TXERR|CEC_FLAG_TXACKE|CEC_FLAG_ARBLST));
hcec->State = HAL_CEC_STATE_ERROR;
__HAL_UNLOCK(hcec);
return HAL_ERROR;
}
} /* end while (while (hcec->TxXferCount > 0)) */
/* if no error up to this point, check that transmission is
* complete, that is wait until TXEOM is reset */
tickstart = HAL_GetTick();
while (HAL_IS_BIT_SET(hcec->Instance->CR, CEC_CR_TXEOM))
{
if(Timeout != HAL_MAX_DELAY)
{
if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
{
hcec->State = HAL_CEC_STATE_ERROR;
__HAL_UNLOCK(hcec);
return HAL_TIMEOUT;
}
}
}
/* Final error check once all bytes have been transmitted */
tempisr = hcec->Instance->ISR;
if ((tempisr & (CEC_FLAG_TXUDR|CEC_FLAG_TXERR|CEC_FLAG_TXACKE)) != 0)
{
/* copy ISR for error handling purposes */
hcec->ErrorCode = tempisr;
/* clear all error flags by default */
__HAL_CEC_CLEAR_FLAG(hcec, (CEC_FLAG_TXUDR|CEC_FLAG_TXERR|CEC_FLAG_TXACKE));
hcec->State = HAL_CEC_STATE_ERROR;
__HAL_UNLOCK(hcec);
return HAL_ERROR;
}
hcec->State = HAL_CEC_STATE_READY;
__HAL_UNLOCK(hcec);
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}