static void bcmgenet_moca_phy_setup(struct bcmgenet_priv *priv) { u32 reg; /* Speed settings are set in bcmgenet_mii_setup() */ reg = bcmgenet_sys_readl(priv, SYS_PORT_CTRL); reg |= LED_ACT_SOURCE_MAC; bcmgenet_sys_writel(priv, reg, SYS_PORT_CTRL); }
static void bcmgenet_moca_phy_setup(struct bcmgenet_priv *priv) { u32 reg; if (!GENET_IS_V5(priv)) { /* Speed settings are set in bcmgenet_mii_setup() */ reg = bcmgenet_sys_readl(priv, SYS_PORT_CTRL); reg |= LED_ACT_SOURCE_MAC; bcmgenet_sys_writel(priv, reg, SYS_PORT_CTRL); } if (priv->hw_params->flags & GENET_HAS_MOCA_LINK_DET) fixed_phy_set_link_update(priv->dev->phydev, bcmgenet_fixed_phy_link_update); }
int bcmgenet_mii_config(struct net_device *dev, bool init) { struct bcmgenet_priv *priv = netdev_priv(dev); struct phy_device *phydev = priv->phydev; struct device *kdev = &priv->pdev->dev; const char *phy_name = NULL; u32 id_mode_dis = 0; u32 port_ctrl; u32 reg; priv->ext_phy = !phy_is_internal(priv->phydev) && (priv->phy_interface != PHY_INTERFACE_MODE_MOCA); if (phy_is_internal(priv->phydev)) priv->phy_interface = PHY_INTERFACE_MODE_NA; switch (priv->phy_interface) { case PHY_INTERFACE_MODE_NA: case PHY_INTERFACE_MODE_MOCA: /* Irrespective of the actually configured PHY speed (100 or * 1000) GENETv4 only has an internal GPHY so we will just end * up masking the Gigabit features from what we support, not * switching to the EPHY */ if (GENET_IS_V4(priv)) port_ctrl = PORT_MODE_INT_GPHY; else port_ctrl = PORT_MODE_INT_EPHY; bcmgenet_sys_writel(priv, port_ctrl, SYS_PORT_CTRL); if (phy_is_internal(priv->phydev)) { phy_name = "internal PHY"; bcmgenet_internal_phy_setup(dev); } else if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) { phy_name = "MoCA"; bcmgenet_moca_phy_setup(priv); } break; case PHY_INTERFACE_MODE_MII: phy_name = "external MII"; phydev->supported &= PHY_BASIC_FEATURES; bcmgenet_sys_writel(priv, PORT_MODE_EXT_EPHY, SYS_PORT_CTRL); break; case PHY_INTERFACE_MODE_REVMII: phy_name = "external RvMII"; /* of_mdiobus_register took care of reading the 'max-speed' * PHY property for us, effectively limiting the PHY supported * capabilities, use that knowledge to also configure the * Reverse MII interface correctly. */ if ((priv->phydev->supported & PHY_BASIC_FEATURES) == PHY_BASIC_FEATURES) port_ctrl = PORT_MODE_EXT_RVMII_25; else port_ctrl = PORT_MODE_EXT_RVMII_50; bcmgenet_sys_writel(priv, port_ctrl, SYS_PORT_CTRL); break; case PHY_INTERFACE_MODE_RGMII: /* RGMII_NO_ID: TXC transitions at the same time as TXD * (requires PCB or receiver-side delay) * RGMII: Add 2ns delay on TXC (90 degree shift) * * ID is implicitly disabled for 100Mbps (RG)MII operation. */ id_mode_dis = BIT(16); /* fall through */ case PHY_INTERFACE_MODE_RGMII_TXID: if (id_mode_dis) phy_name = "external RGMII (no delay)"; else phy_name = "external RGMII (TX delay)"; reg = bcmgenet_ext_readl(priv, EXT_RGMII_OOB_CTRL); reg |= RGMII_MODE_EN | id_mode_dis; bcmgenet_ext_writel(priv, reg, EXT_RGMII_OOB_CTRL); bcmgenet_sys_writel(priv, PORT_MODE_EXT_GPHY, SYS_PORT_CTRL); break; default: dev_err(kdev, "unknown phy mode: %d\n", priv->phy_interface); return -EINVAL; } if (init) dev_info(kdev, "configuring instance for %s\n", phy_name); return 0; }