Exemple #1
0
int main() {
    irq_history = 0;

    // Enable Wake-Up/Soft-Reset/GOCEP IRQs
    *NVIC_ISER = (0x1 << IRQ_WAKEUP) | (0x1 << IRQ_SOFT_RESET) | (0x1 << IRQ_GOCEP);

    // Initialization Sequence
    if (!get_flag(FLAG_ENUM)) { 
        initialization();
    }

    arb_debug_reg(0x20, cyc_num);

    // Testing Sequence
    if      (cyc_num == 0)  cycle0();
    else if (cyc_num == 1)  cycle1();
    else if (cyc_num == 2)  cycle2();
    else if (cyc_num == 3)  cycle3();
    else if (cyc_num == 4)  cycle4();
    else if (cyc_num == 5)  cycle5();
    else if (cyc_num == 6)  cycle6();
    else if (cyc_num == 7)  cycle7();
    else if (cyc_num == 8)  cycle8();
    else if (cyc_num == 9)  cycle9();
    else if (cyc_num == 10) cycle10();
    else if (cyc_num == 11) cycle11();
    else cyc_num = 999;

    arb_debug_reg(0x2F, cyc_num);

    // Sleep/Wakeup OR Terminate operation
    if (cyc_num == 999) *REG_CHIP_ID = 0xFFFFFF; // This will stop the verilog sim.
    else {
        cyc_num++;
        set_wakeup_timer(5, 1, 1);
        mbus_sleep_all();
    }

    while(1){  //Never Quit (should not come here.)
        arb_debug_reg(0xFF, 0xDEADBEEF);
        asm("nop;"); 
    }

    return 1;
}
Exemple #2
0
int main() {
    //Initialize Interrupts
    disable_all_irq();

    if (*REG_CHIP_ID != 0x1234) while(1);
  
    // Initialization Sequence
    if (enumerated != 0xDEADBEEF) { 
        initialization();
    }

    // Testing Sequence
    if      (cyc_num == 0)  cycle0();
    else if (cyc_num == 1)  cycle1();
    else if (cyc_num == 2)  cycle2();
    else if (cyc_num == 3)  cycle3();
    else if (cyc_num == 4)  cycle4();
    else if (cyc_num == 5)  cycle5();
    else if (cyc_num == 6)  cycle6();
    else if (cyc_num == 7)  cycle7();
    else if (cyc_num == 8)  cycle8();
    else if (cyc_num == 9)  cycle9();
    else if (cyc_num == 10) cycle10();
    else if (cyc_num == 11) cycle11();
    else cyc_num = 999;

    // Sleep/Wakeup OR Terminate operation
    if (cyc_num == 999) *REG_CHIP_ID = 0xFFFF; // This will stop the verilog sim.
    else {
        cyc_num++;
        //set_wakeup_timer(5, 1, 1);
        *WUPT_RESET = 0x1;
        mbus_sleep_all();
    }

    while(1){  //Never Quit (should not come here.)
        arb_debug_reg (0xDEADBEEF);
        asm("nop;"); 
    }

    return 1;
}
Exemple #3
0
	void graph_test() {
		Graph g("simple-graph.txt");
		
		// testy zliczania dlugosci cyklu
		std::vector<int> cycle1(g.V());
		cycle1[0] = 1; cycle1[1] = 0; cycle1[2] = 2; cycle1[3] = 3;
		assert(g.hamiltonLength(cycle1) == 12); // 2 + 2 + 5 + 3

		std::vector<int> cycle2(g.V());
		cycle2[0] = 2; cycle2[1] = 1; cycle2[2] = 3; cycle2[3] = 0; 
		assert(g.hamiltonLength(cycle2) == 9); // 1 + 2 + 4 + 2

		// testy konstruktorow kopiujacych i operatora przypisania
		Graph g2(g);
		assert(g2.hamiltonLength(cycle1) == 12);
		assert(g2.hamiltonLength(cycle2) == 9);

		Graph g3(10);
		g3 = g;
		assert(g3.hamiltonLength(cycle1) == 12);
		assert(g3.hamiltonLength(cycle2) == 9);
	}