static struct pipe_resource *createSimpleTexture(struct pipe_screen *screen, struct pipe_context *pipe)
{
struct pipe_resource *tex_resource = fbdemo_create_2d(screen, PIPE_BIND_SAMPLER_VIEW, PIPE_FORMAT_L8_UNORM, TEX_WIDTH, TEX_HEIGHT, 0);
uint8_t pixels[TEX_HEIGHT][TEX_WIDTH];
for(int y=0; y<TEX_HEIGHT; ++y)
{
for(int x=0; x<TEX_WIDTH; ++x)
{
float xx = (float)x / (float)(TEX_WIDTH-1) * 2.0f - 1.0f;
float yy = (float)y / (float)(TEX_HEIGHT-1) * 2.0f - 1.0f;
//float vv = (0.25*xx*xx*yy*yy);
//float vv = (sin(xx*2.0*M_PI*2.0)*sin(yy*2.0*M_PI*2.0) + 1.0f) / 2.0f;
float vv = sin(xx*2.0*M_PI*2.0)*sin(yy*2.0*M_PI*2.0);
vv = vv * (1.0 - yy * yy); /* flatten over poles */
pixels[y][x] = etna_cfloat_to_uint8(vv);
printf("%3i ", pixels[y][x]);
}
printf("\n");
}
etna_pipe_inline_write(pipe, tex_resource, 0, 0, &pixels[0][0], TEX_WIDTH*TEX_HEIGHT);
return tex_resource;
}
static void *etna_pipe_create_depth_stencil_alpha_state(struct pipe_context *pipe,
const struct pipe_depth_stencil_alpha_state *dsa_p)
{
//struct etna_pipe_context *priv = etna_pipe_context(pipe);
struct compiled_depth_stencil_alpha_state *cs = CALLOC_STRUCT(compiled_depth_stencil_alpha_state);
struct pipe_depth_stencil_alpha_state dsa = *dsa_p;
/* XXX does stencil[0] / stencil[1] order depend on rs->front_ccw? */
bool early_z = true;
bool disable_zs = !dsa.depth.writemask;
int i;
/* Set operations to KEEP if write mask is 0.
* When we don't do this, the depth buffer is written for the entire primitive instead of
* just where the stencil condition holds (GC600 rev 0x0019, without feature CORRECT_STENCIL).
* Not sure if this is a hardware bug or just a strange edge case.
*/
for(i=0; i<2; ++i)
{
if(dsa.stencil[i].writemask == 0)
{
dsa.stencil[i].fail_op = dsa.stencil[i].zfail_op = dsa.stencil[i].zpass_op = PIPE_STENCIL_OP_KEEP;
}
}
/* Determine whether to enable early z reject. Don't enable it when any of
* the stencil-modifying functions is used. */
if(dsa.stencil[0].enabled)
{
if(dsa.stencil[0].fail_op != PIPE_STENCIL_OP_KEEP ||
dsa.stencil[0].zfail_op != PIPE_STENCIL_OP_KEEP ||
dsa.stencil[0].zpass_op != PIPE_STENCIL_OP_KEEP)
{
disable_zs = early_z = false;
}
else if(dsa.stencil[1].enabled)
{
if(dsa.stencil[1].fail_op != PIPE_STENCIL_OP_KEEP ||
dsa.stencil[1].zfail_op != PIPE_STENCIL_OP_KEEP ||
dsa.stencil[1].zpass_op != PIPE_STENCIL_OP_KEEP)
{
disable_zs = early_z = false;
}
}
}
/* compare funcs have 1 to 1 mapping */
cs->PE_DEPTH_CONFIG =
VIVS_PE_DEPTH_CONFIG_DEPTH_FUNC(dsa.depth.enabled ? dsa.depth.func : PIPE_FUNC_ALWAYS) |
(dsa.depth.writemask ? VIVS_PE_DEPTH_CONFIG_WRITE_ENABLE : 0) |
(early_z ? VIVS_PE_DEPTH_CONFIG_EARLY_Z : 0) |
(disable_zs ? VIVS_PE_DEPTH_CONFIG_DISABLE_ZS : 0);
cs->PE_ALPHA_OP =
(dsa.alpha.enabled ? VIVS_PE_ALPHA_OP_ALPHA_TEST : 0) |
VIVS_PE_ALPHA_OP_ALPHA_FUNC(dsa.alpha.func) |
VIVS_PE_ALPHA_OP_ALPHA_REF(etna_cfloat_to_uint8(dsa.alpha.ref_value));
cs->PE_STENCIL_OP =
VIVS_PE_STENCIL_OP_FUNC_FRONT(dsa.stencil[0].func) |
VIVS_PE_STENCIL_OP_FUNC_BACK(dsa.stencil[1].func) |
VIVS_PE_STENCIL_OP_FAIL_FRONT(translate_stencil_op(dsa.stencil[0].fail_op)) |
VIVS_PE_STENCIL_OP_FAIL_BACK(translate_stencil_op(dsa.stencil[1].fail_op)) |
VIVS_PE_STENCIL_OP_DEPTH_FAIL_FRONT(translate_stencil_op(dsa.stencil[0].zfail_op)) |
VIVS_PE_STENCIL_OP_DEPTH_FAIL_BACK(translate_stencil_op(dsa.stencil[1].zfail_op)) |
VIVS_PE_STENCIL_OP_PASS_FRONT(translate_stencil_op(dsa.stencil[0].zpass_op)) |
VIVS_PE_STENCIL_OP_PASS_BACK(translate_stencil_op(dsa.stencil[1].zpass_op));
cs->PE_STENCIL_CONFIG =
translate_stencil_mode(dsa.stencil[0].enabled, dsa.stencil[1].enabled) |
VIVS_PE_STENCIL_CONFIG_MASK_FRONT(dsa.stencil[0].valuemask) |
VIVS_PE_STENCIL_CONFIG_WRITE_MASK(dsa.stencil[0].writemask);
/* XXX back masks in VIVS_PE_DEPTH_CONFIG_EXT? */
/* XXX VIVS_PE_STENCIL_CONFIG_REF_FRONT comes from pipe_stencil_ref */
/* XXX does alpha/stencil test affect PE_COLOR_FORMAT_OVERWRITE? */
return cs;
}