void lcd_show_board_info(void) { ulong dram_size, nand_size; int i; char temp[32]; if (has_lcdc()) { lcd_printf("%s\n", U_BOOT_VERSION); lcd_printf("(C) 2012 ATMEL Corp\n"); lcd_printf("[email protected]\n"); lcd_printf("%s CPU at %s MHz\n", get_cpu_name(), strmhz(temp, get_cpu_clk_rate())); dram_size = 0; for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) dram_size += gd->bd->bi_dram[i].size; nand_size = 0; for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) nand_size += get_nand_dev_by_index(i)->size; lcd_printf(" %ld MB SDRAM, %ld MB NAND\n", dram_size >> 20, nand_size >> 20); } }
/* * The legacy NAND code saved the environment in the first NAND device i.e., * nand_dev_desc + 0. This is also the behaviour using the new NAND code. */ static int writeenv(size_t offset, u_char *buf) { size_t end = offset + CONFIG_ENV_RANGE; size_t amount_saved = 0; size_t blocksize, len; struct mtd_info *mtd; u_char *char_ptr; mtd = get_nand_dev_by_index(0); if (!mtd) return 1; blocksize = mtd->erasesize; len = min(blocksize, (size_t)CONFIG_ENV_SIZE); while (amount_saved < CONFIG_ENV_SIZE && offset < end) { if (nand_block_isbad(mtd, offset)) { offset += blocksize; } else { char_ptr = &buf[amount_saved]; if (nand_write(mtd, offset, &len, char_ptr)) return 1; offset += blocksize; amount_saved += len; } } if (amount_saved != CONFIG_ENV_SIZE) return 1; return 0; }
static int fb_nand_lookup(const char *partname, struct mtd_info **mtd, struct part_info **part) { struct mtd_device *dev; int ret; u8 pnum; ret = mtdparts_init(); if (ret) { error("Cannot initialize MTD partitions\n"); fastboot_fail("cannot init mtdparts"); return ret; } ret = find_dev_and_part(partname, &dev, &pnum, part); if (ret) { error("cannot find partition: '%s'", partname); fastboot_fail("cannot find partition"); return ret; } if (dev->id->type != MTD_DEV_TYPE_NAND) { error("partition '%s' is not stored on a NAND device", partname); fastboot_fail("not a NAND device"); return -EINVAL; } *mtd = get_nand_dev_by_index(dev->id->num); return 0; }
static int splash_nand_read_raw(u32 bmp_load_addr, int offset, size_t read_size) { struct mtd_info *mtd = get_nand_dev_by_index(nand_curr_device); return nand_read_skip_bad(mtd, offset, &read_size, NULL, mtd->size, (u_char *)bmp_load_addr); }
int at91_video_show_board_info(void) { ulong dram_size, nand_size; int i; u32 len = 0; char buf[255]; char *corp = "2017 Microchip Technology Inc.\n"; char temp[32]; struct udevice *dev, *con; const char *s; vidinfo_t logo_info; int ret; len += sprintf(&buf[len], "%s\n", U_BOOT_VERSION); memcpy(&buf[len], corp, strlen(corp)); len += strlen(corp); len += sprintf(&buf[len], "%s CPU at %s MHz\n", get_cpu_name(), strmhz(temp, get_cpu_clk_rate())); dram_size = 0; for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) dram_size += gd->bd->bi_dram[i].size; nand_size = 0; #ifdef CONFIG_NAND_ATMEL for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) nand_size += get_nand_dev_by_index(i)->size; #endif len += sprintf(&buf[len], "%ld MB SDRAM, %ld MB NAND\n", dram_size >> 20, nand_size >> 20); ret = uclass_get_device(UCLASS_VIDEO, 0, &dev); if (ret) return ret; microchip_logo_info(&logo_info); ret = video_bmp_display(dev, logo_info.logo_addr, logo_info.logo_x_offset, logo_info.logo_y_offset, false); if (ret) return ret; ret = uclass_get_device(UCLASS_VIDEO_CONSOLE, 0, &con); if (ret) return ret; vidconsole_position_cursor(con, 0, logo_info.logo_height); for (s = buf, i = 0; i < len; s++, i++) vidconsole_put_char(con, *s); return 0; }
static int erase_and_write_env(const struct nand_env_location *location, u_char *env_new) { struct mtd_info *mtd; int ret = 0; mtd = get_nand_dev_by_index(0); if (!mtd) return 1; printf("Erasing %s...\n", location->name); if (nand_erase_opts(mtd, &location->erase_opts)) return 1; printf("Writing to %s... ", location->name); ret = writeenv(location->erase_opts.offset, env_new); puts(ret ? "FAILED!\n" : "OK\n"); return ret; }
static int load_devicetree(void) { int rc; loff_t dtbsize; u32 dtbaddr = env_get_ulong("dtbaddr", 16, 0UL); if (dtbaddr == 0) { printf("%s: don't have a valid <dtbaddr> in env!\n", __func__); return -1; } #ifdef CONFIG_NAND dtbsize = 0x20000; rc = nand_read_skip_bad(get_nand_dev_by_index(0), 0x40000, (size_t *)&dtbsize, NULL, 0x20000, (u_char *)dtbaddr); #else char *dtbname = env_get("dtb"); char *dtbdev = env_get("dtbdev"); char *dtbpart = env_get("dtbpart"); if (!dtbdev || !dtbpart || !dtbname) { printf("%s: <dtbdev>/<dtbpart>/<dtb> missing.\n", __func__); return -1; } if (fs_set_blk_dev(dtbdev, dtbpart, FS_TYPE_EXT)) { puts("load_devicetree: set_blk_dev failed.\n"); return -1; } rc = fs_read(dtbname, (u32)dtbaddr, 0, 0, &dtbsize); #endif if (rc == 0) { gd->fdt_blob = (void *)dtbaddr; gd->fdt_size = dtbsize; debug("loaded %d bytes of dtb onto 0x%08x\n", (u32)dtbsize, (u32)gd->fdt_blob); return dtbsize; } printf("%s: load dtb failed!\n", __func__); return -1; }
void cs4340_upload_firmware(struct phy_device *phydev) { char line_temp[0x50] = {0}; char reg_addr[0x50] = {0}; char reg_data[0x50] = {0}; int i, line_cnt = 0, column_cnt = 0; struct cortina_reg_config fw_temp; char *addr = NULL; #if defined(CONFIG_SYS_CORTINA_FW_IN_NOR) || \ defined(CONFIG_SYS_CORTINA_FW_IN_REMOTE) addr = (char *)CONFIG_CORTINA_FW_ADDR; #elif defined(CONFIG_SYS_CORTINA_FW_IN_NAND) int ret; size_t fw_length = CONFIG_CORTINA_FW_LENGTH; addr = malloc(CONFIG_CORTINA_FW_LENGTH); ret = nand_read(get_nand_dev_by_index(0), (loff_t)CONFIG_CORTINA_FW_ADDR, &fw_length, (u_char *)addr); if (ret == -EUCLEAN) { printf("NAND read of Cortina firmware at 0x%x failed %d\n", CONFIG_CORTINA_FW_ADDR, ret); } #elif defined(CONFIG_SYS_CORTINA_FW_IN_SPIFLASH) int ret; struct spi_flash *ucode_flash; addr = malloc(CONFIG_CORTINA_FW_LENGTH); ucode_flash = spi_flash_probe(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS, CONFIG_ENV_SPI_MAX_HZ, CONFIG_ENV_SPI_MODE); if (!ucode_flash) { puts("SF: probe for Cortina ucode failed\n"); } else { ret = spi_flash_read(ucode_flash, CONFIG_CORTINA_FW_ADDR, CONFIG_CORTINA_FW_LENGTH, addr); if (ret) puts("SF: read for Cortina ucode failed\n"); spi_flash_free(ucode_flash); } #elif defined(CONFIG_SYS_CORTINA_FW_IN_MMC) int dev = CONFIG_SYS_MMC_ENV_DEV; u32 cnt = CONFIG_CORTINA_FW_LENGTH / 512; u32 blk = CONFIG_CORTINA_FW_ADDR / 512; struct mmc *mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV); if (!mmc) { puts("Failed to find MMC device for Cortina ucode\n"); } else { addr = malloc(CONFIG_CORTINA_FW_LENGTH); printf("MMC read: dev # %u, block # %u, count %u ...\n", dev, blk, cnt); mmc_init(mmc); (void)mmc->block_dev.block_read(&mmc->block_dev, blk, cnt, addr); } #endif while (*addr != 'Q') { i = 0; while (*addr != 0x0a) { line_temp[i++] = *addr++; if (0x50 < i) { printf("Not found Cortina PHY ucode at 0x%p\n", (char *)CONFIG_CORTINA_FW_ADDR); return; } } addr++; /* skip '\n' */ line_cnt++; column_cnt = i; line_temp[column_cnt] = '\0'; if (CONFIG_CORTINA_FW_LENGTH < line_cnt) return; for (i = 0; i < column_cnt; i++) { if (isspace(line_temp[i++])) break; } memcpy(reg_addr, line_temp, i); memcpy(reg_data, &line_temp[i], column_cnt - i); strim(reg_addr); strim(reg_data); fw_temp.reg_addr = (simple_strtoul(reg_addr, NULL, 0)) & 0xffff; fw_temp.reg_value = (simple_strtoul(reg_data, NULL, 0)) & 0xffff; phy_write(phydev, 0x00, fw_temp.reg_addr, fw_temp.reg_value); } }