/* * mode : master read or master write * rd : 1 read, 0 write */ static int i2c_message_start(unsigned int addr, unsigned int rd) { unsigned long i; unsigned long iiccon; unsigned long iicstat = 0; iicstat |= 1 << 4; // enable output if (rd) { iicstat |= MASTER_RECEIVE_MODE; addr |= 1; } else { iicstat |= MASTER_SEND_MODE; addr &= ~(1); } i2c_enable_ack(); iiccon = IICCON; IICSTAT = iicstat; IICDS = addr; // set addr for (i = 0; i < 50; i++) // wait for addr signal out ; IICCON = iiccon; iicstat |= (1 << 5); IICSTAT = iicstat; // generate start signal }
/* * Interrupt handler for I2C error conditions. Aborts any pending I2C * transactions. */ void _i2c_irq_error_handler(i2c_dev *dev) { I2C_CRUMB(ERROR_ENTRY, dev->regs->SR1, dev->regs->SR2); dev->error_flags = dev->regs->SR1 & (I2C_SR1_BERR | I2C_SR1_ARLO | I2C_SR1_AF | I2C_SR1_OVR); /* Are we in slave mode? */ if ((dev->regs->SR2 & I2C_SR2_MSL) != I2C_SR2_MSL) { /* Check to see if the master device did a NAK on the last bit * This is perfectly valid for a master to do this on the bus. * We ignore this. Any further error processing takes us into dead * loop waiting for the stop condition that will never arrive */ if (dev->regs->SR1 & I2C_SR1_AF) { /* Clear flags */ dev->regs->SR1 = 0; dev->regs->SR2 = 0; /* We need to write something to CR1 to clear the flag. * This isn't really mentioned but seems important */ i2c_enable_ack(dev); if (dev->state == I2C_STATE_SL_RX && dev->config_flags & I2C_SLAVE_USE_RX_BUFFER && dev->i2c_slave_msg->xferred > 0) { /* Call the callback with the contents of the data */ if (dev->i2c_slave_recv_callback != NULL) (*(dev->i2c_slave_recv_callback))(dev->i2c_slave_msg); } dev->state = I2C_STATE_IDLE; return; } /* Catch any other strange errors while in slave mode. * I have seen BERR caused by an over fast master device * as well as several overflows and arbitration failures. * We are going to reset SR flags and carry on at this point which * is not the best thing to do, but stops the bus locking up completely * If we carry on below and send the stop bit, the code spins forever */ /* Clear flags */ dev->regs->SR1 = 0; dev->regs->SR2 = 0; dev->state = I2C_STATE_IDLE; return; } /* Clear flags */ dev->regs->SR1 = 0; dev->regs->SR2 = 0; i2c_stop_condition(dev); i2c_disable_irq(dev, I2C_IRQ_BUFFER | I2C_IRQ_EVENT | I2C_IRQ_ERROR); dev->state = I2C_STATE_ERROR; }
static uint32_t i2c_read(uint8_t reg) { // while ((I2C_SR2(i2c) & I2C_SR2_BUSY)) { // } i2c_send_start(I2C_PORT); /* Wait for master mode selected */ while (!((I2C_SR1(I2C_PORT) & I2C_SR1_SB) & (I2C_SR2(I2C_PORT) & (I2C_SR2_MSL | I2C_SR2_BUSY)))); i2c_send_7bit_address(I2C_PORT, SLAVE_ADDRESS, I2C_WRITE); /* Waiting for address is transferred. */ while (!(I2C_SR1(I2C_PORT) & I2C_SR1_ADDR)); /* Cleaning ADDR condition sequence. */ uint32_t reg32 = I2C_SR2(I2C_PORT); (void) reg32; /* unused */ /* Common stuff ABOVE HERE */ i2c_send_data(I2C_PORT, reg); while (!(I2C_SR1(I2C_PORT) & (I2C_SR1_BTF))); i2c_send_start(I2C_PORT); /* Wait for master mode selected */ while (!((I2C_SR1(I2C_PORT) & I2C_SR1_SB) & (I2C_SR2(I2C_PORT) & (I2C_SR2_MSL | I2C_SR2_BUSY)))); i2c_send_7bit_address(I2C_PORT, SLAVE_ADDRESS, I2C_READ); /* Waiting for address is transferred. */ while (!(I2C_SR1(I2C_PORT) & I2C_SR1_ADDR)); i2c_disable_ack(I2C_PORT); /* Cleaning ADDR condition sequence. */ reg32 = I2C_SR2(I2C_PORT); (void) reg32; /* unused */ i2c_send_stop(I2C_PORT); while (!(I2C_SR1(I2C_PORT) & I2C_SR1_RxNE)); uint32_t result = i2c_get_data(I2C_PORT); i2c_enable_ack(I2C_PORT); I2C_SR1(I2C_PORT) &= ~I2C_SR1_AF; return result; }
/** * @brief Initialize an I2C device as bus master * @param dev Device to enable * @param flags Bitwise or of the following I2C options: * I2C_FAST_MODE: 400 khz operation, * I2C_DUTY_16_9: 16/9 Tlow/Thigh duty cycle (only applicable for * fast mode), * I2C_BUS_RESET: Reset the bus and clock out any hung slaves on * initialization, * I2C_10BIT_ADDRESSING: Enable 10-bit addressing, * I2C_REMAP: (deprecated, STM32F1 only) Remap I2C1 to SCL/PB8 * SDA/PB9. */ void i2c_master_enable(i2c_dev *dev, uint32 flags) { /* PE must be disabled to configure the device */ ASSERT(!(dev->regs->CR1 & I2C_CR1_PE)); /* Ugh */ _i2c_handle_remap(dev, flags); /* Reset the bus. Clock out any hung slaves. */ if (flags & I2C_BUS_RESET) { i2c_bus_reset(dev); } /* Turn on clock and set GPIO modes */ i2c_init(dev); i2c_config_gpios(dev); /* Configure clock and rise time */ set_ccr_trise(dev, flags); /* Enable event and buffer interrupts */ nvic_irq_enable(dev->ev_nvic_line); nvic_irq_enable(dev->er_nvic_line); i2c_enable_irq(dev, I2C_IRQ_EVENT | I2C_IRQ_BUFFER | I2C_IRQ_ERROR); /* Configure the slave unit */ if (flags & I2C_SLAVE_DUAL_ADDRESS) { i2c_slave_dual_address_enable(dev); } if (flags & I2C_SLAVE_GENERAL_CALL) { i2c_slave_general_call_enable(dev); } /* store all of the flags */ dev->config_flags = flags; /* Make it go! */ i2c_peripheral_enable(dev); i2c_enable_ack(dev); dev->state = I2C_STATE_IDLE; }
static void i2c_init(void) { /* i2c control lines */ rcc_periph_clock_enable(RCC_GPIOB); gpio_mode_setup(GPIOB, GPIO_MODE_AF, GPIO_PUPD_PULLUP, GPIO6 | GPIO7); gpio_set_output_options(GPIOB, GPIO_OTYPE_OD, GPIO_OSPEED_100MHZ /* GPIO_OSPEED_2MHZ */, GPIO6 | GPIO7); gpio_set_af(GPIOB, GPIO_AF4, GPIO6 | GPIO7); rcc_periph_clock_enable(I2C_CLOCK); i2c_reset(I2C_PORT); i2c_peripheral_disable(I2C_PORT); i2c_set_standard_mode(I2C_PORT); i2c_enable_ack(I2C_PORT); i2c_set_dutycycle(I2C_PORT, I2C_CCR_DUTY_DIV2); /* default, no need to do this really */ i2c_set_clock_frequency(I2C_PORT, I2C_FREQ); /* CCR is the number of APB bus cycles in *half* an I2C bus * cycle. For Sm (100Khz) this ends up as: * freq * 1MHz / 2 * 100KHz * freq * 1000000 / 200000 * freq * 5 * * Similar trise is the number of APB bus cycles in the rise * time (plus 1). For Sm (1us) this ends up as: * freq * 1Mhz / (1/1us) + 1 * freq * 1MHz / 1MHz + 1 * freq + 1 */ /* 42MHz / (100kHz * 2) */ i2c_set_ccr(I2C_PORT, I2C_FREQ * 5); /* standard mode, freqMhz+1*/ i2c_set_trise(I2C_PORT, I2C_FREQ + 1); i2c_set_own_7bit_slave_address(I2C_PORT, OWN_ADDRESS); i2c_peripheral_enable(I2C_PORT); }
/* * IRQ handler for I2C master. Handles transmission/reception. */ void _i2c_irq_handler(i2c_dev *dev) { /* WTFs: * - Where is I2C_MSG_10BIT_ADDR handled? */ i2c_msg *msg = dev->msg; uint8 read = msg->flags & I2C_MSG_READ; uint32 sr1 = dev->regs->SR1; uint32 sr2 = dev->regs->SR2; I2C_CRUMB(IRQ_ENTRY, sr1, sr2); /* * Reset timeout counter */ dev->timestamp = systick_uptime(); /* * Add Slave support */ /* Check to see if MSL master slave bit is set */ if ((sr2 & I2C_SR2_MSL) != I2C_SR2_MSL) { /* 0 = slave mode 1 = master */ /* Check for address match */ if (sr1 & I2C_SR1_ADDR) { /* Find out which address was matched */ /* Check the general call address first */ if (sr2 & I2C_SR2_GENCALL) { dev->i2c_slave_msg->addr = 0; } /* We matched the secondary address */ else if (sr2 & I2C_SR2_DUALF) { dev->i2c_slave_msg->addr = dev->regs->OAR2 & 0xFE; } /* We matched the primary address */ else if ((sr2 & I2C_SR2_DUALF) != I2C_SR2_DUALF) { dev->i2c_slave_msg->addr = dev->regs->OAR1 & 0xFE; } /* Shouldn't get here */ else { dev->i2c_slave_msg->addr = -1; /* uh oh */ } /* if we have buffered io */ if ((dev->config_flags & I2C_SLAVE_USE_RX_BUFFER) || (dev->config_flags & I2C_SLAVE_USE_TX_BUFFER)) { /* if receiving then this would be a repeated start * *if we have some bytes already */ if ((dev->state == I2C_STATE_SL_RX) && (dev->i2c_slave_msg->xferred > 0) && (dev->config_flags & I2C_SLAVE_USE_RX_BUFFER)) { /* Call the callback with the contents of the data */ if (dev->i2c_slave_recv_callback != NULL) { (*(dev->i2c_slave_recv_callback))(dev->i2c_slave_msg); } } /* Reset the message back to defaults. * We are starting a new message */ dev->i2c_slave_msg->flags = 0; dev->i2c_slave_msg->length = 0; dev->i2c_slave_msg->xferred = 0; dev->msgs_left = 0; dev->timestamp = systick_uptime(); /* We have been addressed with SLA+R so * the master wants us to transmit */ if ((sr1 & I2C_SR1_TXE) && (dev->config_flags & I2C_SLAVE_USE_TX_BUFFER)) { /* Call the transmit callback so it can populate the msg * data with the bytes to go */ if (dev->i2c_slave_transmit_callback != NULL) { (*(dev->i2c_slave_transmit_callback))(dev->i2c_slave_msg); } } dev->state = I2C_STATE_BUSY; } sr1 = sr2 = 0; } /* EV3: Master requesting data from slave. Transmit a byte*/ if (sr1 & I2C_SR1_TXE) { if (dev->config_flags & I2C_SLAVE_USE_TX_BUFFER) { if (dev->i2c_slave_msg->xferred >= dev->i2c_slave_msg->length) { /* End of the transmit buffer? If so we NACK */ i2c_disable_ack(dev); /* We have to either issue a STOP or write something here. * STOP here seems to screw up some masters, * For now padding with 0 */ i2c_write(dev, 0); /*i2c_stop_condition(dev); // This is causing bus lockups way more than it should !? Seems some I2C master devices freak out here*/ } else { /* NACk the last byte */ if (dev->i2c_slave_msg->xferred == dev->i2c_slave_msg->length-1) { i2c_disable_ack(dev); } else { i2c_enable_ack(dev); } i2c_write(dev, dev->i2c_slave_msg->data[dev->i2c_slave_msg->xferred++]); } } else { /* Call the callback to get the data we need. * The callback is expected to write using i2c_write(...) * If the slave is going to terminate the transfer, this function should * also do a NACK on the last byte! */ if (dev->i2c_slave_transmit_callback != NULL) (*(dev->i2c_slave_transmit_callback))(dev->i2c_slave_msg); } dev->state = I2C_STATE_BUSY; sr1 = sr2 = 0; } /* EV2: Slave received data from a master. Get from DR */ if (sr1 & I2C_SR1_RXNE) { if (dev->config_flags & I2C_SLAVE_USE_RX_BUFFER) { /* Fill the buffer with the contents of the data register */ /* These is potential for buffer overflow here, so we should * really store the size of the array. This is expensive in * the ISR so left out for now. We must trust the implementor! */ dev->i2c_slave_msg->data[dev->i2c_slave_msg->xferred++] = dev->regs->DR; dev->i2c_slave_msg->length++; } else { /* Call the callback with the contents of the data */ dev->i2c_slave_msg->data[0] = dev->regs->DR; if (dev->i2c_slave_recv_callback != NULL) (*(dev->i2c_slave_recv_callback))(dev->i2c_slave_msg); } dev->state = I2C_STATE_SL_RX; sr1 = sr2 = 0; } /* EV4: Slave has detected a STOP condition on the bus */ if (sr1 & I2C_SR1_STOPF) { dev->regs->CR1 |= I2C_CR1_PE; if ((dev->config_flags & I2C_SLAVE_USE_RX_BUFFER) || (dev->config_flags & I2C_SLAVE_USE_TX_BUFFER)) { /* The callback with the data will happen on a NACK of the last data byte. * This is handled in the error IRQ (AF bit) */ /* Handle the case where the master misbehaves by sending no NACK */ if (dev->state != I2C_STATE_IDLE) { if (dev->state == I2C_STATE_SL_RX) { if (dev->i2c_slave_recv_callback != NULL) (*(dev->i2c_slave_recv_callback))(dev->i2c_slave_msg); } else { if (dev->i2c_slave_transmit_callback != NULL) (*(dev->i2c_slave_transmit_callback))(dev->i2c_slave_msg); } } } sr1 = sr2 = 0; dev->state = I2C_STATE_IDLE; } return; } /* * EV5: Start condition sent */ if (sr1 & I2C_SR1_SB) { msg->xferred = 0; i2c_enable_irq(dev, I2C_IRQ_BUFFER); /* * Master receiver */ if (read) { i2c_enable_ack(dev); } i2c_send_slave_addr(dev, msg->addr, read); sr1 = sr2 = 0; } /* * EV6: Slave address sent */ if (sr1 & I2C_SR1_ADDR) { /* * Special case event EV6_1 for master receiver. * Generate NACK and restart/stop condition after ADDR * is cleared. */ if (read) { if (msg->length == 1) { i2c_disable_ack(dev); if (dev->msgs_left > 1) { i2c_start_condition(dev); I2C_CRUMB(RX_ADDR_START, 0, 0); } else { i2c_stop_condition(dev); I2C_CRUMB(RX_ADDR_STOP, 0, 0); } } } else { /* * Master transmitter: write first byte to fill shift * register. We should get another TXE interrupt * immediately to fill DR again. */ if (msg->length != 1) { i2c_write(dev, msg->data[msg->xferred++]); } } sr1 = sr2 = 0; } /* * EV8: Master transmitter * Transmit buffer empty, but we haven't finished transmitting the last * byte written. */ if ((sr1 & I2C_SR1_TXE) && !(sr1 & I2C_SR1_BTF)) { I2C_CRUMB(TXE_ONLY, 0, 0); if (dev->msgs_left) { i2c_write(dev, msg->data[msg->xferred++]); if (msg->xferred == msg->length) { /* * End of this message. Turn off TXE/RXNE and wait for * BTF to send repeated start or stop condition. */ i2c_disable_irq(dev, I2C_IRQ_BUFFER); dev->msgs_left--; } } else { /* * This should be impossible... */ ASSERT(0); } sr1 = sr2 = 0; } /* * EV8_2: Master transmitter * Last byte sent, program repeated start/stop */ if ((sr1 & I2C_SR1_TXE) && (sr1 & I2C_SR1_BTF)) { I2C_CRUMB(TXE_BTF, 0, 0); if (dev->msgs_left) { I2C_CRUMB(TEST, 0, 0); /* * Repeated start insanity: We can't disable ITEVTEN or else SB * won't interrupt, but if we don't disable ITEVTEN, BTF will * continually interrupt us. What the f**k ST? */ i2c_start_condition(dev); while (!(dev->regs->SR1 & I2C_SR1_SB)) ; dev->msg++; } else { i2c_stop_condition(dev); /* * Turn off event interrupts to keep BTF from firing until * the end of the stop condition. Why on earth they didn't * have a start/stop condition request clear BTF is beyond * me. */ i2c_disable_irq(dev, I2C_IRQ_EVENT); I2C_CRUMB(STOP_SENT, 0, 0); dev->state = I2C_STATE_XFER_DONE; } sr1 = sr2 = 0; } /* * EV7: Master Receiver */ if (sr1 & I2C_SR1_RXNE) { I2C_CRUMB(RXNE_ONLY, 0, 0); msg->data[msg->xferred++] = dev->regs->DR; /* * EV7_1: Second to last byte in the reception? Set NACK and generate * stop/restart condition in time for the last byte. We'll get one more * RXNE interrupt before shutting things down. */ if (msg->xferred == (msg->length - 1)) { i2c_disable_ack(dev); if (dev->msgs_left > 2) { i2c_start_condition(dev); I2C_CRUMB(RXNE_START_SENT, 0, 0); } else { i2c_stop_condition(dev); I2C_CRUMB(RXNE_STOP_SENT, 0, 0); } } else if (msg->xferred == msg->length) { dev->msgs_left--; if (dev->msgs_left == 0) { /* * We're done. */ I2C_CRUMB(RXNE_DONE, 0, 0); dev->state = I2C_STATE_XFER_DONE; } else { dev->msg++; } } } }
// Doc ID 13902 Rev 11 p 712/1072 // Transfer Sequence Diagram for Master Receiver for N>2 static inline enum STMI2CSubTransactionStatus stmi2c_readmany(uint32_t i2c, struct i2c_periph *periph, struct i2c_transaction *trans) { uint16_t SR1 = I2C_SR1(i2c); // Start Condition Was Just Generated if (BIT_X_IS_SET_IN_REG( I2C_SR1_SB, SR1 ) ) { i2c_disable_interrupt(i2c, I2C_CR2_ITBUFEN); // The first data byte will be acked in read many so the slave knows it should send more i2c_nack_current(i2c); i2c_enable_ack(i2c); // Clear the SB flag i2c_send_data(i2c, trans->slave_addr | 0x01); // Document the current Status periph->status = I2CAddrRdSent; } // Address Was Sent else if (BIT_X_IS_SET_IN_REG(I2C_SR1_ADDR, SR1) ) { periph->idx_buf = 0; // Enable RXNE: receive an interrupt any time a byte is available // only enable if MORE than 3 bytes need to be read if (periph->idx_buf < (trans->len_r - 3)) { i2c_enable_interrupt(i2c, I2C_CR2_ITBUFEN); } // ACK is still on to get more DATA // Read SR2 to clear the ADDR (next byte will start arriving) uint16_t SR2 __attribute__ ((unused)) = I2C_SR2(i2c); // Document the current Status periph->status = I2CReadingByte; } // one or more bytes are available AND we were interested in Buffer interrupts else if ( (BIT_X_IS_SET_IN_REG(I2C_SR1_RxNE, SR1) ) && (BIT_X_IS_SET_IN_REG(I2C_CR2_ITBUFEN, I2C_CR2(i2c))) ) { // read byte until 3 bytes remain to be read (e.g. len_r = 6, -> idx=3 means idx 3,4,5 = 3 remain to be read if (periph->idx_buf < (trans->len_r - 3)) { trans->buf[periph->idx_buf] = I2C_DR(i2c); periph->idx_buf ++; } // from : 3bytes -> last byte: do nothing // // finally: this was the last byte else if (periph->idx_buf >= (trans->len_r - 1)) { i2c_disable_interrupt(i2c, I2C_CR2_ITBUFEN); // Last Value trans->buf[periph->idx_buf] = i2c_get_data(i2c); periph->idx_buf ++; // We got all the results trans->status = I2CTransSuccess; return STMI2C_SubTra_Ready_StopRequested; } // Check for end of transaction: start waiting for BTF instead of RXNE if (periph->idx_buf < (trans->len_r - 3)) { i2c_enable_interrupt(i2c, I2C_CR2_ITBUFEN); } else // idx >= len-3: there are 3 bytes to be read { // We want to halt I2C to have sufficient time to clear ACK, so: // Stop listening to RXNE as it will be triggered infinitely since we did not empty the buffer // on the next (second in buffer) received byte BTF will be set (buffer full and I2C halted) i2c_disable_interrupt(i2c, I2C_CR2_ITBUFEN); } } // Buffer is full while this was not a RXNE interrupt else if (BIT_X_IS_SET_IN_REG(I2C_SR1_BTF, SR1) ) { // Now the shift register and data register contain data(n-2) and data(n-1) // And I2C is halted so we have time // --- Make absolutely sure the next 2 I2C actions are performed with no delay __I2C_REG_CRITICAL_ZONE_START; // First we clear the ACK while the SCL is held low by BTF i2c_disable_ack(i2c); // Now that ACK is cleared we read one byte: instantly the last byte is being clocked in... trans->buf[periph->idx_buf] = i2c_get_data(i2c); periph->idx_buf ++; // Now the last byte is being clocked. Stop in MUST be set BEFORE the transfer of the last byte is complete PPRZ_I2C_SEND_STOP(i2c); __I2C_REG_CRITICAL_ZONE_STOP; // --- end of critical zone ----------- // Document the current Status periph->status = I2CStopRequested; // read the byte2 we had in the buffer (BTF means 2 bytes available) trans->buf[periph->idx_buf] = i2c_get_data(i2c); periph->idx_buf ++; // Ask for an interrupt to read the last byte (which is normally still busy now) // The last byte will be received with RXNE i2c_enable_interrupt(i2c, I2C_CR2_ITBUFEN); } else // Event Logic Error { return STMI2C_SubTra_Error; } return STMI2C_SubTra_Busy; }
// Doc ID 13902 Rev 11 p 713/1072 // Transfer Sequence Diagram for Master Receiver for N=2 static inline enum STMI2CSubTransactionStatus stmi2c_read2(uint32_t i2c, struct i2c_periph *periph, struct i2c_transaction *trans) { uint16_t SR1 = I2C_SR1(i2c); // Start Condition Was Just Generated if (BIT_X_IS_SET_IN_REG( I2C_SR1_SB, SR1 ) ) { // according to the datasheet: instantly shedule a NAK on the second received byte: i2c_disable_interrupt(i2c, I2C_CR2_ITBUFEN); i2c_enable_ack(i2c); i2c_nack_next(i2c); i2c_send_data(i2c, trans->slave_addr | 0x01); // Document the current Status periph->status = I2CAddrRdSent; } // Address Was Sent else if (BIT_X_IS_SET_IN_REG(I2C_SR1_ADDR, SR1) ) { // --- make absolutely sure this command is not delayed too much after the previous: // --- the NAK bits must be set before the first byte arrived: allow other interrupts here __I2C_REG_CRITICAL_ZONE_START; // if transfer of DR was finished already then we will get too many bytes // BEFORE clearing ACK, read SR2 to clear the ADDR (next byte will start arriving) // clearing ACK after the byte transfer has already started will NACK the next (2nd) uint16_t SR2 __attribute__ ((unused)) = I2C_SR2(i2c); // NOT First Clear the ACK bit but only AFTER clearing ADDR i2c_disable_ack(i2c); // Disable the RXNE and wait for BTF i2c_disable_interrupt(i2c, I2C_CR2_ITBUFEN); __I2C_REG_CRITICAL_ZONE_STOP; // --- end of critical zone ----------- // We do not set the RxE but wait for both bytes to arrive using BTF // Document the current Status periph->status = I2CReadingByte; } // Receive buffer if full, master is halted: BTF else if (BIT_X_IS_SET_IN_REG(I2C_SR1_BTF, SR1) ) { // Stop condition MUST be set BEFORE reading the DR // otherwise since there is new buffer space a new byte will be read PPRZ_I2C_SEND_STOP(i2c); // Document the current Status periph->status = I2CStopRequested; trans->buf[0] = I2C_DR(i2c); trans->buf[1] = I2C_DR(i2c); // We got all the results trans->status = I2CTransSuccess; return STMI2C_SubTra_Ready_StopRequested; } else // Event Logic Error { return STMI2C_SubTra_Error; } return STMI2C_SubTra_Busy; }
/** * @brief IRQ handler for I2C master. Handles transmission/reception. * @param dev I2C device */ static void i2c_irq_handler(i2c_dev *dev) { i2c_msg *msg = dev->msg; uint8 read = msg->flags & I2C_MSG_READ; uint32 sr1 = dev->regs->SR1; uint32 sr2 = dev->regs->SR2; I2C_CRUMB(IRQ_ENTRY, sr1, sr2); /* * Reset timeout counter */ dev->timestamp = systick_uptime(); /* * EV5: Start condition sent */ if (sr1 & I2C_SR1_SB) { msg->xferred = 0; i2c_enable_irq(dev, I2C_IRQ_BUFFER); /* * Master receiver */ if (read) { i2c_enable_ack(dev); } i2c_send_slave_addr(dev, msg->addr, read); sr1 = sr2 = 0; } /* * EV6: Slave address sent */ if (sr1 & I2C_SR1_ADDR) { /* * Special case event EV6_1 for master receiver. * Generate NACK and restart/stop condition after ADDR * is cleared. */ if (read) { if (msg->length == 1) { i2c_disable_ack(dev); if (dev->msgs_left > 1) { i2c_start_condition(dev); I2C_CRUMB(RX_ADDR_START, 0, 0); } else { i2c_stop_condition(dev); I2C_CRUMB(RX_ADDR_STOP, 0, 0); } } } else { /* * Master transmitter: write first byte to fill shift * register. We should get another TXE interrupt * immediately to fill DR again. */ if (msg->length != 1) { i2c_write(dev, msg->data[msg->xferred++]); } } sr1 = sr2 = 0; } /* * EV8: Master transmitter * Transmit buffer empty, but we haven't finished transmitting the last * byte written. */ if ((sr1 & I2C_SR1_TXE) && !(sr1 & I2C_SR1_BTF)) { I2C_CRUMB(TXE_ONLY, 0, 0); if (dev->msgs_left) { i2c_write(dev, msg->data[msg->xferred++]); if (msg->xferred == msg->length) { /* * End of this message. Turn off TXE/RXNE and wait for * BTF to send repeated start or stop condition. */ i2c_disable_irq(dev, I2C_IRQ_BUFFER); dev->msgs_left--; } } else { /* * This should be impossible... */ throb(); } sr1 = sr2 = 0; } /* * EV8_2: Master transmitter * Last byte sent, program repeated start/stop */ if ((sr1 & I2C_SR1_TXE) && (sr1 & I2C_SR1_BTF)) { I2C_CRUMB(TXE_BTF, 0, 0); if (dev->msgs_left) { I2C_CRUMB(TEST, 0, 0); /* * Repeated start insanity: We can't disable ITEVTEN or else SB * won't interrupt, but if we don't disable ITEVTEN, BTF will * continually interrupt us. What the f**k ST? */ i2c_start_condition(dev); while (!(dev->regs->SR1 & I2C_SR1_SB)) ; dev->msg++; } else { i2c_stop_condition(dev); /* * Turn off event interrupts to keep BTF from firing until * the end of the stop condition. Why on earth they didn't * have a start/stop condition request clear BTF is beyond * me. */ i2c_disable_irq(dev, I2C_IRQ_EVENT); I2C_CRUMB(STOP_SENT, 0, 0); dev->state = I2C_STATE_XFER_DONE; } sr1 = sr2 = 0; } /* * EV7: Master Receiver */ if (sr1 & I2C_SR1_RXNE) { I2C_CRUMB(RXNE_ONLY, 0, 0); msg->data[msg->xferred++] = dev->regs->DR; /* * EV7_1: Second to last byte in the reception? Set NACK and generate * stop/restart condition in time for the last byte. We'll get one more * RXNE interrupt before shutting things down. */ if (msg->xferred == (msg->length - 1)) { i2c_disable_ack(dev); if (dev->msgs_left > 2) { i2c_start_condition(dev); I2C_CRUMB(RXNE_START_SENT, 0, 0); } else { i2c_stop_condition(dev); I2C_CRUMB(RXNE_STOP_SENT, 0, 0); } } else if (msg->xferred == msg->length) { dev->msgs_left--; if (dev->msgs_left == 0) { /* * We're done. */ I2C_CRUMB(RXNE_DONE, 0, 0); dev->state = I2C_STATE_XFER_DONE; } else { dev->msg++; } } } }
/* * IRQ handler for I2C master. Handles transmission/reception. */ void _i2c_irq_handler(i2c_dev *dev) { static uint8_t received_bytes; i2c_msg *msg = dev->msg; fooprint("inside interrupt"); // true if this is a receive intruction uint8 read = msg->flags & I2C_MSG_READ; uint32_t controlReg = dev ->regs->CONTROL; fooprint_int(controlReg); /* * Reset timeout counter */ dev->timestamp = systick_uptime(); /* * Master needs to acknowledge after recieving every byte and clear the acknowledge interrupt bit */ if (controlReg & I2C_CR_ACKI_MASK){ uint8_t bp,bc; fooprint("ack condition"); received_bytes++; // there's a bug here if we have multiple msgs fooprint("xferred"); fooprint_int(dev->msg->xferred); fooprint(""); fooprint("received_bytes"); fooprint_int(received_bytes); fooprint(""); fooprint("msg_length"); fooprint_int(dev->msg->length); fooprint(""); fooprint("msgs_left"); fooprint_int(dev->msgs_left); fooprint(""); if ((dev->msg->xferred + received_bytes == dev->msg->length) && (dev->msgs_left==1)) { dev->regs->CONTROL &=~I2C_CR_ACK_MASK; fooprint("last byte, sending NACK"); } else { fooprint("more bytes expected, sending ACK"); dev->regs->CONTROL |=I2C_CR_ACK_MASK; } dev->regs->CONTROL &= ~I2C_CR_ACKI_MASK; return; } /* * Stop Condition Sent */ if (controlReg & I2C_CR_STOI_MASK){ fooprint("stop condition"); dev->state = I2C_STATE_XFER_DONE; dev->regs->CONTROL &= ~I2C_CR_STO_MASK; dev->regs->CONTROL &= ~I2C_CR_STOI_MASK; return; } /* * EV5: Start condition sent */ if (controlReg & I2C_CR_STAI_MASK) { fooprint("start condition"); msg->xferred = 0; //i2c_enable_irq(dev, I2C_IRQ_BUFFER); // clear Start bit (sta) and dev->regs->CONTROL &= (~I2C_CR_STA_MASK); /* * Master receiver */ //??????????????????????????????????????????????????????????????? // enable an acknowledge interrupt if (read) { i2c_enable_ack(dev); } dev->regs->CONFIG &= ~I2C_CFGR_BC_MASK; dev->regs->CONFIG |= 1 << I2C_CFGR_BC_BIT; // sets the slave address and read/write direction i2c_send_slave_addr(dev, msg->addr, read); controlReg = 0; // set the arm transmit bit to enable transmission of message dev->regs->CONTROL |= I2C_CR_TXARM_MASK; // clear start interrupt flag(STAI) bit dev->regs->CONTROL &= (~I2C_CR_STAI_MASK); } /* * EV6: Slave address sent */ if (controlReg & I2C_CR_TXI_MASK) { fooprint("transfer"); //if slave doesn't acknowledge generate a stop if (!(controlReg & I2C_CR_ACK_MASK)){ fooprint("nack"); i2c_stop_condition(dev); return; } fooprint(" no nack"); if (read) { received_bytes=0; fooprint("transfer reading"); int32_t bytesLeft = msg->length - msg->xferred; if (bytesLeft >= 4){ bytesLeft = 4; } dev->regs->CONFIG &= ~I2C_CFGR_BC_MASK; if (bytesLeft < 4) { dev->regs->CONFIG |= bytesLeft << I2C_CFGR_BC_BIT; } // set the receive arm interrupt bit dev->regs->CONTROL |= I2C_CR_RXARM_MASK; // clear the transmit interrupt flag dev->regs->CONTROL &= (~I2C_CR_TXI_MASK); } else { fooprint("transfer writing"); int32_t bytesLeft = msg->length - msg->xferred; // if the last byte is transferred and there are no more messages generate a stop condition if (!bytesLeft) { if (--dev->msgs_left) dev->msg++; } if (bytesLeft == 0 && dev->msgs_left == 0){ fooprint("tx done, generating stop"); i2c_stop_condition(dev); // clear the transmit interrupt flag dev->regs->CONTROL &= (~I2C_CR_TXI_MASK); return; } // are no more bytes to transfer and there are messages do a repeated start else if(bytesLeft == 0){ fooprint("transfer repeated start"); i2c_start_condition(dev); // clear the transmit interrupt flag dev->regs->CONTROL &= (~I2C_CR_TXI_MASK); // clear the transmit interrupt flag dev->regs->CONTROL &= (~I2C_CR_TXI_MASK); return; } if (bytesLeft >= 4){ bytesLeft = 4; } fooprint("bytes left:"); fooprint_int(bytesLeft); fooprint(""); //clear BC bits dev->regs->CONFIG &= ~I2C_CFGR_BC_MASK; if (bytesLeft < 4) { dev->regs->CONFIG |= bytesLeft << I2C_CFGR_BC_BIT; } fooprint("CONFIG"); fooprint_int(dev->regs->CONFIG); fooprint(""); // load the data Buffer i2c_write(dev, bytesLeft); fooprint("DATA"); fooprint_int(dev->regs->DATA); fooprint(""); // set the arm transmit bit to enable transmission of message dev->regs->CONTROL |= I2C_CR_TXARM_MASK; // clear the transmit interrupt flag dev->regs->CONTROL &= (~I2C_CR_TXI_MASK); } fooprint("transfer done"); } /* * EV7: Master Receiver */ if (controlReg & I2C_CR_RXI_MASK) { fooprint("receive"); uint32_t start = dev->msg->xferred; uint8_t bytes = (dev->regs->CONFIG & I2C_CFGR_BC_MASK) >> I2C_CFGR_BC_BIT; if (!bytes) bytes = 4; fooprint("bytes"); fooprint_int(bytes); fooprint(""); memcpy(&dev->msg->data[start], &dev->regs->DATA, bytes); dev->msg->xferred += bytes; start = dev->msg->xferred; received_bytes=0; fooprint("xferred"); fooprint_int(dev->msg->xferred); fooprint(""); int32_t bytesLeft = msg->length - msg->xferred; if (!bytesLeft) { fooprint("rx: no bytes left"); dev->msgs_left--; } if (bytesLeft == 0 && dev->msgs_left == 0){ fooprint("rx: no msgs left, generating stop"); i2c_stop_condition(dev); fooprint("rx: clearing rxi"); // clear the receive interrupt flag dev->regs->CONTROL &= (~I2C_CR_RXI_MASK); return; } // are no more bytes to transfer and there are messages do a repeated start else if(bytesLeft == 0){ fooprint("rx: msgs left, repeated start"); // clear the receive interrupt flag i2c_start_condition(dev); dev->regs->CONTROL &= (~I2C_CR_RXI_MASK); return; } if (bytesLeft >= 4){ //clear BC bits bytesLeft = 4; } dev->regs->CONFIG &= ~I2C_CFGR_BC_MASK; if (bytesLeft < 4) { dev->regs->CONFIG |= bytesLeft << I2C_CFGR_BC_BIT; } // set the receive arm interrupt bit dev->regs->CONTROL |= I2C_CR_RXARM_MASK; dev->regs->CONTROL &= (~I2C_CR_RXI_MASK); fooprint("rx: exit"); }