static void __init save_end_v1(u32 *ptr)
{
/* write end of restore buffer */
ptr[0] = nvhost_opcode_setclass(NV_GRAPHICS_3D_CLASS_ID,
AR3D_DW_MEMORY_OUTPUT_DATA, 1);
nvhost_3dctx_restore_end(ptr + 1);
ptr += RESTORE_END_SIZE;
/* reset to dual reg if necessary */
ptr[1] = nvhost_opcode_imm(AR3D_GSHIM_WRITE_MASK,
(1 << register_sets) - 1);
/* op_done syncpt incr to flush FDC */
ptr[2] = nvhost_opcode_imm_incr_syncpt(NV_SYNCPT_OP_DONE, NVSYNCPT_3D);
/* host wait for that syncpt incr, and advance the wait base */
ptr[3] = nvhost_opcode_setclass(NV_HOST1X_CLASS_ID,
NV_CLASS_HOST_WAIT_SYNCPT_BASE,
nvhost_mask2(
NV_CLASS_HOST_WAIT_SYNCPT_BASE,
NV_CLASS_HOST_INCR_SYNCPT_BASE));
ptr[4] = nvhost_class_host_wait_syncpt_base(NVSYNCPT_3D,
NVWAITBASE_3D, nvhost_3dctx_save_incrs - 1);
ptr[5] = nvhost_class_host_incr_syncpt_base(NVWAITBASE_3D,
nvhost_3dctx_save_incrs);
/* set class back to 3d */
ptr[6] = nvhost_opcode_setclass(NV_GRAPHICS_3D_CLASS_ID, 0, 0);
/* send reg reads back to host */
ptr[7] = nvhost_opcode_imm(AR3D_GLOBAL_MEMORY_OUTPUT_READS, 0);
/* final syncpt increment to release waiters */
ptr[8] = nvhost_opcode_imm(0, NVSYNCPT_3D);
}
static void save_end_v1(struct host1x_hwctx_handler *p, u32 *ptr)
{
/* write end of restore buffer */
ptr[0] = nvhost_opcode_setclass(NV_GRAPHICS_3D_CLASS_ID,
AR3D_PIPEALIAS_DW_MEMORY_OUTPUT_DATA, 1);
nvhost_3dctx_restore_end(p, ptr + 1);
ptr += RESTORE_END_SIZE;
/* op_done syncpt incr to flush FDC */
ptr[1] = nvhost_opcode_imm_incr_syncpt(
host1x_uclass_incr_syncpt_cond_op_done_v(), p->h.syncpt);
/* host wait for that syncpt incr, and advance the wait base */
ptr[2] = nvhost_opcode_setclass(NV_HOST1X_CLASS_ID,
host1x_uclass_wait_syncpt_base_r(),
nvhost_mask2(
host1x_uclass_wait_syncpt_base_r(),
host1x_uclass_incr_syncpt_base_r()));
ptr[3] = nvhost_class_host_wait_syncpt_base(p->h.syncpt,
p->h.waitbase, p->save_incrs - 1);
ptr[4] = nvhost_class_host_incr_syncpt_base(p->h.waitbase,
p->save_incrs);
/* set class back to 3d */
ptr[5] = nvhost_opcode_setclass(NV_GRAPHICS_3D_CLASS_ID, 0, 0);
/* send reg reads back to host */
ptr[6] = nvhost_opcode_imm(AR3D_GLOBAL_MEMORY_OUTPUT_READS, 0);
/* final syncpt increment to release waiters */
ptr[7] = nvhost_opcode_imm(0, p->h.syncpt);
}
