Exemple #1
0
static void __devinit palm_bk3710_chipinit(void __iomem *base)
{
	/*
	 * REVISIT:  the ATA reset signal needs to be managed through a
	 * GPIO, which means it should come from platform_data.  Until
	 * we get and use such information, we have to trust that things
	 * have been reset before we get here.
	 */

	/*
	 * Program the IDETIMP Register Value based on the following assumptions
	 *
	 * (ATA_IDETIMP_IDEEN		, ENABLE ) |
	 * (ATA_IDETIMP_PREPOST1	, DISABLE) |
	 * (ATA_IDETIMP_PREPOST0	, DISABLE) |
	 *
	 * DM6446 silicon rev 2.1 and earlier have no observed net benefit
	 * from enabling prefetch/postwrite.
	 */
	writew(BIT(15), base + BK3710_IDETIMP);

	/*
	 * UDMACTL Ultra-ATA DMA Control
	 * (ATA_UDMACTL_UDMAP1	, 0 ) |
	 * (ATA_UDMACTL_UDMAP0	, 0 )
	 *
	 */
	writew(0, base + BK3710_UDMACTL);

	/*
	 * MISCCTL Miscellaneous Conrol Register
	 * (ATA_MISCCTL_HWNHLD1P	, 1 cycle)
	 * (ATA_MISCCTL_HWNHLD0P	, 1 cycle)
	 * (ATA_MISCCTL_TIMORIDE	, 1)
	 */
	writel(0x001, base + BK3710_MISCCTL);

	/*
	 * IORDYTMP IORDY Timer for Primary Register
	 * (ATA_IORDYTMP_IORDYTMP     , 0xffff  )
	 */
	writel(0xFFFF, base + BK3710_IORDYTMP);

	/*
	 * Configure BMISP Register
	 * (ATA_BMISP_DMAEN1	, DISABLE )	|
	 * (ATA_BMISP_DMAEN0	, DISABLE )	|
	 * (ATA_BMISP_IORDYINT	, CLEAR)	|
	 * (ATA_BMISP_INTRSTAT	, CLEAR)	|
	 * (ATA_BMISP_DMAERROR	, CLEAR)
	 */
	writew(0, base + BK3710_BMISP);

	palm_bk3710_setpiomode(base, NULL, 0, 600, 0);
	palm_bk3710_setpiomode(base, NULL, 1, 600, 0);
}
Exemple #2
0
static void palm_bk3710_set_pio_mode(ide_drive_t *drive, u8 pio)
{
	unsigned int cycle_time;
	int is_slave = drive->dn & 1;
	ide_drive_t *mate;
	void __iomem *base = (void *)drive->hwif->dma_base;

	/*
	 * Obtain the drive PIO data for tuning the Palm Chip registers
	 */
	cycle_time = ide_pio_cycle_time(drive, pio);
	mate = ide_get_pair_dev(drive);
	palm_bk3710_setpiomode(base, mate, is_slave, cycle_time, pio);
}
Exemple #3
0
static void palm_bk3710_tune_drive(ide_drive_t *drive, u8 pio)
{
	ide_pio_data_t piodata;
	int is_slave = drive->dn & 1;
	ide_drive_t *mate;
	void __iomem *base = (void *)drive->hwif->dma_base;

	/*
	 * Obtain the drive PIO data for tuning the Palm Chip registers
	 */
	pio  = ide_get_best_pio_mode(drive, pio, 4, &piodata);

	mate = ide_get_paired_drive(drive);
	palm_bk3710_setpiomode(base, mate, is_slave, piodata.cycle_time, pio);
	(void)ide_config_drive_speed(drive, XFER_PIO_0 + pio);
}
Exemple #4
0
static void __devinit palm_bk3710_chipinit(void __iomem *base)
{
	/*
	 * enable the reset_en of ATA controller so that when ata signals
	 * are brought out, by writing into device config. at that
	 * time por_n signal should not be 'Z' and have a stable value.
	 */
	writel(0x0300, base + BK3710_MISCCTL);

	/* wait for some time and deassert the reset of ATA Device. */
	mdelay(100);

	/* Deassert the Reset */
	writel(0x0200, base + BK3710_MISCCTL);

	/*
	 * Program the IDETIMP Register Value based on the following assumptions
	 *
	 * (ATA_IDETIMP_IDEEN		, ENABLE ) |
	 * (ATA_IDETIMP_SLVTIMEN	, DISABLE) |
	 * (ATA_IDETIMP_RDYSMPL		, 70NS)    |
	 * (ATA_IDETIMP_RDYRCVRY	, 50NS)    |
	 * (ATA_IDETIMP_DMAFTIM1	, PIOCOMP) |
	 * (ATA_IDETIMP_PREPOST1	, DISABLE) |
	 * (ATA_IDETIMP_RDYSEN1		, DISABLE) |
	 * (ATA_IDETIMP_PIOFTIM1	, DISABLE) |
	 * (ATA_IDETIMP_DMAFTIM0	, PIOCOMP) |
	 * (ATA_IDETIMP_PREPOST0	, DISABLE) |
	 * (ATA_IDETIMP_RDYSEN0		, DISABLE) |
	 * (ATA_IDETIMP_PIOFTIM0	, DISABLE)
	 */
	writew(0xB388, base + BK3710_IDETIMP);

	/*
	 * Configure  SIDETIM  Register
	 * (ATA_SIDETIM_RDYSMPS1	,120NS ) |
	 * (ATA_SIDETIM_RDYRCYS1	,120NS )
	 */
	writeb(0, base + BK3710_SIDETIM);

	/*
	 * UDMACTL Ultra-ATA DMA Control
	 * (ATA_UDMACTL_UDMAP1	, 0 ) |
	 * (ATA_UDMACTL_UDMAP0	, 0 )
	 *
	 */
	writew(0, base + BK3710_UDMACTL);

	/*
	 * MISCCTL Miscellaneous Conrol Register
	 * (ATA_MISCCTL_RSTMODEP	, 1) |
	 * (ATA_MISCCTL_RESETP		, 0) |
	 * (ATA_MISCCTL_TIMORIDE	, 1)
	 */
	writel(0x201, base + BK3710_MISCCTL);

	/*
	 * IORDYTMP IORDY Timer for Primary Register
	 * (ATA_IORDYTMP_IORDYTMP     , 0xffff  )
	 */
	writel(0xFFFF, base + BK3710_IORDYTMP);

	/*
	 * Configure BMISP Register
	 * (ATA_BMISP_DMAEN1	, DISABLE )	|
	 * (ATA_BMISP_DMAEN0	, DISABLE )	|
	 * (ATA_BMISP_IORDYINT	, CLEAR)	|
	 * (ATA_BMISP_INTRSTAT	, CLEAR)	|
	 * (ATA_BMISP_DMAERROR	, CLEAR)
	 */
	writew(0, base + BK3710_BMISP);

	palm_bk3710_setpiomode(base, NULL, 0, 600, 0);
	palm_bk3710_setpiomode(base, NULL, 1, 600, 0);
}