void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; #if CONFIG_HAVE_ACPI_RESUME void *resume_backup_memory; #endif amd_initmmio(); hudson_lpc_port80(); if (!cpu_init_detectedx && boot_cpu()) { post_code(0x30); post_code(0x31); console_init(); } /* Halt if there was a built in self test failure */ post_code(0x34); report_bist_failure(bist); /* Load MPB */ val = cpuid_eax(1); printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx); post_code(0x37); AGESAWRAPPER(amdinitreset); post_code(0x38); printk(BIOS_DEBUG, "Got past agesawrapper_amdinitreset\n"); post_code(0x39); AGESAWRAPPER(amdinitearly); int s3resume = acpi_is_wakeup_s3(); if (!s3resume) { post_code(0x40); AGESAWRAPPER(amdinitpost); post_code(0x41); AGESAWRAPPER(amdinitenv); /* TODO: Disable cache is not ok. */ disable_cache_as_ram(); } else { /* S3 detect */ printk(BIOS_INFO, "S3 detected\n"); post_code(0x60); AGESAWRAPPER(amdinitresume); AGESAWRAPPER(amds3laterestore); post_code(0x61); prepare_for_resume(); } post_code(0x50); copy_and_run(); post_code(0x54); /* Should never see this post code. */ }
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; /* Must come first to enable PCI MMCONF. */ amd_initmmio(); if (!cpu_init_detectedx && boot_cpu()) { post_code(0x30); sb_Poweron_Init(); post_code(0x31); nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); } /* Halt if there was a built in self test failure */ post_code(0x34); report_bist_failure(bist); /* Load MPB */ val = cpuid_eax(1); printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); post_code(0x37); agesawrapper_amdinitreset(); post_code(0x39); agesawrapper_amdinitearly(); int s3resume = acpi_is_wakeup_s3(); if (!s3resume) { post_code(0x40); agesawrapper_amdinitpost(); post_code(0x42); agesawrapper_amdinitenv(); amd_initenv(); } else { /* S3 detect */ printk(BIOS_INFO, "S3 detected\n"); post_code(0x60); agesawrapper_amdinitresume(); agesawrapper_amds3laterestore(); post_code(0x61); prepare_for_resume(); } post_code(0x50); copy_and_run(); printk(BIOS_ERR, "Error: copy_and_run() returned!\n"); post_code(0x54); /* Should never see this post code. */ }
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; amd_initmmio(); hudson_lpc_port80(); if (!cpu_init_detectedx && boot_cpu()) { post_code(0x30); post_code(0x31); console_init(); } /* Halt if there was a built in self test failure */ post_code(0x34); report_bist_failure(bist); /* Load MPB */ val = cpuid_eax(1); printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); post_code(0x37); agesawrapper_amdinitreset(); post_code(0x39); agesawrapper_amdinitearly(); int s3resume = acpi_is_wakeup_s3(); if (!s3resume) { post_code(0x40); agesawrapper_amdinitpost(); post_code(0x41); agesawrapper_amdinitenv(); disable_cache_as_ram(); } else { /* S3 detect */ printk(BIOS_INFO, "S3 detected\n"); post_code(0x60); agesawrapper_amdinitresume(); amd_initcpuio(); agesawrapper_amds3laterestore(); post_code(0x61); prepare_for_resume(); } post_code(0x50); copy_and_run(); post_code(0x54); /* Should never see this post code. */ }
void romstage_after_car(void) { struct romstage_handoff *handoff; handoff = romstage_handoff_find_or_add(); prepare_for_resume(handoff); #if CONFIG_VBOOT_VERIFY_FIRMWARE vboot_verify_firmware(handoff); #endif /* Load the ramstage. */ copy_and_run(); }
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; /* * All cores: allow caching of flash chip code and data * (there are no cache-as-ram reliability concerns with family 14h) */ __writemsr (0x20c, (0x0100000000ull - CACHE_ROM_SIZE) | 5); __writemsr (0x20d, (0x1000000000ull - CACHE_ROM_SIZE) | 0x800); /* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */ __writemsr (0xc0010062, 0); amd_initmmio(); if (!cpu_init_detectedx && boot_cpu()) { post_code(0x30); sb_Poweron_Init(); post_code(0x31); fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); } /* Halt if there was a built in self test failure */ post_code(0x34); report_bist_failure(bist); /* Load MPB */ val = cpuid_eax(1); printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); post_code(0x37); agesawrapper_amdinitreset(); post_code(0x39); agesawrapper_amdinitearly(); int s3resume = acpi_is_wakeup_s3(); if (!s3resume) { post_code(0x40); agesawrapper_amdinitpost(); post_code(0x42); agesawrapper_amdinitenv(); amd_initenv(); } else { /* S3 detect */ printk(BIOS_INFO, "S3 detected\n"); post_code(0x60); agesawrapper_amdinitresume(); agesawrapper_amds3laterestore(); post_code(0x61); prepare_for_resume(); } post_code(0x50); copy_and_run(); printk(BIOS_ERR, "Error: copy_and_run() returned!\n"); post_code(0x54); /* Should never see this post code. */ }
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; u8 byte; pci_devfn_t dev; amd_initmmio(); /* Set LPC decode enables. */ dev = PCI_DEV(0, 0x14, 3); pci_write_config32(dev, 0x44, 0xff03ffd5); hudson_lpc_port80(); byte = pci_read_config8(dev, 0x48); byte |= 3; /* 2e, 2f */ pci_write_config8(dev, 0x48, byte); if (!cpu_init_detectedx && boot_cpu()) { post_code(0x30); post_code(0x31); lpc47n217_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); outb(0x24, 0xcd6); outb(0x1, 0xcd7); outb(0xea, 0xcd6); outb(0x1, 0xcd7); *(u8 *)0xfed80101 = 0x98; console_init(); } /* Halt if there was a built in self test failure */ post_code(0x34); report_bist_failure(bist); /* Load MPB */ val = cpuid_eax(1); printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); post_code(0x37); agesawrapper_amdinitreset(); post_code(0x39); agesawrapper_amdinitearly(); int s3resume = acpi_is_wakeup_s3(); if (!s3resume) { post_code(0x40); agesawrapper_amdinitpost(); post_code(0x41); agesawrapper_amdinitenv(); disable_cache_as_ram(); } else { /* S3 detect */ printk(BIOS_INFO, "S3 detected\n"); post_code(0x60); agesawrapper_amdinitresume(); amd_initcpuio(); agesawrapper_amds3laterestore(); post_code(0x61); prepare_for_resume(); } post_code(0x50); copy_and_run(); post_code(0x54); /* Should never see this post code. */ }
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; u8 byte; device_t dev; AGESAWRAPPER(amdinitmmio); hudson_lpc_port80(); //__asm__ volatile ("1: jmp 1b"); /* TODO: */ dev = PCI_DEV(0, 0x14, 3);//pci_locate_device(PCI_ID(0x1002, 0x439D), 0); byte = pci_read_config8(dev, 0x48); byte |= 3; /* 2e, 2f */ pci_write_config8(dev, 0x48, byte); if (!cpu_init_detectedx && boot_cpu()) { post_code(0x30); post_code(0x31); lpc47n217_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); outb(0x24, 0xcd6); outb(0x1, 0xcd7); outb(0xea, 0xcd6); outb(0x1, 0xcd7); *(u8 *)0xfed80101 = 0x98; console_init(); } /* Halt if there was a built in self test failure */ post_code(0x34); report_bist_failure(bist); /* Load MPB */ val = cpuid_eax(1); printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx); post_code(0x37); AGESAWRAPPER(amdinitreset); post_code(0x39); AGESAWRAPPER(amdinitearly); int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed(); if (!s3resume) { post_code(0x40); AGESAWRAPPER(amdinitpost); post_code(0x41); AGESAWRAPPER(amdinitenv); disable_cache_as_ram(); } else { /* S3 detect */ printk(BIOS_INFO, "S3 detected\n"); post_code(0x60); AGESAWRAPPER(amdinitresume); AGESAWRAPPER(amds3laterestore); post_code(0x61); prepare_for_resume(); } post_code(0x50); copy_and_run(); post_code(0x54); /* Should never see this post code. */ }
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; /* * In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for * LpcClk[1:0]". This following register setting has been * replicated in every reference design since Parmer, so it is * believed to be required even though it is not documented in * the SoC BKDGs. Without this setting, there is no serial * output. */ outb(0xD2, 0xcd6); outb(0x00, 0xcd7); amd_initmmio(); hudson_lpc_port80(); if (!cpu_init_detectedx && boot_cpu()) { post_code(0x30); post_code(0x31); console_init(); } /* Halt if there was a built in self test failure */ post_code(0x34); report_bist_failure(bist); /* Load MPB */ val = cpuid_eax(1); printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx); post_code(0x37); AGESAWRAPPER(amdinitreset); post_code(0x38); printk(BIOS_DEBUG, "Got past avalon_early_setup\n"); post_code(0x39); AGESAWRAPPER(amdinitearly); int s3resume = acpi_is_wakeup_s3(); if (!s3resume) { post_code(0x40); AGESAWRAPPER(amdinitpost); //PspMboxBiosCmdDramInfo(); post_code(0x41); AGESAWRAPPER(amdinitenv); /* If code hangs here, please check cahaltasm.S */ disable_cache_as_ram(); } else { /* S3 detect */ printk(BIOS_INFO, "S3 detected\n"); post_code(0x60); AGESAWRAPPER(amdinitresume); AGESAWRAPPER(amds3laterestore); post_code(0x61); prepare_for_resume(); } outb(0xEA, 0xCD6); outb(0x1, 0xcd7); post_code(0x50); copy_and_run(); post_code(0x54); /* Should never see this post code. */ }
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; amd_initmmio(); /* Set LPC decode enables. */ pci_devfn_t dev = PCI_DEV(0, 0x14, 3); pci_write_config32(dev, 0x44, 0xff03ffd5); hudson_lpc_port80(); if (!cpu_init_detectedx && boot_cpu()) { post_code(0x30); post_code(0x31); fintek_enable_serial(SERIAL_DEV1, CONFIG_TTYS0_BASE); console_init(); } /* Halt if there was a built in self test failure */ post_code(0x34); report_bist_failure(bist); /* Load MPB */ val = cpuid_eax(1); printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); /* On Larne, after LpcClkDrvSth is set, it needs some time to be stable, because of the buffer ICS551M */ int i; for(i = 0; i < 200000; i++) val = inb(0xcd6); post_code(0x37); agesawrapper_amdinitreset(); post_code(0x38); printk(BIOS_DEBUG, "Got past yangtze_early_setup\n"); post_code(0x39); agesawrapper_amdinitearly(); int s3resume = acpi_is_wakeup_s3(); if (!s3resume) { post_code(0x40); agesawrapper_amdinitpost(); post_code(0x41); agesawrapper_amdinitenv(); /* TODO: Disable cache is not ok. */ disable_cache_as_ram(); } else { /* S3 detect */ printk(BIOS_INFO, "S3 detected\n"); post_code(0x60); agesawrapper_amdinitresume(); amd_initcpuio(); agesawrapper_amds3laterestore(); post_code(0x61); prepare_for_resume(); } outb(0xEA, 0xCD6); outb(0x1, 0xcd7); post_code(0x50); copy_and_run(); post_code(0x54); /* Should never see this post code. */ }
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; /* Must come first to enable PCI MMCONF. */ amd_initmmio(); if (!cpu_init_detectedx && boot_cpu()) { post_code(0x30); sb_Poweron_Init(); post_code(0x31); winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); } /* Halt if there was a built in self test failure */ post_code(0x34); report_bist_failure(bist); /* Load MPB */ val = cpuid_eax(1); printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); post_code(0x37); agesawrapper_amdinitreset(); post_code(0x39); agesawrapper_amdinitearly(); int s3resume = acpi_is_wakeup_s3(); if (!s3resume) { post_code(0x40); /* Reboots with outb(3,0x92), outb(4,0xcf9) or triple-fault all * hang, looks like DRAM re-init goes wrong, don't know why. */ val = agesawrapper_amdinitpost(); if (val == 7) /* fatal, amdinitenv below is going to hang */ outb(0x06, 0x0cf9); /* reset system harder instead */ post_code(0x42); agesawrapper_amdinitenv(); amd_initenv(); } else { /* S3 detect */ printk(BIOS_INFO, "S3 detected\n"); post_code(0x60); agesawrapper_amdinitresume(); agesawrapper_amds3laterestore(); post_code(0x61); prepare_for_resume(); } post_code(0x50); copy_and_run(); printk(BIOS_ERR, "Error: copy_and_run() returned!\n"); post_code(0x54); /* Should never see this post code. */ }
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; /* * In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for * LpcClk[1:0]". This following register setting has been * replicated in every reference design since Parmer, so it is * believed to be required even though it is not documented in * the SoC BKDGs. Without this setting, there is no serial * output. */ outb(0xD2, 0xcd6); outb(0x00, 0xcd7); amd_initmmio(); hudson_lpc_decode(); outb(0x24, 0xCD6); outb(0x01, 0xCD7); *(volatile u32 *) (0xFED80000 + 0xE00 + 0x28) |= 1 << 18; /* 24Mhz */ *(volatile u32 *) (0xFED80000 + 0xE00 + 0x40) &= ~(1 << 2); /* 24Mhz */ hudson_lpc_port80(); if (!cpu_init_detectedx) { post_code(0x30); f81216h_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE, MODE_7777); post_code(0x31); console_init(); } /* Halt if there was a built in self test failure */ post_code(0x34); report_bist_failure(bist); /* Load MPB */ val = cpuid_eax(1); printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); post_code(0x37); AGESAWRAPPER(amdinitreset); post_code(0x38); printk(BIOS_DEBUG, "Got past hudson_early_setup\n"); post_code(0x39); AGESAWRAPPER(amdinitearly); int s3resume = acpi_is_wakeup_s3(); if (!s3resume) { post_code(0x40); AGESAWRAPPER(amdinitpost); post_code(0x41); AGESAWRAPPER(amdinitenv); /* If code hangs here, please check cahaltasm.S */ disable_cache_as_ram(); } else if (IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)) { /* S3 detect */ printk(BIOS_INFO, "S3 detected\n"); post_code(0x60); AGESAWRAPPER(amdinitresume); AGESAWRAPPER(amds3laterestore); post_code(0x61); prepare_for_resume(); } post_code(0x50); copy_and_run(); post_code(0x54); /* Should never see this post code. */ }
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; u8 byte; device_t dev; #if IS_ENABLED(CONFIG_POST_DEVICE_PCI_PCIE) hudson_pci_port80(); #endif #if IS_ENABLED(CONFIG_POST_DEVICE_LPC) hudson_lpc_port80(); #endif val = agesawrapper_amdinitmmio(); if (!cpu_init_detectedx && boot_cpu()) { /* enable SIO LPC decode */ dev = PCI_DEV(0, 0x14, 3); byte = pci_read_config8(dev, 0x48); byte |= 3; /* 2e, 2f */ pci_write_config8(dev, 0x48, byte); /* enable serial decode */ byte = pci_read_config8(dev, 0x44); byte |= (1 << 6); /* 0x3f8 */ pci_write_config8(dev, 0x44, byte); post_code(0x30); /* enable SB MMIO space */ outb(0x24, 0xcd6); outb(0x1, 0xcd7); /* enable SIO clock */ sbxxx_enable_48mhzout(); ite_kill_watchdog(GPIO_DEV); ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); ite_enable_3vsbsw(GPIO_DEV); console_init(); /* turn on secondary smbus at b20 */ outb(0x28, 0xcd6); byte = inb(0xcd7); byte |= 1; outb(byte, 0xcd7); /* set DDR3 voltage */ byte = CONFIG_BOARD_ASUS_F2A85_M_DDR3_VOLT_VAL; /* default is byte = 0x0, so no need to set it in this case */ if (byte) do_smbus_write_byte(0xb20, 0x15, 0x3, byte); } /* Halt if there was a built in self test failure */ post_code(0x34); report_bist_failure(bist); /* Load MPB */ val = cpuid_eax(1); printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx); post_code(0x37); printk(BIOS_DEBUG, "agesawrapper_amdinitreset "); val = agesawrapper_amdinitreset(); if(val) { printk(BIOS_DEBUG, "agesawrapper_amdinitreset failed: %x \n", val); } post_code(0x39); val = agesawrapper_amdinitearly (); if(val) { printk(BIOS_DEBUG, "agesawrapper_amdinitearly failed: %x \n", val); } printk(BIOS_DEBUG, "Got past agesawrapper_amdinitearly\n"); int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed(); if (!s3resume) { post_code(0x40); val = agesawrapper_amdinitpost (); if(val) { printk(BIOS_DEBUG, "agesawrapper_amdinitpost failed: %x \n", val); } printk(BIOS_DEBUG, "Got past agesawrapper_amdinitpost\n"); post_code(0x41); val = agesawrapper_amdinitenv (); if(val) { printk(BIOS_DEBUG, "agesawrapper_amdinitenv failed: %x \n", val); } printk(BIOS_DEBUG, "Got past agesawrapper_amdinitenv\n"); disable_cache_as_ram(); } else { /* S3 detect */ printk(BIOS_INFO, "S3 detected\n"); post_code(0x60); printk(BIOS_DEBUG, "agesawrapper_amdinitresume "); val = agesawrapper_amdinitresume(); if (val) printk(BIOS_DEBUG, "error level: %x \n", val); else printk(BIOS_DEBUG, "passed.\n"); printk(BIOS_DEBUG, "agesawrapper_amds3laterestore "); val = agesawrapper_amds3laterestore (); if (val) printk(BIOS_DEBUG, "error level: %x \n", val); else printk(BIOS_DEBUG, "passed.\n"); post_code(0x61); prepare_for_resume(); } post_code(0x50); copy_and_run(); post_code(0x54); /* Should never see this post code. */ }
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; msr_t msr; /* * All cores: allow caching of flash chip code and data * (there are no cache-as-ram reliability concerns with family 14h) */ msr.lo = ((0x0100000000ull - CACHE_ROM_SIZE) | 5) & 0xFFFFFFFF; msr.hi = ((0x0100000000ull - CACHE_ROM_SIZE) | 5) >> 32; wrmsr (MSR_MTRR_VARIABLE_BASE6, msr); msr.lo = ((0x1000000000ull - CACHE_ROM_SIZE) | 0x800) & 0xFFFFFFFF; msr.hi = ((0x1000000000ull - CACHE_ROM_SIZE) | 0x800) >> 32; wrmsr (MSR_MTRR_VARIABLE_MASK6, msr); /* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */ msr.lo = 0; msr.hi = 0; wrmsr (MSR_PSTATE_CONTROL, msr); amd_initmmio(); if (!cpu_init_detectedx && boot_cpu()) { post_code(0x30); sb_Poweron_Init(); post_code(0x31); console_init(); } /* Halt if there was a built in self test failure */ post_code(0x34); report_bist_failure(bist); /* Load MPB */ val = cpuid_eax(1); printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); post_code(0x37); agesawrapper_amdinitreset(); post_code(0x39); agesawrapper_amdinitearly(); int s3resume = acpi_is_wakeup_s3(); if (!s3resume) { post_code(0x40); agesawrapper_amdinitpost(); post_code(0x42); agesawrapper_amdinitenv(); amd_initenv(); } else { /* S3 detect */ printk(BIOS_INFO, "S3 detected\n"); post_code(0x60); agesawrapper_amdinitresume(); agesawrapper_amds3laterestore(); post_code(0x61); prepare_for_resume(); } post_code(0x50); copy_and_run(); printk(BIOS_ERR, "Error: copy_and_run() returned!\n"); post_code(0x54); /* Should never see this post code. */ }
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; /* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for * LpcClk[1:0]". To be consistent with Parmer, setting to 4mA * even though the register is not documented in the Kabini BKDG. * Otherwise the serial output is bad code. */ outb(0xD2, 0xcd6); outb(0x00, 0xcd7); AGESAWRAPPER(amdinitmmio); hudson_lpc_port80(); if (!cpu_init_detectedx && boot_cpu()) { post_code(0x30); post_code(0x31); console_init(); } /* Halt if there was a built in self test failure */ post_code(0x34); report_bist_failure(bist); /* Load MPB */ val = cpuid_eax(1); printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx); /* On Larne, after LpcClkDrvSth is set, it needs some time to be stable, because of the buffer ICS551M */ int i; for(i = 0; i < 200000; i++) val = inb(0xcd6); post_code(0x37); AGESAWRAPPER(amdinitreset); post_code(0x38); printk(BIOS_DEBUG, "Got past yangtze_early_setup\n"); post_code(0x39); AGESAWRAPPER(amdinitearly); int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed(); if (!s3resume) { post_code(0x40); AGESAWRAPPER(amdinitpost); post_code(0x41); AGESAWRAPPER(amdinitenv); /* TODO: Disable cache is not ok. */ disable_cache_as_ram(); } else { /* S3 detect */ printk(BIOS_INFO, "S3 detected\n"); post_code(0x60); AGESAWRAPPER(amdinitresume); AGESAWRAPPER(amds3laterestore); post_code(0x61); prepare_for_resume(); } outb(0xEA, 0xCD6); outb(0x1, 0xcd7); post_code(0x50); copy_and_run(); post_code(0x54); /* Should never see this post code. */ }
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val, t32; u32 *addr32; /* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for * LpcClk[1:0]". To be consistent with Parmer, setting to 4mA * even though the register is not documented in the Kabini BKDG. * Otherwise the serial output is bad code. */ //outb(0xD2, 0xcd6); //outb(0x00, 0xcd7); amd_initmmio(); /* Set LPC decode enables. */ pci_devfn_t dev = PCI_DEV(0, 0x14, 3); pci_write_config32(dev, 0x44, 0xff03ffd5); hudson_lpc_port80(); /* Enable the AcpiMmio space */ outb(0x24, 0xcd6); outb(0x1, 0xcd7); /* Set auxiliary output clock frequency on OSCOUT1 pin to be 48MHz */ addr32 = (u32 *)0xfed80e28; t32 = *addr32; t32 &= 0xfff8ffff; *addr32 = t32; /* Enable Auxiliary Clock1, disable FCH 14 MHz OscClk */ addr32 = (u32 *)0xfed80e40; t32 = *addr32; t32 &= 0xffffbffb; *addr32 = t32; if (!cpu_init_detectedx && boot_cpu()) { post_code(0x30); post_code(0x31); /* w83627uhg has a default clk of 48MHz, p.9 of data-sheet */ winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); } /* Halt if there was a built in self test failure */ post_code(0x34); report_bist_failure(bist); /* Load MPB */ val = cpuid_eax(1); printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); /* On Larne, after LpcClkDrvSth is set, it needs some time to be stable, because of the buffer ICS551M */ int i; for(i = 0; i < 200000; i++) val = inb(0xcd6); post_code(0x37); agesawrapper_amdinitreset(); post_code(0x38); printk(BIOS_DEBUG, "Got past yangtze_early_setup\n"); post_code(0x39); agesawrapper_amdinitearly(); int s3resume = acpi_is_wakeup_s3(); if (!s3resume) { post_code(0x40); agesawrapper_amdinitpost(); post_code(0x41); agesawrapper_amdinitenv(); /* TODO: Disable cache is not ok. */ disable_cache_as_ram(); } else { /* S3 detect */ printk(BIOS_INFO, "S3 detected\n"); post_code(0x60); agesawrapper_amdinitresume(); amd_initcpuio(); agesawrapper_amds3laterestore(); post_code(0x61); prepare_for_resume(); } outb(0xEA, 0xCD6); outb(0x1, 0xcd7); post_code(0x50); copy_and_run(); post_code(0x54); /* Should never see this post code. */ }
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; #if CONFIG_SVI2_SLOW_SPEED device_t d18f3_dev = PCI_DEV(0, 0x18, 3); #endif //CONFIG_SVI2_SLOW_SPEED #if CONFIG_SVI_WAIT_COMP_DIS device_t d18f5_dev = PCI_DEV(0, 0x18, 5); #endif //CONFIG_SVI_WAIT_COMP_DIS /* * In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for * LpcClk[1:0]". This following register setting has been * replicated in every reference design since Parmer, so it is * believed to be required even though it is not documented in * the SoC BKDGs. Without this setting, there is no serial * output. */ outb(0xD2, 0xcd6); outb(0x00, 0xcd7); AGESAWRAPPER_PRE_CONSOLE(amdinitmmio); if (!cpu_init_detectedx && boot_cpu()) { u32 data, *memptr; hudson_lpc_port80(); // // Configure the GPIO's // HandleFchGpioTbl ( (GPIO_CONTROL *) &gGpioInitTable[0] ); hudson_clk_output_48Mhz(); post_code(0x31); console_init(); printk(BIOS_INFO, "14-25-48Mhz Clock settings\n"); memptr = (u32 *)(ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG28 ); data = *memptr; printk(BIOS_INFO, "FCH_MISC_REG28 is 0x%08x \n", data); memptr = (u32 *)(ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG40 ); data = *memptr; printk(BIOS_INFO, "FCH_MISC_REG40 is 0x%08x \n", data); // // Configure clock request // data = *((u32 *)(ACPI_MMIO_BASE + MISC_BASE+FCH_MISC_REG00)); data &= 0xFFFF0000; data |= (0 + 1) << (0 * 4); // CLKREQ 0 to CLK0 data |= (1 + 1) << (1 * 4); // CLKREQ 1 to CLK1 data |= (2 + 1) << (2 * 4); // CLKREQ 2 to CLK2 data |= (3 + 1) << (3 * 4); // CLKREQ 3 to CLK3 *((u32 *)(ACPI_MMIO_BASE + MISC_BASE+FCH_MISC_REG00)) = data; data = *((u32 *)(ACPI_MMIO_BASE + MISC_BASE+FCH_MISC_REG04)); data &= 0xFFFFFF0F; data |= 0xA << (1 * 4); // CLKREQ GFX to GFXCLK *((u32 *)(ACPI_MMIO_BASE + MISC_BASE+FCH_MISC_REG04)) = data; // // // // Configure clock strength // // // data = *((u32 *)(ACPI_MMIO_BASE + MISC_BASE+FCH_MISC_REG24)); // // data &= ~( (3 << 18) | (3 << 6) | (3 << 4) | (3 << 2) | (3 << 0) ); // data |= 3 << 18; // GFX CLOCK // data |= 3 << (0 * 2); // CLK0 // data |= 3 << (1 * 2); // CLK1 // data |= 3 << (2 * 2); // CLK2 // data |= 3 << (3 * 2); // CLK3 // // *((u32 *)(ACPI_MMIO_BASE + MISC_BASE+FCH_MISC_REG24)) = data; } /* Halt if there was a built in self test failure */ post_code(0x34); report_bist_failure(bist); /* Load MPB */ val = cpuid_eax(1); printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx); /* * This refers to LpcClkDrvSth settling time. Without this setting, processor * initialization is slow or incorrect, so this wait has been replicated from * earlier development boards. */ { int i; for(i = 0; i < 200000; i++) inb(0xCD6); } post_code(0x37); AGESAWRAPPER(amdinitreset); /* TODO There is no debug output between the return from amdinitreset and amdinitearly */ post_code(0x38); printk(BIOS_DEBUG, "Got past avalon_early_setup\n"); post_code(0x39); AGESAWRAPPER(amdinitearly); /* // Moved here to prevent double signon message // amdinitreset AGESA code might issue a reset when the hardware is in a wrong state. */ printk(BIOS_ERR, CONFIG_MAINBOARD_PART_NUMBER "\n"); printk(BIOS_ERR, "coreboot build " COREBOOT_YYYYMMDD_DATE "\n"); #if CONFIG_SVI2_SLOW_SPEED /* Force SVI2 to slow speed for APU2 */ val = pci_read_config32( d18f3_dev, 0xA0); if ( val & (1 << 14 ) ) { printk(BIOS_DEBUG, "SVI2 FREQUENCY 20 Mhz changing to 3.4\n"); val &= ~(1 << 14 ); pci_write_config32(d18f3_dev, 0xA0, val ); } else { printk(BIOS_DEBUG, "SVI2 FREQUENCY 3.4 Mhz\n"); } #endif //CONFIG_SVI2_SLOW_SPEED #if CONFIG_SVI_WAIT_COMP_DIS /* Disable SVI2 controller to wait for command completion */ val = pci_read_config32( d18f5_dev, 0x12C); if ( val & (1 << 30 ) ) { printk(BIOS_DEBUG, "SVI2 Wait completion disabled\n"); } else { printk(BIOS_DEBUG, "Disabling SVI2 Wait completion\n"); val |= (1 << 30 ); pci_write_config32(d18f5_dev, 0x12C, val ); } #endif //CONFIG_SVI_WAIT_COMP_DIS int s3resume = acpi_is_wakeup_s3(); if (!s3resume) { post_code(0x40); AGESAWRAPPER(amdinitpost); //PspMboxBiosCmdDramInfo(); post_code(0x41); AGESAWRAPPER(amdinitenv); /* If code hangs here, please check cahaltasm.S */ disable_cache_as_ram(); } else { /* S3 detect */ printk(BIOS_INFO, "S3 detected\n"); post_code(0x60); AGESAWRAPPER(amdinitresume); AGESAWRAPPER(amds3laterestore); post_code(0x61); prepare_for_resume(); } outb(0xEA, 0xCD6); outb(0x1, 0xcd7); post_code(0x50); copy_and_run(); post_code(0x54); /* Should never see this post code. */ }