static int codec_detect(u8 *base)
{
u32 reg32;
/* Set bit 0 to 0 to enter reset state (BAR + 0x8)[0]. */
if (set_bits(base + 0x08, 1, 0) == -1)
goto no_codec;
/* Set bit 0 to 1 to exit reset state (BAR + 0x8)[0]. */
if (set_bits(base + 0x08, 1, 1) == -1)
goto no_codec;
/* Read in codec location (BAR + 0xe)[2..0]. */
reg32 = read32(base + 0xe);
reg32 &= 0x0f;
if (!reg32)
goto no_codec;
return reg32;
no_codec:
/* Codec not found. */
/* Put HDA back in reset (BAR + 0x8)[0]. */
set_bits(base + 0x08, 1, 0);
printk(BIOS_DEBUG, "Azalia: No codec!\n");
return 0;
}
inline int stv6419_set_vsw( struct i2c_client *client, int sw, int type )
{
printk("[AVS]: %s: SET VSW: %d %d\n",__func__, sw, type);
if (type<0 || type>4)
{
return -EINVAL;
}
switch(sw)
{
case 0: // VCR video output selection
set_bits(regs, cReg2, type, 7, 1);
break;
case 1: // rgb selection
if (type<0 || type>2)
{
return -EINVAL;
}
set_bits(regs, cReg2, type, 5, 2);
break;
case 2: // TV video output selection
set_bits(regs, cReg2, type, 3, 2);
break;
default:
return -EINVAL;
}
dprintk("[AVS]: %s <\n", __func__);
return stv6419_set(client);
}
inline int stv6418_set_vsw( struct i2c_client *client, int sw, int type )
{
printk("[AVS]: %s: SET VSW: %d %d\n",__func__, sw, type);
if (type<0 || type>4)
{
return -EINVAL;
}
switch(sw)
{
case 0: // vcr
set_bits(regs, cReg2, type, 4, 3);
break;
case 1: // rgb
if (type<0 || type>2)
{
return -EINVAL;
}
set_bits(regs, cReg3, type, 2, 2);
break;
case 2: // tv
set_bits(regs, cReg2, type, 0, 3);
break;
default:
return -EINVAL;
}
dprintk("[AVS]: %s <\n", __func__);
return stv6418_set(client);
}
static u32 codec_detect(u32 base)
{
u32 dword;
/* Set Bit0 to 0 to enter reset state (BAR + 0x8)[0] */
if (set_bits(base + 0x08, 1, 0) == -1)
goto no_codec;
/* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */
if (set_bits(base + 0x08, 1, 1) == -1)
goto no_codec;
/* Delay for 1 ms since the BKDG does */
mdelay(1);
/* Read in Codec location (BAR + 0xe)[3..0]*/
dword = read32(base + 0xe);
dword &= 0x0F;
if (!dword)
goto no_codec;
return dword;
no_codec:
/* Codec Not found */
/* Put HDA back in reset (BAR + 0x8) [0] */
set_bits(base + 0x08, 1, 0);
printk(BIOS_DEBUG, "No codec!\n");
return 0;
}
static inline void set_fmt_bits(void __iomem *addr, u32 bits)
{
set_bits(addr + SPIFMT0, bits);
set_bits(addr + SPIFMT1, bits);
set_bits(addr + SPIFMT2, bits);
set_bits(addr + SPIFMT3, bits);
}
static int codec_detect(u32 base)
{
u8 reg8;
/* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */
if (set_bits(base + 0x08, 1, 1) == -1)
goto no_codec;
/* Write back the value once reset bit is set. */
write16(base + 0x0, read16(base + 0x0));
/* Read in Codec location (BAR + 0xe)[2..0]*/
reg8 = read8(base + 0xe);
reg8 &= 0x0f;
if (!reg8)
goto no_codec;
return reg8;
no_codec:
/* Codec Not found */
/* Put HDA back in reset (BAR + 0x8) [0] */
set_bits(base + 0x08, 1, 0);
printk(BIOS_DEBUG, "Azalia: No codec!\n");
return 0;
}
/**
* Probe for supported codecs
*/
int hda_codec_detect(u32 base)
{
u8 reg8;
/* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */
if (set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, HDA_GCTL_CRST) < 0)
goto no_codec;
/* Write back the value once reset bit is set. */
write16(base + HDA_GCAP_REG, read16(base + HDA_GCAP_REG));
/* Read in Codec location (BAR + 0xe)[2..0]*/
reg8 = read8(base + HDA_STATESTS_REG);
reg8 &= 0x0f;
if (!reg8)
goto no_codec;
return reg8;
no_codec:
/* Codec Not found */
/* Put HDA back in reset (BAR + 0x8) [0] */
set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, 0);
printk(BIOS_DEBUG, "HDA: No codec!\n");
return 0;
}
inline int stv6419_set_mute( struct i2c_client *client, int type )
{
dprintk("[AVS]: %s >\n", __func__);
if ((type<0) || (type>1))
{
return -EINVAL;
}
if (type == AVS_MUTE)
{
audio_value = get_bits(regs, cReg0, 0, 2);
set_bits(regs, cReg0, 0, 0, 2); /* audio mute */
}
else /* unmute with old values */
{
set_bits(regs, cReg0, audio_value, 0, 2); /* audio unmute */
audio_value = 0xff;
}
dprintk("[AVS]: %s <\n", __func__);
return stv6419_set(client);
}
static inline int d2083_audio_poweron(bool on)
{
int ret = 0;
int (*set_bits)(struct d2083 * const d2083, u8 const reg, u8 const mask);
if(on==true) {
audio_write(D2083_LDO1_MCTL_REG, 0x54);
audio_write(D2083_LDO_AUD_MCTL_REG, 0x54);
}
set_bits = (on) ? d2083_set_bits : d2083_clear_bits;
ret |= set_bits(d2083, D2083_PREAMP_A_CTRL1_REG, D2083_PREAMP_EN);
ret |= set_bits(d2083, D2083_PREAMP_B_CTRL1_REG, D2083_PREAMP_EN);
ret |= set_bits(d2083, D2083_MXHPR_CTRL_REG, D2083_MX_EN);
ret |= set_bits(d2083, D2083_MXHPL_CTRL_REG, D2083_MX_EN);
ret |= set_bits(d2083, D2083_CP_CTRL_REG, D2083_CP_EN);
if(on==false){
audio_write(D2083_CP_CTRL_REG,0xC9);
audio_write(D2083_LDO1_MCTL_REG, 0x00);
audio_write(D2083_LDO_AUD_MCTL_REG, 0x00);
}
return ret;
}
inline int stv6419_set_wss( struct i2c_client *client, int vol )
{
/* fixme: on stv6418 we hav more possibilites here
* think on this ->see register description below
*/
dprintk("[AVS]: %s >\n", __func__);
if (vol == SAA_WSS_43F)
{
set_bits(regs, cReg3, 3, 2, 3);
}
else if (vol == SAA_WSS_169F)
{
set_bits(regs, cReg3, 2, 2, 3);
}
else if (vol == SAA_WSS_OFF)
{
set_bits(regs, cReg3, 0, 2, 3);
}
else
{
return -EINVAL;
}
dprintk("[AVS]: %s <\n", __func__);
return stv6419_set(client);
}
static void test_bv_combined_boolean_ops(TestCase *tc, void *data)
{
BitVector *bv1 = bv_new();
BitVector *bv2 = bv_new();
BitVector *bv3;
BitVector *bv4;
BitVector *bv5;
BitVector *bv_empty = bv_new();
(void)data;
set_bits(bv1, "1, 5, 7");
set_bits(bv2, "1, 8, 20");
bv3 = bv_not(bv1);
Aiequal(bv3->size, bv1->size);
bv4 = bv_and(bv1, bv3);
Assert(bv_eq(bv4, bv_empty), "bv & ~bv == empty BitVector");
bv_destroy(bv4);
bv4 = bv_and(bv2, bv3);
bv5 = set_bits(bv_new(), "8, 20");
Assert(bv_eq(bv4, bv5), "~[1,5,7] & [1,8,20] == [8,20]");
bv_destroy(bv4);
bv_destroy(bv5);
bv4 = bv_or(bv1, bv3);
bv5 = bv_not(bv_empty);
Assert(bv_eq(bv4, bv5), "bv | ~bv == all 1s");
bv_destroy(bv4);
bv_destroy(bv5);
bv4 = bv_or(bv2, bv3);
bv5 = bv_not_x(set_bits(bv_new(), "5, 7"));
Assert(bv_eq(bv4, bv5), "~[1,5,7] | [1,8,20] == ~[5, 7]");
bv_destroy(bv4);
bv_destroy(bv5);
bv4 = bv_xor(bv1, bv3);
bv5 = bv_not(bv_empty);
Assert(bv_eq(bv4, bv5), "bv ^ ~bv == full BitVector");
bv_destroy(bv4);
bv_destroy(bv5);
bv4 = bv_xor(bv2, bv3);
bv5 = bv_not_x(set_bits(bv_new(), "5, 7, 8, 20"));
Assert(bv_eq(bv4, bv5), "~[1,5,7] ^ [1,8,20] == ~[5, 7, 8, 20]");
bv_destroy(bv4);
bv_destroy(bv5);
bv_destroy(bv1);
bv_destroy(bv2);
bv_destroy(bv3);
bv_destroy(bv_empty);
}
//*****************************************************************************
// Initialize Accelerometer
//*****************************************************************************
//
// This function initializes the accelerometer. Listed Below are the parameters
// that the accelerometer is initialized to.
void init_accel(){
// Enable X,Y and Z accelerometer axes
set_bits(CTRL9_XL, Xen_XL | Yen_XL | Zen_XL);
// Set accelerometer ODR to 1.66KHz and acceleration range to +/- 8G's
set_bits(CTRL1_XL, ODR_XL2 | FS_XL0 | FS_XL1);
// Enable data ready interrupt on INT1
set_bits(INT1_CTRL, INT1_DRDY_XL);
}
void breakpoint_Relocation::set_enabled(bool b) {
assert(!is_copy(), "cannot change breakpoint state when working on a copy");
if (enabled() == b) return;
if (b) {
set_bits(bits() | enabled_state);
} else {
set_active(false); // remove the actual breakpoint insn, if any
set_bits(bits() & ~enabled_state);
}
}
/* Tests bits set/clear/test functions */
static void test01(struct sb *sb, block_t blocks)
{
tux3_msg(sb, "---- test bitops ----");
unsigned char bits[16];
memset(bits, 0, sizeof(bits));
/* set some bits */
set_bits(bits, 6, 20);
set_bits(bits, 49, 16);
set_bits(bits, 0x51, 2);
/* test set bits */
test_assert(all_set(bits, 6, 20));
test_assert(all_set(bits, 49, 16));
test_assert(all_set(bits, 0x51, 2));
/* test clear bits */
test_assert(all_clear(bits, 6, 20) == 0);
test_assert(all_clear(bits, 49, 16) == 0);
test_assert(all_clear(bits, 0x51, 2) == 0);
/* should return false */
test_assert(all_set(bits, 5, 20) == 0);
test_assert(all_set(bits, 49, 17) == 0);
test_assert(all_set(bits, 0x51, 3) == 0);
test_assert(all_clear(bits, 5, 20) == 0);
test_assert(all_clear(bits, 49, 17) == 0);
test_assert(all_clear(bits, 0x51, 3) == 0);
/* all zero now */
clear_bits(bits, 6, 20);
clear_bits(bits, 49, 16);
clear_bits(bits, 0x51, 2);
test_assert(all_clear(bits, 0, 8 * sizeof(bits)));
test_assert(all_clear(bits, 6, 20));
test_assert(all_clear(bits, 49, 16));
test_assert(all_clear(bits, 0x51, 2));
test_assert(all_set(bits, 6, 20) == 0);
test_assert(all_set(bits, 49, 16) == 0);
test_assert(all_set(bits, 0x51, 2) == 0);
/* Corner case */
#if 1
unsigned char *bitmap = malloc(8); /* bitmap must be array of ulong */
#else
unsigned char *bitmap = malloc(7);
#endif
set_bits(bitmap, 0, 7 * 8);
test_assert(all_set(bitmap, 0, 7 * 8));
test_assert(all_clear(bitmap, 0, 7 * 8) == 0);
clear_bits(bitmap, 0, 7 * 8);
test_assert(all_clear(bitmap, 0, 7 * 8));
test_assert(all_set(bitmap, 0, 7 * 8) == 0);
free(bitmap);
clean_main(sb);
}
void init_gyro(){
// Enable X,Y and Z gyroscope axes
set_bits(CTRL10_C, Xen_G | Yen_G | Zen_G);
// Set gyroscope ODR to 1.66KHz angular rate to to 1000 degrees/second
set_bits(CTRL2_G, ODR_G2 | FS_G1);
// Enable gyroscope data ready interrupt on INT1
set_bits(INT2_CTRL, INT2_DRDY_G);
}
static void test_bv_eq_hash(TestCase *tc, void *data)
{
static int const COUNT = 1000;
int i;
BitVector *bv1 = bv_new();
BitVector *bv2 = bv_new();
(void)data;
test_bveq(bv1, bv2);
Assert(bv_eq(bv1, bv1), "bv_eq on self should work");
bv_set(bv1, 1);
test_bvneq(bv1, bv2);
bv_set(bv2, 11);
test_bvneq(bv1, bv2);
bv_set(bv1, 11);
bv_set(bv2, 1);
test_bveq(bv1, bv2);
/* This will increase size of bv1 to 1000 */
bv_unset(bv1, 1000);
/* difference in size shouldn't matter */
test_bveq(bv1, bv2);
for (i = 0; i < COUNT; i++) {
int bit = rand() % COUNT;
bv_set(bv1, bit);
bv_set(bv2, bit);
}
test_bveq(bv1, bv2);
bv_destroy(bv1);
bv_destroy(bv2);
/* although the saet bits will be equal, the extension will be different*/
bv1 = set_bits(bv_new(), "1, 3, 5");
bv2 = bv_not_x(set_bits(bv_new(), "0, 2, 4"));
bv_set(bv2, 5);
test_bvneq(bv1, bv2);
bv_destroy(bv2);
bv2 = set_bits(bv_new(), "1, 3, 5");
bv1 = bv_not_x(bv1);
bv2 = bv_not_x(bv2);
bv_unset(bv1, 1000);
test_bvneq(bv1, bv2);
bv_destroy(bv1);
bv_destroy(bv2);
}
void barrier() {
if (rank==0) {
printf("Rank 0 in barrier\n");
// Rank zero waits for the others
while (barrier_count != xcount*ycount-1) {}
barrier_count = 0; // Reset the count
for (int i=1;i<xcount*ycount;i++) {
// Send message to all ranks
uint32_t buffer = 0;
// Assemble header
set_bits(&buffer,i,OPTIMSOC_DEST_MSB,OPTIMSOC_DEST_LSB);
set_bits(&buffer,0,OPTIMSOC_CLASS_MSB,OPTIMSOC_CLASS_LSB);
set_bits(&buffer,0,OPTIMSOC_SRC_MSB,OPTIMSOC_SRC_LSB);
set_bits(&buffer,MSG_TYPE_BARRIER,1,0);
optimsoc_mp_simple_send(1,&buffer);
}
} else {
// Send message to rank 0
uint32_t buffer = 0;
// Assemble header
set_bits(&buffer,0,OPTIMSOC_DEST_MSB,OPTIMSOC_DEST_LSB);
set_bits(&buffer,0,OPTIMSOC_CLASS_MSB,OPTIMSOC_CLASS_LSB);
set_bits(&buffer,rank,OPTIMSOC_SRC_MSB,OPTIMSOC_SRC_LSB);
set_bits(&buffer,MSG_TYPE_BARRIER,1,0); // is a barrier
optimsoc_mp_simple_send(1,&buffer);
// Wait until we received the message of rank 0
while (barrier_continue==0) {}
// And reset signal
barrier_continue = 0;
}
}
static int codec_detect(u8 *base)
{
u32 reg32;
int count;
/* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */
if (set_bits(base + 0x08, 1, 1) == -1)
goto no_codec;
/* clear STATESTS bits (BAR + 0xE)[2:0] */
reg32 = read32(base + 0x0E);
reg32 |= 7;
write32(base + 0x0E, reg32);
/* Wait for readback of register to
* match what was just written to it
*/
count = 50;
do {
/* Wait 1ms based on BKDG wait time */
mdelay(1);
reg32 = read32(base + 0x0E);
} while ((reg32 != 0) && --count);
/* Timeout occured */
if (!count)
goto no_codec;
/* Set Bit0 to 0 to enter reset state (BAR + 0x8)[0] */
if (set_bits(base + 0x08, 1, 0) == -1)
goto no_codec;
/* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */
if (set_bits(base + 0x08, 1, 1) == -1)
goto no_codec;
/* Read in Codec location (BAR + 0xe)[2..0] */
reg32 = read32(base + 0xe);
reg32 &= 0x0f;
if (!reg32)
goto no_codec;
return reg32;
no_codec:
/* Codec Not found */
/* Put HDA back in reset (BAR + 0x8) [0] */
set_bits(base + 0x08, 1, 0);
printk(BIOS_DEBUG, "azalia_audio: No codec!\n");
return 0;
}
int stv6418_src_sel( struct i2c_client *client, int src )
{
dprintk("[AVS]: %s >\n", __func__);
if (src == SAA_SRC_ENC)
{
set_bits(regs, cReg2, stv6418_s_old_src, 0, 3); /* t_vsc */
set_bits(regs, cReg2, stv6418_s_old_src, 4, 3); /* v_vsc */
set_bits(regs, cReg1, 1, 0, 2); /* tc_asc */
set_bits(regs, cReg1, 1, 3, 2); /* v_asc */
}
else if(src == SAA_SRC_SCART)
{
stv6418_s_old_src = get_bits(regs, cReg2, 0, 3);
set_bits(regs, cReg2, 4, 0, 3);
set_bits(regs, cReg2, 0, 4, 3);
set_bits(regs, cReg1, 2, 0, 2);
set_bits(regs, cReg1, 0, 3, 2);
}
else
{
return -EINVAL;
}
dprintk("[AVS]: %s <\n", __func__);
return stv6418_set(client);
}
void leds_init(){
//LED 1 configuration
unset_bits(LED_1_PORTSEL, LED_1_PINMASK); //GPIO
unset_bits(LED_1_PORTSEL2, LED_1_PINMASK); //GPIO
unset_bits(LED_1_PORTOUT, LED_1_PINMASK); //set led off (low)
set_bits(LED_1_PORTDIR, LED_1_PINMASK); //output
//LED 2 configuration
unset_bits(LED_2_PORTSEL, LED_2_PINMASK); //GPIO
unset_bits(LED_2_PORTSEL2, LED_2_PINMASK); //GPIO
unset_bits(LED_2_PORTOUT, LED_2_PINMASK); //set led off (low)
set_bits(LED_2_PORTDIR, LED_2_PINMASK); //output
}
inline int stv6419_set_asw( struct i2c_client *client, int sw, int type )
{
dprintk("[AVS]: %s >\n", __func__);
switch(sw)
{
case 0:
case 1:
case 2:
if (type<=0 || type>3)
{
return -EINVAL;
}
/* if muted ? yes: save in temp */
if ( audio_value == 0xff )
set_bits(regs, cReg0, type, 0, 2);
else
audio_value = type;
break;
default:
return -EINVAL;
}
dprintk("[AVS]: %s <\n", __func__);
return stv6419_set(client);
}
static void cmd_char(const char *pf, char **args)
{
enum condition_type type = COND_CHAR;
bool not = false;
struct condition *c;
while (*pf) {
switch (*pf) {
case 'b':
type = COND_CHAR_BUFFER;
break;
case 'n':
not = true;
break;
}
pf++;
}
c = add_condition(type, args[1], args[2]);
if (!c)
return;
set_bits(c->u.cond_char.bitmap, args[0]);
if (not) {
int i;
for (i = 0; i < ARRAY_COUNT(c->u.cond_char.bitmap); i++)
c->u.cond_char.bitmap[i] = ~c->u.cond_char.bitmap[i];
}
}
static int codec_detect(u8 *base)
{
u32 dword;
int idx=0;
/* 1 */ // controller reset
printk(BIOS_DEBUG, "controller reset\n");
set_bits(base + 0x08, 1, 1);
do{
dword = read32(base + 0x08)&0x1;
if(idx++>1000) { printk(BIOS_DEBUG, "controller reset fail !!! \n"); break;}
} while (dword !=1);
dword=send_verb(base,0x000F0000); // get codec VendorId and DeviceId
if(dword==0) {
printk(BIOS_DEBUG, "No codec!\n");
return 0;
}
printk(BIOS_DEBUG, "Codec ID = %x\n", dword);
dword=0x1;
return dword;
}
int main(){
uint8_t rd_buf[1];
char str[6];
// Initialize UART
UART_Init(MY_UBRR);
init_twi();
sei();
init_LSM6DS3();
rd_buf[0] = check_bit(CTRL9_XL,SOFT_EN);
sprintf(str,"%02X\r\n",rd_buf[0]);
UART_Transmit_String(str);
set_bits(CTRL9_XL, SOFT_EN);
rd_buf[0] = check_bit(CTRL9_XL,SOFT_EN);
sprintf(str,"%02X\r\n",rd_buf[0]);
UART_Transmit_String(str);
clear_bits(CTRL9_XL, SOFT_EN);
rd_buf[0] = check_bit(CTRL9_XL,SOFT_EN);
sprintf(str,"%02X\r\n",rd_buf[0]);
UART_Transmit_String(str);
return 0;
}
void kvmppc_set_tsr_bits(struct kvm_vcpu *vcpu, u32 tsr_bits)
{
set_bits(tsr_bits, &vcpu->arch.tsr);
smp_wmb();
kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
kvm_vcpu_kick(vcpu);
}
/*
* Interface to control the chip select signal
*/
static void davinci_spi_chipselect(struct spi_device *spi, int value)
{
struct davinci_spi *davinci_spi;
u32 data1_reg_val = 0;
struct davinci_spi_platform_data *pdata;
int i;
davinci_spi = spi_master_get_devdata(spi->master);
pdata = davinci_spi->pdata;
/* board specific chip select logic decides the polarity and cs */
/* line for the controller */
if (value == BITBANG_CS_INACTIVE) {
/* set all chip select high */
if (pdata->chip_sel != NULL) {
for (i = 0; i < pdata->num_chipselect; i++) {
if (pdata->chip_sel[i] != DAVINCI_SPI_INTERN_CS)
gpio_set_value(pdata->chip_sel[i], 1);
}
}
set_bits(davinci_spi->base + SPIDEF, CS_DEFAULT);
data1_reg_val |= CS_DEFAULT << SPI_SPIDAT1_CSNR_SHIFT;
iowrite32(data1_reg_val, davinci_spi->base + SPIDAT1);
while (1)
if (ioread32(davinci_spi->base + SPIBUF)
& SPI_SPIBUF_RXEMPTY_MASK)
break;
}
}
static void print_feature_defs(void)
{
uint64_t base_feat[S390_FEAT_MAX / 64 + 1] = {};
uint64_t default_feat[S390_FEAT_MAX / 64 + 1] = {};
uint64_t full_feat[S390_FEAT_MAX / 64 + 1] = {};
int i, j;
printf("\n/* CPU model feature list data */\n");
for (i = 0; i < ARRAY_SIZE(CpuFeatDef); i++) {
set_bits(base_feat, CpuFeatDef[i].base_bits);
/* add the base to the default features */
set_bits(default_feat, CpuFeatDef[i].base_bits);
set_bits(default_feat, CpuFeatDef[i].default_bits);
/* add the base to the full features */
set_bits(full_feat, CpuFeatDef[i].base_bits);
set_bits(full_feat, CpuFeatDef[i].full_bits);
printf("#define %s_BASE\t", CpuFeatDef[i].name);
for (j = 0; j < ARRAY_SIZE(base_feat); j++) {
printf("0x%016"PRIx64"ULL", base_feat[j]);
if (j < ARRAY_SIZE(base_feat) - 1) {
printf(",");
} else {
printf("\n");
}
}
printf("#define %s_DEFAULT\t", CpuFeatDef[i].name);
for (j = 0; j < ARRAY_SIZE(default_feat); j++) {
printf("0x%016"PRIx64"ULL", default_feat[j]);
if (j < ARRAY_SIZE(default_feat) - 1) {
printf(",");
} else {
printf("\n");
}
}
printf("#define %s_FULL\t\t", CpuFeatDef[i].name);
for (j = 0; j < ARRAY_SIZE(full_feat); j++) {
printf("0x%016"PRIx64"ULL", full_feat[j]);
if (j < ARRAY_SIZE(full_feat) - 1) {
printf(",");
} else {
printf("\n");
}
}
}
}
/* si4713_s_modulator - set modulator attributes */
static int si4713_s_modulator(struct v4l2_subdev *sd, struct v4l2_modulator *vm)
{
struct si4713_device *sdev = to_si4713_device(sd);
int rval = 0;
u16 stereo, rds;
u32 p;
if (!sdev)
return -ENODEV;
if (vm->index > 0)
return -EINVAL;
/* Set audio mode: mono or stereo */
if (vm->txsubchans & V4L2_TUNER_SUB_STEREO)
stereo = 1;
else if (vm->txsubchans & V4L2_TUNER_SUB_MONO)
stereo = 0;
else
return -EINVAL;
rds = !!(vm->txsubchans & V4L2_TUNER_SUB_RDS);
mutex_lock(&sdev->mutex);
if (sdev->power_state) {
rval = si4713_read_property(sdev,
SI4713_TX_COMPONENT_ENABLE, &p);
if (rval < 0)
goto unlock;
p = set_bits(p, stereo, 1, 1 << 1);
p = set_bits(p, rds, 2, 1 << 2);
rval = si4713_write_property(sdev,
SI4713_TX_COMPONENT_ENABLE, p);
if (rval < 0)
goto unlock;
}
sdev->stereo = stereo;
sdev->rds_info.enabled = rds;
unlock:
mutex_unlock(&sdev->mutex);
return rval;
}
inline int stv6417_set_asw( struct i2c_client *client, int sw, int type )
{
unsigned char tmp_tv_value;
unsigned char tmp_vcr_value;
dprintk("%s >\n", __func__);
// I don't get what this does, seems to be not used
return 0;
switch(sw)
{
case 0:
if (type<=0 || type>3)
{
return -EINVAL;
}
/* if muted ? yes: save in temp */
tmp_tv_value = get_bits(regs, AOS_TV_REG, AOS_TV_START, AOS_TV_SIZE);
tmp_vcr_value = get_bits(regs, AOS_VCR_REG, AOS_VCR_START, AOS_VCR_SIZE);
if ( vcr_value == 0xff )
set_bits(regs, cReg1, type, 3, 2);
else
vcr_value = type;
break;
case 1:
case 2:
if (type<=0 || type>4)
{
return -EINVAL;
}
/* if muted ? yes: save in temp */
if ( tv_value == 0xff )
set_bits(regs, cReg1, type, 0, 2);
else
tv_value = type;
break;
default:
return -EINVAL;
}
dprintk("%s <\n", __func__);
return stv6417_set(client);
}
void write_regbits(__u32 reg, int high_bit, int low_bit, __u32 value)
{
__u32 curval = read_register(reg);
set_bits(&curval, reg, high_bit, low_bit, value);
write_register(reg, curval);
}
