/* * this is all a bit magic. the soc.exceptvec register is effectively * undocumented. we had to look at linux and experiment, alas. this is the * sort of thing that should be standardised as part of the cortex mpcore spec. * even intel document their equivalent procedure. */ int startcpu(uint cpu) { int i, r; ulong oldvec, rstaddr; ulong *evp = (ulong *)soc.exceptvec; /* magic */ r = 0; if (getncpus() < 2 || cpu == m->machno || cpu >= MAXMACH || cpu >= navailcpus) return -1; oldvec = *evp; l1cache->wb(); /* start next cpu w same view of ram */ *evp = rstaddr = PADDR(_vrst); /* will start cpu executing at _vrst */ coherence(); l1cache->wb(); unfreeze(cpu); for (i = 2000; i > 0 && *evp == rstaddr; i--) delay(1); if (i <= 0 || *evp != cpu) { iprint("cpu%d: didn't start!\n", cpu); stopcpu(cpu); /* make sure it's stopped */ r = -1; } *evp = oldvec; return r; }
/* * exit kernel either on a panic or user request */ void exit(int code) { shutdown(code); splhi(); if (m->machno == 0) archreboot(); else { intrcpushutdown(); stopcpu(m->machno); for (;;) idlehands(); } }
/* * at entry, l.s has set m for cpu0 and printed "Plan 9 from Be" * but has not zeroed bss. */ void main(void) { int cpu; static ulong vfy = 0xcafebabe; up = nil; if (vfy != 0xcafebabe) { serialputc('?'); serialputc('d'); panic("data segment misaligned"); } memset(edata, 0, end - edata); /* * we can't lock until smpon has run, but we're supposed to wait * until l1 & l2 are on. too bad. l1 is on, l2 will soon be. */ smpon(); iprint("ll Labs "); cacheinit(); /* * data segment is aligned, bss is zeroed, caches' characteristics * are known. begin initialisation. */ mach0init(); l2pageinit(); mmuinit(); optionsinit("/boot/boot boot"); quotefmtinstall(); /* want plan9.ini to be able to affect memory sizing in confinit */ plan9iniinit(); /* before we step on plan9.ini in low memory */ /* l2 looks for *l2off= in plan9.ini */ l2cache->on(); /* l2->on requires locks to work, thus smpon */ l2cache->info(&cachel[2]); allcache->on(); cortexa9cachecfg(); trapinit(); /* so confinit can probe memory to size it */ confinit(); /* figures out amount of memory */ /* xinit prints (if it can), so finish up the banner here. */ delay(100); navailcpus = getncpus(); iprint("(mp arm; %d cpus)\n\n", navailcpus); delay(100); for (cpu = 1; cpu < navailcpus; cpu++) stopcpu(cpu); xinit(); irqtooearly = 0; /* now that xinit and trapinit have run */ mainmem->flags |= POOL_ANTAGONISM /* | POOL_PARANOIA */ ; /* * Printinit will cause the first malloc call. * (printinit->qopen->malloc) unless any of the * above (like clockinit) do an irqenable, which * will call malloc. * If the system dies here it's probably due * to malloc(->xalloc) not being initialised * correctly, or the data segment is misaligned * (it's amazing how far you can get with * things like that completely broken). * * (Should be) boilerplate from here on. */ archreset(); /* cfg clock signals, print cache cfg */ clockinit(); /* start clocks */ timersinit(); delay(50); /* let uart catch up */ printinit(); kbdenable(); cpuidprint(); chkmissing(); procinit0(); initseg(); // dmainit(); links(); conf.monitor = 1; // screeninit(); iprint("pcireset..."); pcireset(); /* this tends to hang after a reboot */ iprint("ok\n"); chandevreset(); /* most devices are discovered here */ // i8250console(); /* too early; see init0 */ pageinit(); /* prints "1020M memory: ⋯ */ swapinit(); userinit(); /* * starting a cpu will eventually result in it calling schedinit, * so everything necessary to run user processes should be set up * before starting secondary cpus. */ launchinit(); /* SMP & FW are already on when we get here; u-boot set them? */ for (cpu = 1; cpu < navailcpus; cpu++) if (startcpu(cpu) < 0) panic("cpu%d didn't start", cpu); l1diag(); schedinit(); panic("cpu%d: schedinit returned", m->machno); }