static void mt7628_ephy_init(void) { int i; u32 val; val = sysRegRead(REG_AGPIOCFG); val &= ~(MT7628_P0_EPHY_AIO_EN | MT7628_P1_EPHY_AIO_EN | MT7628_P2_EPHY_AIO_EN | MT7628_P3_EPHY_AIO_EN | MT7628_P4_EPHY_AIO_EN); sysRegWrite(REG_AGPIOCFG, val); // reset EPHY esw_ephy_reset(); udelay(5000); /* set P0~P4 EPHY LED mode */ sysRegRead(RALINK_SYSCTL_BASE + 0x64); val &= 0xf003f003; sysRegWrite(RALINK_SYSCTL_BASE + 0x64, val); mii_mgr_write(0, 31, 0x2000); // change G2 page mii_mgr_write(0, 26, 0x0000); for(i=0; i<5; i++) { mii_mgr_write(i, 31, 0x8000); // change L0 page mii_mgr_write(i, 0, 0x3100); #if defined (CONFIG_RAETH_8023AZ_EEE) mii_mgr_read(i, 26, &phy_val); // EEE setting phy_val |= (1 << 5); mii_mgr_write(i, 26, phy_val); #endif mii_mgr_write(i, 30, 0xa000); mii_mgr_write(i, 31, 0xa000); // change L2 page mii_mgr_write(i, 16, 0x0606); mii_mgr_write(i, 23, 0x0f0e); mii_mgr_write(i, 24, 0x1610); mii_mgr_write(i, 30, 0x1f15); mii_mgr_write(i, 28, 0x6111); #if 0 mii_mgr_read(i, 4, &phy_val); phy_val |= (1 << 10); mii_mgr_write(i, 4, phy_val); mii_mgr_write(i, 31, 0x2000); // change G2 page mii_mgr_write(i, 26, 0x0000); #endif } //100Base AOI setting mii_mgr_write(0, 31, 0x5000); //change G5 page mii_mgr_write(0, 19, 0x004a); mii_mgr_write(0, 20, 0x015a); mii_mgr_write(0, 21, 0x00ee); mii_mgr_write(0, 22, 0x0033); mii_mgr_write(0, 23, 0x020a); mii_mgr_write(0, 24, 0x0000); mii_mgr_write(0, 25, 0x024a); mii_mgr_write(0, 26, 0x035a); mii_mgr_write(0, 27, 0x02ee); mii_mgr_write(0, 28, 0x0233); mii_mgr_write(0, 29, 0x000a); mii_mgr_write(0, 30, 0x0000); }
void enable_auto_negotiate(int ge) { #if defined (CONFIG_RALINK_RT3052) || defined (CONFIG_RALINK_RT3352) || defined (CONFIG_RALINK_RT5350) u32 regValue = sysRegRead(0xb01100C8); #else u32 regValue; regValue = (ge == 2)? sysRegRead(MDIO_CFG2) : sysRegRead(MDIO_CFG); #endif regValue &= 0xe0ff7fff; // clear auto polling related field: // (MD_PHY1ADDR & GP1_FRC_EN). regValue |= 0x20000000; // force to enable MDC/MDIO auto polling. #if defined (CONFIG_GE2_RGMII_AN) || defined (CONFIG_GE2_MII_AN) if(ge==2) { regValue |= (CONFIG_MAC_TO_GIGAPHY_MODE_ADDR2 << 24); // setup PHY address for auto polling. } #endif #if defined (CONFIG_GE1_RGMII_AN) || defined (CONFIG_GE1_MII_AN) || defined (CONFIG_P5_MAC_TO_PHY_MODE) if(ge==1) { regValue |= (CONFIG_MAC_TO_GIGAPHY_MODE_ADDR << 24); // setup PHY address for auto polling. } #endif #if defined (CONFIG_RALINK_RT3052) || defined (CONFIG_RALINK_RT3352) || defined (CONFIG_RALINK_RT5350) sysRegWrite(0xb01100C8, regValue); #else if (ge == 2) sysRegWrite(MDIO_CFG2, regValue); else sysRegWrite(MDIO_CFG, regValue); #endif }
static void read_counters_gdma2(PSEUDO_ADAPTER *pPseudoAd) { u32 tx_skipped; u32 rx_fcs_bad; u32 rx_too_sho; u32 rx_too_lon; pPseudoAd->stat.tx_bytes += sysRegRead(GDMA2_TX_GBCNT); pPseudoAd->stat.tx_packets += sysRegRead(GDMA2_TX_GPCNT); tx_skipped = sysRegRead(GDMA2_TX_SKIPCNT); pPseudoAd->stat.collisions += sysRegRead(GDMA2_TX_COLCNT); pPseudoAd->stat.rx_bytes += sysRegRead(GDMA2_RX_GBCNT); pPseudoAd->stat.rx_packets += sysRegRead(GDMA2_RX_GPCNT); pPseudoAd->stat.rx_over_errors += sysRegRead(GDMA2_RX_OERCNT); rx_fcs_bad = sysRegRead(GDMA2_RX_FERCNT); rx_too_sho = sysRegRead(GDMA2_RX_SERCNT); rx_too_lon = sysRegRead(GDMA2_RX_LERCNT); if (tx_skipped) pPseudoAd->stat.tx_dropped += tx_skipped; if (rx_too_sho) pPseudoAd->stat.rx_length_errors += rx_too_sho; if (rx_too_lon) pPseudoAd->stat.rx_length_errors += rx_too_lon; if (rx_fcs_bad) { pPseudoAd->stat.rx_errors += rx_fcs_bad; pPseudoAd->stat.rx_crc_errors += rx_fcs_bad; } }
static void fe_reset(void) { u32 val; val = sysRegRead(REG_RSTCTRL); /* RT5350/MT7628 (SDMA) need to reset ESW and FE at the same to avoid PDMA panic */ #if defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_MT7628) val |= RALINK_ESW_RST; #endif /* Reset PPE at this point */ #if defined (CONFIG_RALINK_MT7620) || defined (CONFIG_RALINK_MT7621) val |= RALINK_PPE_RST; #endif /* MT7621 + TRGMII need to reset GMAC */ #if defined (CONFIG_RALINK_MT7621) && defined (CONFIG_GE1_TRGMII_FORCE_1200) val |= RALINK_ETH_RST; #endif val |= RALINK_FE_RST; sysRegWrite(REG_RSTCTRL, val); udelay(10); /* set TRGMII clock */ #if defined (CONFIG_RALINK_MT7621) && defined (CONFIG_GE1_TRGMII_FORCE_1200) { u32 val_clk = sysRegRead(REG_CLK_CFG_0); val_clk &= 0xffffff9f; val_clk |= (0x1 << 5); sysRegWrite(REG_CLK_CFG_0, val_clk); udelay(1000); } #endif #if defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_MT7628) || defined (CONFIG_RALINK_MT7620) val &= ~(RALINK_ESW_RST); #endif #if defined (CONFIG_RALINK_MT7620) val &= ~(RALINK_EPHY_RST); #endif #if defined (CONFIG_RALINK_MT7621) val &= ~(RALINK_ETH_RST | RALINK_HSDMA_RST); #endif #if defined (CONFIG_RALINK_MT7620) || defined (CONFIG_RALINK_MT7621) val &= ~(RALINK_PPE_RST); #endif val &= ~(RALINK_FE_RST); sysRegWrite(REG_RSTCTRL, val); udelay(1000); }
static int aes_engine_desc_init(void) { int i; u32 regVal; AES_Entry.AES_tx_ring0 = dma_alloc_coherent(NULL, NUM_AES_TX_DESC * sizeof(struct AES_txdesc), &AES_Entry.phy_aes_tx_ring0, GFP_KERNEL); if (!AES_Entry.AES_tx_ring0) goto err_cleanup; AES_Entry.AES_rx_ring0 = dma_alloc_coherent(NULL, NUM_AES_RX_DESC * sizeof(struct AES_rxdesc), &AES_Entry.phy_aes_rx_ring0, GFP_KERNEL); if (!AES_Entry.AES_rx_ring0) goto err_cleanup; for (i = 0; i < NUM_AES_TX_DESC; i++) { memset(&AES_Entry.AES_tx_ring0[i], 0, sizeof(struct AES_txdesc)); AES_Entry.AES_tx_ring0[i].txd_info2 |= TX2_DMA_DONE; } for (i = 0; i < NUM_AES_RX_DESC; i++) { memset(&AES_Entry.AES_rx_ring0[i], 0, sizeof(struct AES_rxdesc)); } AES_Entry.aes_tx_front_idx = 0; AES_Entry.aes_tx_rear_idx = NUM_AES_TX_DESC-1; AES_Entry.aes_rx_front_idx = 0; AES_Entry.aes_rx_rear_idx = NUM_AES_RX_DESC-1; wmb(); regVal = sysRegRead(AES_GLO_CFG); regVal &= 0x00000ff0; sysRegWrite(AES_GLO_CFG, regVal); regVal = sysRegRead(AES_GLO_CFG); sysRegWrite(AES_TX_BASE_PTR0, phys_to_bus((u32)AES_Entry.phy_aes_tx_ring0)); sysRegWrite(AES_TX_MAX_CNT0, cpu_to_le32((u32)NUM_AES_TX_DESC)); sysRegWrite(AES_TX_CTX_IDX0, 0); sysRegWrite(AES_RST_CFG, AES_PST_DTX_IDX0); sysRegWrite(AES_RX_BASE_PTR0, phys_to_bus((u32)AES_Entry.phy_aes_rx_ring0)); sysRegWrite(AES_RX_MAX_CNT0, cpu_to_le32((u32)NUM_AES_RX_DESC)); sysRegWrite(AES_RX_CALC_IDX0, cpu_to_le32((u32)(NUM_AES_RX_DESC - 1))); regVal = sysRegRead(AES_RX_CALC_IDX0); sysRegWrite(AES_RST_CFG, AES_PST_DRX_IDX0); return 0; err_cleanup: aes_engine_desc_free(); return -ENOMEM; }
void ra2880Mac2AddressSet(MAC_INFO *MACInfo, unsigned char p[6]) { unsigned long regValue; regValue = (p[0] << 8) | (p[1]); sysRegWrite(GDMA2_MAC_ADRH, regValue); regValue = (p[2] << 24) | (p[3] <<16) | (p[4] << 8) | p[5]; sysRegWrite(GDMA2_MAC_ADRL, regValue); printk("GDMA2_MAC_ADRH -- : 0x%08x\n", sysRegRead(GDMA2_MAC_ADRH)); printk("GDMA2_MAC_ADRL -- : 0x%08x\n", sysRegRead(GDMA2_MAC_ADRL)); return; }
static void fe_dma_stop(void) { u32 regValue; regValue = sysRegRead(PDMA_GLO_CFG); regValue &= ~(TX_WB_DDONE | RX_DMA_EN | TX_DMA_EN); sysRegWrite(PDMA_GLO_CFG, regValue); #if defined (CONFIG_RAETH_QDMA) regValue = sysRegRead(QDMA_GLO_CFG); regValue &= ~(TX_WB_DDONE | RX_DMA_EN | TX_DMA_EN); sysRegWrite(QDMA_GLO_CFG, regValue); #endif }
u32 mii_mgr_read(u32 phy_addr, u32 phy_register, u32 *read_data) { u32 volatile status = 0; u32 rc = 0; unsigned long volatile t_start = jiffies; u32 volatile data = 0; /* We enable mdio gpio purpose register, and disable it when exit. */ enable_mdio(1); // make sure previous read operation is complete while (1) { // 0 : Read/write operation complete if(!( sysRegRead(MDIO_PHY_CONTROL_0) & (0x1 << 31))) { break; } else if (time_after(jiffies, t_start + 5*HZ)) { enable_mdio(0); printk("\n MDIO Read operation is ongoing !!\n"); return rc; } } data = (0x01 << 16) | (0x02 << 18) | (phy_addr << 20) | (phy_register << 25); sysRegWrite(MDIO_PHY_CONTROL_0, data); data |= (1<<31); sysRegWrite(MDIO_PHY_CONTROL_0, data); //printk("\n Set Command [0x%08X] to PHY !!\n",MDIO_PHY_CONTROL_0); // make sure read operation is complete t_start = jiffies; while (1) { if (!(sysRegRead(MDIO_PHY_CONTROL_0) & (0x1 << 31))) { status = sysRegRead(MDIO_PHY_CONTROL_0); *read_data = (u32)(status & 0x0000FFFF); enable_mdio(0); return 1; } else if (time_after(jiffies, t_start+5*HZ)) { enable_mdio(0); printk("\n MDIO Read operation is ongoing and Time Out!!\n"); return 0; } } }
static int et_virt_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause) { int mdio_cfg_reg; int mii_an_reg; PSEUDO_ADAPTER *pseudo = dev->priv; //printk("et_set_pauseparam(): autoneg=%d, tx_pause=%d, rx_pause=%d\n", epause->autoneg, epause->tx_pause, epause->rx_pause); // auto-neg pause mii_mgr_read(pseudo->mii_info.phy_id, AUTO_NEGOTIATION_ADVERTISEMENT, &mii_an_reg); if(epause->autoneg) mii_an_reg |= AN_PAUSE; else mii_an_reg &= ~AN_PAUSE; mii_mgr_write(pseudo->mii_info.phy_id, AUTO_NEGOTIATION_ADVERTISEMENT, mii_an_reg); // tx/rx pause mdio_cfg_reg = sysRegRead(MDIO_CFG); if(epause->tx_pause) mdio_cfg_reg |= MDIO_CFG_GP1_FC_TX; else mdio_cfg_reg &= ~MDIO_CFG_GP1_FC_TX; if(epause->rx_pause) mdio_cfg_reg |= MDIO_CFG_GP1_FC_RX; else mdio_cfg_reg &= ~MDIO_CFG_GP1_FC_RX; sysRegWrite(MDIO_CFG, mdio_cfg_reg); return 0; }
static void RaWdgStart(void) { #if defined (CONFIG_RALINK_RT6855A) int HwConf; #endif printk(KERN_INFO "Started WatchDog Timer.\n"); SetTimerMode(TMR1CTL,WATCHDOG); #if defined (CONFIG_RALINK_RT2880) || defined (CONFIG_RALINK_RT2883) || \ defined (CONFIG_RALINK_RT3052) || defined (CONFIG_RALINK_RT3883) /* * For user easy configuration, We assume the unit of watch dog timer is 1s, * so we need to calculate the TMR1LOAD value. * * Unit= 1/(SysClk/65536), 1 Sec = (SysClk)/65536 * */ SetWdgTimerClock(TMR1CTL,SYS_CLK_DIV65536); WdgLoadValue = WATCHDOG_TIMEOUT * (get_surfboard_sysclk()/65536); #elif defined (CONFIG_RALINK_RT6855A) HwConf = sysRegRead(RALINK_SYSCTL_BASE + 0x8c); if(((HwConf >> 24) & 0x3) == 0) { //SDR WdgLoadValue = WATCHDOG_TIMEOUT * (140 * 1000 * 1000 / 2); }else { if(((HwConf >> 26) & 0x1) == 0) {
static void wait_dma_stop(int cycles_10ms) { int i; u32 regVal; for (i = 0; i < cycles_10ms; i++) { regVal = sysRegRead(PDMA_GLO_CFG); #if defined (CONFIG_RAETH_QDMA) regVal |= sysRegRead(QDMA_GLO_CFG); #endif if (!(regVal & (RX_DMA_BUSY | TX_DMA_BUSY))) break; msleep(10); } }
void ra2880EnableInterrupt() { unsigned int regValue = sysRegRead(FE_INT_ENABLE); RAETH_PRINT("FE_INT_ENABLE -- : 0x%08x\n", regValue); // regValue |= (RX_DONE_INT0 | TX_DONE_INT0); sysRegWrite(FE_INT_ENABLE, regValue); }
void SetWdgTimerClock(int prescale) { unsigned int result; result=sysRegRead(TMR1CTL); result &= 0x0000FFFF; result |= (prescale << 16); //unit = 1u sysRegWrite(TMR1CTL, result); }
void set_wdg_timer_mode(unsigned int timer, enum timer_mode mode) { unsigned int result; result = sysRegRead(timer); result &= ~(0x3<<4); result |= (mode << 4); sysRegWrite(timer, result); }
void set_wdg_timer_clock_prescale(unsigned int timer, enum timer_clock_freq prescale) { unsigned int result; result = sysRegRead(timer); result &= ~0xF; result |= (prescale & 0xF); sysRegWrite(timer, result); }
void set_wdg_timer_clock_prescale(int prescale) { unsigned int result; result = sysRegRead(TMR1CTL); result &= 0x0000FFFF; result |= (prescale << 16); //unit = 1u sysRegWrite(TMR1CTL, result); }
void SetWdgTimerClock(unsigned int timer, enum timer_clock_freq prescale) { unsigned int result; result=sysRegRead(timer); result &= ~0xF; result=result | (prescale&0xF); sysRegWrite(timer,result); }
void SetTimerMode(unsigned int timer, enum timer_mode mode) { unsigned int result; result=sysRegRead(timer); result &= ~(0x3<<4); //watchdog mode result=result | (mode << 4); sysRegWrite(timer,result); }
static int ar2315_wdt_release(struct inode *inode, struct file *file) { if (!strcmp (get_arch_type (), "Atheros AR5315")) { printk("%s: release with %d left\n", __FUNCTION__, CYCLES_TO_S(sysRegRead(AR5315_WD))); }else { printk("%s: release with %d left\n", __FUNCTION__, CYCLES_TO_S(sysRegRead(AR531X_WD))); } // uncomment the below if closing this device should prevent the // watchdog from rebooting the system //started = 0; //sysRegWrite(AR5315_WDC, AR531X_WD_CTRL_DEFAULT); //sysRegWrite(AR5315_WD, 0); clear_bit(0, &wdt_is_open); return 0; }
u32 mii_mgr_write(u32 phy_addr, u32 phy_register, u32 write_data) { unsigned long volatile t_start=jiffies; u32 volatile data; enable_mdio(1); // make sure previous write operation is complete while(1) { if (!(sysRegRead(MDIO_PHY_CONTROL_0) & (0x1 << 31))) { break; } else if (time_after(jiffies, t_start + 5 * HZ)) { enable_mdio(0); printk("\n MDIO Write operation ongoing\n"); return 0; } } data = (0x01 << 16)| (1<<18) | (phy_addr << 20) | (phy_register << 25) | write_data; sysRegWrite(MDIO_PHY_CONTROL_0, data); data |= (1<<31); sysRegWrite(MDIO_PHY_CONTROL_0, data); //start operation //printk("\n Set Command [0x%08X] to PHY !!\n",MDIO_PHY_CONTROL_0); t_start = jiffies; // make sure write operation is complete while (1) { if (!(sysRegRead(MDIO_PHY_CONTROL_0) & (0x1 << 31))) //0 : Read/write operation complete { enable_mdio(0); return 1; } else if (time_after(jiffies, t_start + 5 * HZ)) { enable_mdio(0); printk("\n MDIO Write operation Time Out\n"); return 0; } } }
void SetWdgTimerClock(unsigned int timer, enum timer_clock_freq prescale) { #if !defined (CONFIG_RALINK_RT63365) unsigned int result; result=sysRegRead(timer); result &= ~0xF; result=result | (prescale&0xF); sysRegWrite(timer,result); #endif }
void enable_mdio(int enable) { #if !defined (CONFIG_P5_MAC_TO_PHY_MODE) u32 data = sysRegRead(GPIO_PRUPOSE); if (enable) data &= ~GPIO_MDIO_BIT; else data |= GPIO_MDIO_BIT; sysRegWrite(GPIO_PRUPOSE, data); #endif }
void SetTimerMode(unsigned int timer, enum timer_mode mode) { #if !defined (CONFIG_RALINK_RT63365) unsigned int result; result=sysRegRead(timer); result &= ~(0x3<<4); //watchdog mode result=result | (mode << 4); sysRegWrite(timer,result); #endif }
static void aes_engine_stop(void) { int i; u32 regValue; regValue = sysRegRead(AES_GLO_CFG); regValue &= ~(AES_TX_WB_DDONE | AES_RX_DMA_EN | AES_TX_DMA_EN); sysRegWrite(AES_GLO_CFG, regValue); /* wait AES stopped */ for (i = 0; i < 50; i++) { msleep(1); regValue = sysRegRead(AES_GLO_CFG); if (!(regValue & (AES_RX_DMA_BUSY | AES_TX_DMA_BUSY))) break; } /* disable AES interrupt */ sysRegWrite(AES_INT_MASK, 0); }
static void aes_engine_reset(void) { u32 val; val = sysRegRead(REG_CLKCTRL); val |= RALINK_CRYPTO_CLK_EN; sysRegWrite(REG_CLKCTRL, val); udelay(10); val = sysRegRead(REG_RSTCTRL); val |= RALINK_CRYPTO_RST; sysRegWrite(REG_RSTCTRL, val); udelay(10); val &= ~(RALINK_CRYPTO_RST); sysRegWrite(REG_RSTCTRL, val); udelay(100); }
static int et_virt_set_rx_csum(struct net_device *dev, u32 data) { int value; //printk("et_set_rx_csum(): data = %d\n", data); value = sysRegRead(GDMA2_FWD_CFG); if(data) value |= GDM1_STRPCRC; else value &= ~GDM1_STRPCRC; sysRegWrite(GDMA1_FWD_CFG, value); return 0; }
void ra2880stop(END_DEVICE *ei_local) { unsigned int regValue; printk("ra2880stop()..."); regValue = sysRegRead(PDMA_GLO_CFG); regValue &= ~(TX_WB_DDONE | RX_DMA_EN | TX_DMA_EN); sysRegWrite(PDMA_GLO_CFG, regValue); printk("Done\n"); // printk("Done0x%x...\n", readreg(PDMA_GLO_CFG)); }
static void esw_ephy_reset(void) { /* reset EPHY */ u32 val = sysRegRead(REG_RSTCTRL); val |= RALINK_EPHY_RST; sysRegWrite(REG_RSTCTRL, val); udelay(10); val &= ~(RALINK_EPHY_RST); sysRegWrite(REG_RSTCTRL, val); udelay(100); }
/****************************************************************************** * ae531x_reset -- Cold reset ethernet interface */ void ae531x_reset(ae531x_MAC_t *MACInfo) { UINT32 mask = 0; UINT32 regtmp; if (MACInfo->unit == 0) { mask = RESET_ENET0 | RESET_EPHY0; } else { mask = RESET_ENET1 | RESET_EPHY1; #ifdef TWISTED_ENET_MACS mask |= RESET_ENET0 | RESET_EPHY0; #endif } /* Put into reset */ regtmp = sysRegRead(AR531X_RESET); sysRegWrite(AR531X_RESET, regtmp | mask); sysMsDelay(15); /* Pull out of reset */ regtmp = sysRegRead(AR531X_RESET); sysRegWrite(AR531X_RESET, regtmp & ~mask); sysUDelay(25); /* Enable */ if (MACInfo->unit == 0) { mask = ENABLE_ENET0; } else { mask = ENABLE_ENET1; #ifdef TWISTED_ENET_MACS mask |= ENABLE_ENET0; #endif } regtmp = sysRegRead(AR531X_ENABLE); sysRegWrite(AR531X_ENABLE, regtmp | mask); }
static void ar2315_wdt_print_info(void) { printk("watchdog hb: %d", heartbeat); if (!strcmp (get_arch_type (), "Atheros AR5315")) { printk(" ISR: 0x%x", sysRegRead(AR5315_ISR)); printk(" IMR: 0x%x", sysRegRead(AR5315_IMR)); printk(" WD : 0x%x", sysRegRead(AR5315_WD)); printk(" WDC: 0x%x\n", sysRegRead(AR5315_WDC)); }else{ printk(" ISR: 0x%x", sysRegRead(AR531X_ISR)); printk(" IMR: 0x%x", sysRegRead(AR531X_IMR)); printk(" WD : 0x%x", sysRegRead(AR531X_WD)); printk(" WDC: 0x%x\n", sysRegRead(AR531X_WDC)); } }