void saturn_state::scu_single_transfer(address_space &space, UINT32 src, UINT32 dst,UINT8 *src_shift)
{
UINT32 src_data;
if(src & 1)
{
/* Road Blaster does a work ram h to color ram with offsetted source address, do some data rotation */
src_data = ((space.read_dword(src & 0x07fffffc) & 0x00ffffff)<<8);
src_data |= ((space.read_dword((src & 0x07fffffc)+4) & 0xff000000) >> 24);
src_data >>= (*src_shift)*16;
}
void dc_state::g2_dma_execute(address_space &space, int channel)
{
UINT32 src,dst,size;
dst = m_g2_dma[channel].g2_addr;
src = m_g2_dma[channel].root_addr;
size = 0;
/* 0 rounding size = 32 Mbytes */
if (m_g2_dma[channel].size == 0) { m_g2_dma[channel].size = 0x200000; }
if (m_g2_dma[channel].dir == 0)
{
for (; size<m_g2_dma[channel].size; size += 4)
{
space.write_dword(dst,space.read_dword(src));
src+=4;
dst+=4;
}
}
else
{
for (; size<m_g2_dma[channel].size; size += 4)
{
space.write_dword(src,space.read_dword(dst));
src+=4;
dst+=4;
}
}
/* update the params*/
m_g2_dma[channel].g2_addr = g2bus_regs[SB_ADSTAG + (channel * 8)] = dst;
m_g2_dma[channel].root_addr = g2bus_regs[SB_ADSTAR + (channel * 8)] = src;
m_g2_dma[channel].size = g2bus_regs[SB_ADLEN + (channel * 8)] = 0;
m_g2_dma[channel].flag = (m_g2_dma[channel].indirect & 1) ? 1 : 0;
/* Note: if you trigger an instant DMA IRQ trigger, sfz3upper doesn't play any bgm. */
/* TODO: timing of this */
machine().scheduler().timer_set(m_maincpu->cycles_to_attotime(m_g2_dma[channel].size / 4), timer_expired_delegate(FUNC(dc_state::g2_dma_irq), this), channel);
}
int gt64xxx_device::dma_fetch_next(address_space &space, int which)
{
offs_t address = 0;
UINT32 data;
/* no-op for unchained mode */
if (!(m_reg[GREG_DMA0_CONTROL + which] & 0x200))
address = m_reg[GREG_DMA0_NEXT + which];
/* if we hit the end address, signal an interrupt */
if (address == 0)
{
if (m_reg[GREG_DMA0_CONTROL + which] & 0x400)
{
m_reg[GREG_INT_STATE] |= 1 << (GINT_DMA0COMP_SHIFT + which);
update_irqs();
}
m_reg[GREG_DMA0_CONTROL + which] &= ~0x5000;
return 0;
}
/* fetch the byte count */
data = space.read_dword(address); address += 4;
m_reg[GREG_DMA0_COUNT + which] = data;
/* fetch the source address */
data = space.read_dword(address); address += 4;
m_reg[GREG_DMA0_SOURCE + which] = data;
/* fetch the dest address */
data = space.read_dword(address); address += 4;
m_reg[GREG_DMA0_DEST + which] = data;
/* fetch the next record address */
data = space.read_dword(address); address += 4;
m_reg[GREG_DMA0_NEXT + which] = data;
return 1;
}