static void b2m_set_bank(running_machine &machine,int bank)
{
UINT8 *rom;
b2m_state *state = machine.driver_data<b2m_state>();
address_space &space = machine.device("maincpu")->memory().space(AS_PROGRAM);
UINT8 *ram = machine.device<ram_device>(RAM_TAG)->pointer();
space.install_write_bank(0x0000, 0x27ff, "bank1");
space.install_write_bank(0x2800, 0x2fff, "bank2");
space.install_write_bank(0x3000, 0x6fff, "bank3");
space.install_write_bank(0x7000, 0xdfff, "bank4");
space.install_write_bank(0xe000, 0xffff, "bank5");
rom = state->memregion("maincpu")->base();
switch(bank) {
case 0 :
case 1 :
space.unmap_write(0xe000, 0xffff);
state->membank("bank1")->set_base(ram);
state->membank("bank2")->set_base(ram + 0x2800);
state->membank("bank3")->set_base(ram + 0x3000);
state->membank("bank4")->set_base(ram + 0x7000);
state->membank("bank5")->set_base(rom + 0x10000);
break;
#if 0
case 1 :
space.unmap_write(0x3000, 0x6fff);
space.unmap_write(0xe000, 0xffff);
state->membank("bank1")->set_base(ram);
state->membank("bank2")->set_base(ram + 0x2800);
state->membank("bank3")->set_base(rom + 0x12000);
state->membank("bank4")->set_base(rom + 0x16000);
state->membank("bank5")->set_base(rom + 0x10000);
break;
#endif
case 2 :
space.unmap_write(0x2800, 0x2fff);
space.unmap_write(0xe000, 0xffff);
state->membank("bank1")->set_base(ram);
space.install_read_handler(0x2800, 0x2fff, read8_delegate(FUNC(b2m_state::b2m_keyboard_r),state));
state->membank("bank3")->set_base(ram + 0x10000);
state->membank("bank4")->set_base(ram + 0x7000);
state->membank("bank5")->set_base(rom + 0x10000);
break;
case 3 :
space.unmap_write(0x2800, 0x2fff);
space.unmap_write(0xe000, 0xffff);
state->membank("bank1")->set_base(ram);
space.install_read_handler(0x2800, 0x2fff, read8_delegate(FUNC(b2m_state::b2m_keyboard_r),state));
state->membank("bank3")->set_base(ram + 0x14000);
state->membank("bank4")->set_base(ram + 0x7000);
state->membank("bank5")->set_base(rom + 0x10000);
break;
case 4 :
space.unmap_write(0x2800, 0x2fff);
space.unmap_write(0xe000, 0xffff);
state->membank("bank1")->set_base(ram);
space.install_read_handler(0x2800, 0x2fff, read8_delegate(FUNC(b2m_state::b2m_keyboard_r),state));
state->membank("bank3")->set_base(ram + 0x18000);
state->membank("bank4")->set_base(ram + 0x7000);
state->membank("bank5")->set_base(rom + 0x10000);
break;
case 5 :
space.unmap_write(0x2800, 0x2fff);
space.unmap_write(0xe000, 0xffff);
state->membank("bank1")->set_base(ram);
space.install_read_handler(0x2800, 0x2fff, read8_delegate(FUNC(b2m_state::b2m_keyboard_r),state));
state->membank("bank3")->set_base(ram + 0x1c000);
state->membank("bank4")->set_base(ram + 0x7000);
state->membank("bank5")->set_base(rom + 0x10000);
break;
case 6 :
state->membank("bank1")->set_base(ram);
state->membank("bank2")->set_base(ram + 0x2800);
state->membank("bank3")->set_base(ram + 0x3000);
state->membank("bank4")->set_base(ram + 0x7000);
state->membank("bank5")->set_base(ram + 0xe000);
break;
case 7 :
space.unmap_write(0x0000, 0x27ff);
space.unmap_write(0x2800, 0x2fff);
space.unmap_write(0x3000, 0x6fff);
space.unmap_write(0x7000, 0xdfff);
space.unmap_write(0xe000, 0xffff);
state->membank("bank1")->set_base(rom + 0x10000);
state->membank("bank2")->set_base(rom + 0x10000);
state->membank("bank3")->set_base(rom + 0x10000);
state->membank("bank4")->set_base(rom + 0x10000);
state->membank("bank5")->set_base(rom + 0x10000);
break;
}
}
static void internal_timer_update(running_machine &machine,
int which,
int new_count,
int new_maxA,
int new_maxB,
int new_control)
{
compis_state *state = machine.driver_data<compis_state>();
struct timer_state *t = &state->m_i186.timer[which];
int update_int_timer = 0;
/* if we have a new count and we're on, update things */
if (new_count != -1)
{
if (t->control & 0x8000)
{
internal_timer_sync(machine, which);
update_int_timer = 1;
}
t->count = new_count;
}
/* if we have a new max and we're on, update things */
if (new_maxA != -1 && new_maxA != t->maxA)
{
if (t->control & 0x8000)
{
internal_timer_sync(machine, which);
update_int_timer = 1;
}
t->maxA = new_maxA;
if (new_maxA == 0)
{
new_maxA = 0x10000;
}
}
/* if we have a new max and we're on, update things */
if (new_maxB != -1 && new_maxB != t->maxB)
{
if (t->control & 0x8000)
{
internal_timer_sync(machine, which);
update_int_timer = 1;
}
t->maxB = new_maxB;
if (new_maxB == 0)
{
new_maxB = 0x10000;
}
}
/* handle control changes */
if (new_control != -1)
{
int diff;
/* merge back in the bits we don't modify */
new_control = (new_control & ~0x1fc0) | (t->control & 0x1fc0);
/* handle the /INH bit */
if (!(new_control & 0x4000))
new_control = (new_control & ~0x8000) | (t->control & 0x8000);
new_control &= ~0x4000;
/* check for control bits we don't handle */
diff = new_control ^ t->control;
if (diff & 0x001c)
logerror("%05X:ERROR! -unsupported timer mode %04X\n",
cpu_get_pc(machine.device("maincpu")), new_control);
/* if we have real changes, update things */
if (diff != 0)
{
/* if we're going off, make sure our timers are gone */
if ((diff & 0x8000) && !(new_control & 0x8000))
{
/* compute the final count */
internal_timer_sync(machine, which);
/* nuke the timer and force the interrupt timer to be recomputed */
t->time_timer->adjust(attotime::never, which);
t->time_timer_active = 0;
update_int_timer = 1;
}
/* if we're going on, start the timers running */
else if ((diff & 0x8000) && (new_control & 0x8000))
{
/* start the timing */
t->time_timer->adjust(attotime::never, which);
t->time_timer_active = 1;
update_int_timer = 1;
}
/* if something about the interrupt timer changed, force an update */
if (!(diff & 0x8000) && (diff & 0x2000))
{
internal_timer_sync(machine, which);
update_int_timer = 1;
}
}
/* set the new control register */
t->control = new_control;
}
/* update the interrupt timer */
if (update_int_timer)
{
if ((t->control & 0x8000) && (t->control & 0x2000))
{
int diff = t->maxA - t->count;
if (diff <= 0)
diff += 0x10000;
t->int_timer->adjust(attotime::from_hz(2000000) * diff, which);
if (LOG_TIMER) logerror("Set interrupt timer for %d\n", which);
}
else
{
t->int_timer->adjust(attotime::never, which);
}
}
}
static void roldfrog_update_irq( running_machine &machine )
{
splash_state * state = machine.driver_data<splash_state>();
int irq = (state->m_sound_irq ? 0x08 : 0) | ((state->m_vblank_irq) ? 0x18 : 0);
machine.device("audiocpu")->execute().set_input_line_and_vector(0, irq ? ASSERT_LINE : CLEAR_LINE, 0xc7 | irq);
}
static void cybiko_pcf8593_save(running_machine &machine, emu_file *file)
{
device_t *device = machine.device("rtc");
pcf8593_save(device, file);
}
static void update_irq_state(running_machine &machine)
{
artmagic_state *state = machine.driver_data<artmagic_state>();
machine.device("maincpu")->execute().set_input_line(4, state->m_tms_irq ? ASSERT_LINE : CLEAR_LINE);
machine.device("maincpu")->execute().set_input_line(5, state->m_hack_irq ? ASSERT_LINE : CLEAR_LINE);
}
static void tms_interrupt(running_machine &machine, int state)
{
machine.device("maincpu")->execute().set_input_line(INT_TMS34061, state);
}
void address_map::uplift_submaps(running_machine &machine, device_t &device, device_t &owner, endianness_t endian)
{
address_map_entry *prev = 0;
address_map_entry *entry = m_entrylist.first();
while (entry)
{
if (entry->m_read.m_type == AMH_DEVICE_SUBMAP)
{
astring tag;
owner.subtag(tag, entry->m_read.m_tag);
device_t *mapdevice = machine.device(tag);
if (mapdevice == NULL) {
throw emu_fatalerror("Attempted to submap a non-existent device '%s' in space %d of device '%s'\n", tag.cstr(), m_spacenum, device.basetag());
}
// Grab the submap
address_map submap(*mapdevice, entry);
// Recursively uplift it if needed
submap.uplift_submaps(machine, device, *mapdevice, endian);
// Compute the unit repartition characteristics
int entry_bits = entry->m_submap_bits;
if (!entry_bits)
entry_bits = m_databits;
if (submap.m_databits != entry_bits)
throw emu_fatalerror("AM_DEVICE wants a %d bits large address map and got a %d bits large one instead.\n", entry_bits, submap.m_databits);
int entry_bytes = entry_bits / 8;
int databytes = m_databits / 8;
offs_t mirror_address_mask = (databytes - 1) & ~(entry_bytes - 1);
UINT64 entry_mask = (2ULL << (entry_bits-1)) - 1;
int slot_offset[8];
int slot_count = 0;
int max_slot_count = m_databits / entry_bits;
int slot_xor_mask = endian == ENDIANNESS_LITTLE ? 0 : max_slot_count - 1;
UINT64 global_mask = entry->m_read.m_mask;
// zero means all
if (!global_mask)
global_mask = ~global_mask;
// mask consistency has already been checked in
// unitmask_is_appropriate, so one bit is enough
for (int slot=0; slot < max_slot_count; slot++)
if (global_mask & (1ULL << ((slot ^ slot_xor_mask) * entry_bits)))
slot_offset[slot_count++] = (slot ^ slot_xor_mask) * entry_bits;
// Merge in all the map contents in order
while (submap.m_entrylist.count())
{
address_map_entry *subentry = submap.m_entrylist.detach_head();
// Remap start and end
int start_offset = subentry->m_addrstart / entry_bytes;
int start_slot = start_offset % slot_count;
subentry->m_addrstart = entry->m_addrstart + (start_offset / slot_count) * databytes;
// Drop the entry if it ends up outside the range
if (subentry->m_addrstart > entry->m_addrend)
{
global_free(subentry);
continue;
}
int end_offset = subentry->m_addrend / entry_bytes;
int end_slot = end_offset % slot_count;
subentry->m_addrend = entry->m_addrstart + (end_offset / slot_count) * databytes + databytes - 1;
// Clip the entry to the end of the range
if (subentry->m_addrend > entry->m_addrend)
subentry->m_addrend = entry->m_addrend;
// Detect special unhandled case (range straddling
// slots, requiring splitting in multiple entries and
// unimplemented offset-add subunit handler)
if (subentry->m_addrstart + databytes - 1 != subentry->m_addrend &&
(start_slot != 0 || end_slot != slot_count - 1))
throw emu_fatalerror("uplift_submaps unhandled case: range straddling slots.\n");
if (entry->m_addrmask || subentry->m_addrmask)
throw emu_fatalerror("uplift_submaps unhandled case: address masks.\n");
if (subentry->m_addrmirror & mirror_address_mask)
throw emu_fatalerror("uplift_submaps unhandled case: address mirror bit within subentry.\n");
subentry->m_addrmirror |= entry->m_addrmirror;
// Twiddle the unitmask on the data accessors that need it
for (int data_entry = 0; data_entry < 2; data_entry++)
{
map_handler_data &mdata = data_entry ? subentry->m_write : subentry->m_read;
if (mdata.m_type == AMH_NONE)
continue;
if (mdata.m_type != AMH_DEVICE_DELEGATE)
throw emu_fatalerror("Only normal read/write methods are accepted in device submaps.\n");
if (mdata.m_bits == 0 && entry_bits != m_databits)
mdata.m_bits = entry_bits;
UINT64 mask = 0;
if (entry_bits != m_databits)
{
UINT64 unitmask = mdata.m_mask ? mdata.m_mask : entry_mask;
for (int slot = start_slot; slot <= end_slot; slot++)
mask |= unitmask << slot_offset[slot];
}
mdata.m_mask = mask;
}
// Insert the entry in the map
m_entrylist.insert_after(*subentry, prev);
prev = subentry;
}
address_map_entry *to_delete = entry;
entry = entry->next();
m_entrylist.remove(*to_delete);
}
else
{
prev = entry;
entry = entry->next();
}
}
}
void ti990_hold_load(running_machine &machine)
{
machine.device("maincpu")->execute().set_input_line(INPUT_LINE_NMI, ASSERT_LINE);
machine.scheduler().timer_set(attotime::from_msec(100), FUNC(clear_load));
}
static void dmac_install(running_machine &machine, offs_t base)
{
address_space *space = machine.device("maincpu")->memory().space(AS_PROGRAM);
space->install_legacy_read_handler(base, base + 0xFFFF, FUNC(amiga_dmac_r));
space->install_legacy_write_handler(base, base + 0xFFFF, FUNC(amiga_dmac_w));
}
static void update_ti83p_memory (running_machine &machine)
{
ti85_state *state = machine.driver_data<ti85_state>();
address_space *space = machine.device("maincpu")->memory().space(AS_PROGRAM);
if (state->m_ti8x_memory_page_1 & 0x40)
{
if (state->m_ti83p_port4 & 1)
{
memory_set_bankptr(machine, "bank3", state->m_ti8x_ram + 0x004000*(state->m_ti8x_memory_page_1&0x01));
space->install_write_bank(0x8000, 0xbfff, "bank3");
}
else
{
memory_set_bankptr(machine, "bank2", state->m_ti8x_ram + 0x004000*(state->m_ti8x_memory_page_1&0x01));
space->install_write_bank(0x4000, 0x7fff, "bank2");
}
}
else
{
if (state->m_ti83p_port4 & 1)
{
memory_set_bankptr(machine, "bank3", machine.region("maincpu")->base() + 0x010000 + 0x004000*(state->m_ti8x_memory_page_1&0x1f));
space->unmap_write(0x8000, 0xbfff);
}
else
{
memory_set_bankptr(machine, "bank2", machine.region("maincpu")->base() + 0x010000 + 0x004000*(state->m_ti8x_memory_page_1&0x1f));
space->unmap_write(0x4000, 0x7fff);
}
}
if (state->m_ti8x_memory_page_2 & 0x40)
{
if (state->m_ti83p_port4 & 1)
{
memory_set_bankptr(machine, "bank4", state->m_ti8x_ram + 0x004000*(state->m_ti8x_memory_page_2&0x01));
space->install_write_bank(0xc000, 0xffff, "bank4");
}
else
{
memory_set_bankptr(machine, "bank3", state->m_ti8x_ram + 0x004000*(state->m_ti8x_memory_page_2&0x01));
space->install_write_bank(0x8000, 0xbfff, "bank3");
}
}
else
{
if (state->m_ti83p_port4 & 1)
{
memory_set_bankptr(machine, "bank4", machine.region("maincpu")->base() + 0x010000 + 0x004000*(state->m_ti8x_memory_page_2&0x1f));
space->unmap_write(0xc000, 0xffff);
}
else
{
memory_set_bankptr(machine, "bank3", machine.region("maincpu")->base() + 0x010000 + 0x004000*(state->m_ti8x_memory_page_2&0x1f));
space->unmap_write(0x8000, 0xbfff);
}
}
}
static void ti8x_snapshot_setup_registers (running_machine &machine, UINT8 * data)
{
unsigned char lo,hi;
unsigned char * reg = data + 0x40;
/* Set registers */
lo = reg[0x00] & 0x0ff;
hi = reg[0x01] & 0x0ff;
cpu_set_reg(machine.device("maincpu"), Z80_AF, (hi << 8) | lo);
lo = reg[0x04] & 0x0ff;
hi = reg[0x05] & 0x0ff;
cpu_set_reg(machine.device("maincpu"), Z80_BC, (hi << 8) | lo);
lo = reg[0x08] & 0x0ff;
hi = reg[0x09] & 0x0ff;
cpu_set_reg(machine.device("maincpu"), Z80_DE, (hi << 8) | lo);
lo = reg[0x0c] & 0x0ff;
hi = reg[0x0d] & 0x0ff;
cpu_set_reg(machine.device("maincpu"), Z80_HL, (hi << 8) | lo);
lo = reg[0x10] & 0x0ff;
hi = reg[0x11] & 0x0ff;
cpu_set_reg(machine.device("maincpu"), Z80_IX, (hi << 8) | lo);
lo = reg[0x14] & 0x0ff;
hi = reg[0x15] & 0x0ff;
cpu_set_reg(machine.device("maincpu"), Z80_IY, (hi << 8) | lo);
lo = reg[0x18] & 0x0ff;
hi = reg[0x19] & 0x0ff;
cpu_set_reg(machine.device("maincpu"), Z80_PC, (hi << 8) | lo);
lo = reg[0x1c] & 0x0ff;
hi = reg[0x1d] & 0x0ff;
cpu_set_reg(machine.device("maincpu"), Z80_SP, (hi << 8) | lo);
lo = reg[0x20] & 0x0ff;
hi = reg[0x21] & 0x0ff;
cpu_set_reg(machine.device("maincpu"), Z80_AF2, (hi << 8) | lo);
lo = reg[0x24] & 0x0ff;
hi = reg[0x25] & 0x0ff;
cpu_set_reg(machine.device("maincpu"), Z80_BC2, (hi << 8) | lo);
lo = reg[0x28] & 0x0ff;
hi = reg[0x29] & 0x0ff;
cpu_set_reg(machine.device("maincpu"), Z80_DE2, (hi << 8) | lo);
lo = reg[0x2c] & 0x0ff;
hi = reg[0x2d] & 0x0ff;
cpu_set_reg(machine.device("maincpu"), Z80_HL2, (hi << 8) | lo);
cpu_set_reg(machine.device("maincpu"), Z80_IFF1, reg[0x30]&0x0ff);
cpu_set_reg(machine.device("maincpu"), Z80_IFF2, reg[0x34]&0x0ff);
cpu_set_reg(machine.device("maincpu"), Z80_HALT, reg[0x38]&0x0ff);
cpu_set_reg(machine.device("maincpu"), Z80_IM, reg[0x3c]&0x0ff);
cpu_set_reg(machine.device("maincpu"), Z80_I, reg[0x40]&0x0ff);
cpu_set_reg(machine.device("maincpu"), Z80_R, (reg[0x44]&0x7f) | (reg[0x48]&0x80));
cputag_set_input_line(machine, "maincpu", 0, 0);
cputag_set_input_line(machine, "maincpu", INPUT_LINE_NMI, 0);
cputag_set_input_line(machine, "maincpu", INPUT_LINE_HALT, 0);
}
static void init_ram_handler(running_machine &machine, offs_t start, offs_t size, offs_t mirror)
{
machine.device("maincpu")->memory().space(AS_PROGRAM)->install_read_bank(start, start + size - 1, 0, mirror - size, "bank1");
machine.device("maincpu")->memory().space(AS_PROGRAM)->install_write_bank(start, start + size - 1, 0, mirror - size, "bank1");
memory_set_bankptr( machine, "bank1", ram_get_ptr(machine.device(RAM_TAG)));
}
static void cybiko_sst39vfx_save(running_machine &machine, emu_file *file)
{
device_t *device = machine.device("flash2");
sst39vfx_save(device, file);
}
static void cybiko_at45dbxx_save(running_machine &machine, emu_file *file)
{
device_t *device = machine.device("flash1");
at45dbxx_save(device, file);
}
static void famicombox_reset(running_machine &machine)
{
famicombox_bankswitch(machine, 0);
machine.device("maincpu")->reset();
}
static void dmac_uninstall(running_machine &machine, offs_t base)
{
address_space *space = machine.device("maincpu")->memory().space(AS_PROGRAM);
space->unmap_readwrite(base, base + 0xFFFF);
}
static void command_verify_memory(running_machine &machine)
{
int i = 0;
offs_t offset, offset_start, offset_end;
const UINT8 *verify_data;
size_t verify_data_size;
const UINT8 *target_data = NULL;
size_t target_data_size = 0;
const char *region;
const char *cpu_name;
offset_start = current_command->u.verify_args.start;
offset_end = current_command->u.verify_args.end;
verify_data = (const UINT8 *) current_command->u.verify_args.verify_data;
verify_data_size = current_command->u.verify_args.verify_data_size;
if (offset_end == 0)
offset_end = offset_start + verify_data_size - 1;
cpu_name = current_command->u.verify_args.cpu_name;
/* what type of memory are we validating? */
region = current_command->u.verify_args.mem_region;
if (region)
{
/* we're validating a conventional memory region */
target_data = machine.region(region)->base();
target_data_size = machine.region(region)->bytes();
}
/* sanity check the ranges */
if (!verify_data || (verify_data_size <= 0))
{
state = STATE_ABORTED;
report_message(MSG_FAILURE, "Invalid memory region during verify");
return;
}
if (offset_start > offset_end)
{
state = STATE_ABORTED;
report_message(MSG_FAILURE, "Invalid verify offset range (0x%x-0x%x)", offset_start, offset_end);
return;
}
if (region) {
if (offset_end >= target_data_size)
{
state = STATE_ABORTED;
report_message(MSG_FAILURE, "Verify memory range out of bounds");
return;
}
} else {
if (cpu_name==NULL) {
state = STATE_ABORTED;
report_message(MSG_FAILURE, "If region is not defined then cpu must be");
return;
}
}
/* loop through the memory, verifying it byte by byte */
for (offset = offset_start; offset <= offset_end; offset++)
{
if (region) {
if (verify_data[i] != target_data[offset])
{
state = STATE_ABORTED;
report_message(MSG_FAILURE, "Failed verification step (region %s; 0x%x-0x%x)",
region, offset_start, offset_end);
break;
}
} else {
address_space *space = machine.device(cpu_name)->memory().space(AS_PROGRAM);
if (verify_data[i] != space->read_byte(offset))
{
state = STATE_ABORTED;
report_message(MSG_FAILURE, "Failed verification step (0x%x-0x%x)",
offset_start, offset_end);
break;
}
}
i = (i + 1) % verify_data_size;
}
}
INPUT_PORTS_END
static void magtouch_set_keyb_int(running_machine &machine, int state)
{
pic8259_ir1_w(machine.device("pic8259_1"), state);
}
static void svi318_set_banks(running_machine &machine)
{
svi318_state *state = machine.driver_data<svi318_state>();
const UINT8 v = state->m_svi.bank_switch;
UINT8 *ram = ram_get_ptr(machine.device(RAM_TAG));
UINT32 ram_size = ram_get_size(machine.device(RAM_TAG));
state->m_svi.bankLow = ( v & 1 ) ? ( ( v & 2 ) ? ( ( v & 8 ) ? SVI_INTERNAL : SVI_EXPRAM3 ) : SVI_EXPRAM2 ) : SVI_CART;
state->m_svi.bankHigh1 = ( v & 4 ) ? ( ( v & 16 ) ? SVI_INTERNAL : SVI_EXPRAM3 ) : SVI_EXPRAM2;
state->m_svi.bankLow_ptr = state->m_svi.empty_bank;
state->m_svi.bankLow_read_only = 1;
switch( state->m_svi.bankLow )
{
case SVI_INTERNAL:
state->m_svi.bankLow_ptr = machine.region("maincpu")->base();
break;
case SVI_CART:
if ( state->m_pcart )
{
state->m_svi.bankLow_ptr = state->m_pcart;
}
break;
case SVI_EXPRAM2:
if ( ram_size >= 64 * 1024 )
{
state->m_svi.bankLow_ptr = ram + ram_size - 64 * 1024;
state->m_svi.bankLow_read_only = 0;
}
break;
case SVI_EXPRAM3:
if ( ram_size > 128 * 1024 )
{
state->m_svi.bankLow_ptr = ram + ram_size - 128 * 1024;
state->m_svi.bankLow_read_only = 0;
}
break;
}
state->m_svi.bankHigh1_ptr = state->m_svi.bankHigh2_ptr = state->m_svi.empty_bank;
state->m_svi.bankHigh1_read_only = state->m_svi.bankHigh2_read_only = 1;
switch( state->m_svi.bankHigh1 )
{
case SVI_INTERNAL:
if ( ram_size == 16 * 1024 )
{
state->m_svi.bankHigh2_ptr = ram;
state->m_svi.bankHigh2_read_only = 0;
}
else
{
state->m_svi.bankHigh1_ptr = ram;
state->m_svi.bankHigh1_read_only = 0;
state->m_svi.bankHigh2_ptr = ram + 0x4000;
state->m_svi.bankHigh2_read_only = 0;
}
break;
case SVI_EXPRAM2:
if ( ram_size > 64 * 1024 )
{
state->m_svi.bankHigh1_ptr = ram + ram_size - 64 * 1024 + 32 * 1024;
state->m_svi.bankHigh1_read_only = 0;
state->m_svi.bankHigh2_ptr = ram + ram_size - 64 * 1024 + 48 * 1024;
state->m_svi.bankHigh2_read_only = 0;
}
break;
case SVI_EXPRAM3:
if ( ram_size > 128 * 1024 )
{
state->m_svi.bankHigh1_ptr = ram + ram_size - 128 * 1024 + 32 * 1024;
state->m_svi.bankHigh1_read_only = 0;
state->m_svi.bankHigh2_ptr = ram + ram_size - 128 * 1024 + 48 * 1024;
state->m_svi.bankHigh2_read_only = 0;
}
break;
}
/* Check for special CART based banking */
if ( state->m_svi.bankLow == SVI_CART && ( v & 0xc0 ) != 0xc0 )
{
state->m_svi.bankHigh1_ptr = state->m_svi.empty_bank;
state->m_svi.bankHigh1_read_only = 1;
state->m_svi.bankHigh2_ptr = state->m_svi.empty_bank;
state->m_svi.bankHigh2_read_only = 1;
if ( state->m_pcart && ! ( v & 0x80 ) )
{
state->m_svi.bankHigh2_ptr = state->m_pcart + 0x4000;
}
if ( state->m_pcart && ! ( v & 0x40 ) )
{
state->m_svi.bankHigh1_ptr = state->m_pcart;
}
}
memory_set_bankptr(machine, "bank1", state->m_svi.bankLow_ptr );
memory_set_bankptr(machine, "bank2", state->m_svi.bankHigh1_ptr );
memory_set_bankptr(machine, "bank3", state->m_svi.bankHigh2_ptr );
/* SVI-806 80 column card specific banking */
if ( state->m_svi.svi806_present )
{
if ( state->m_svi.svi806_ram_enabled )
{
memory_set_bankptr(machine, "bank4", state->m_svi.svi806_ram );
}
else
{
memory_set_bankptr(machine, "bank4", state->m_svi.bankHigh2_ptr + 0x3000 );
}
}
}
static void magtouch_microtouch_tx_callback(running_machine &machine, UINT8 data)
{
ins8250_receive(machine.device("ns16450_0"), data);
};
void psx_irq_set( running_machine &machine, UINT32 data )
{
psxcpu_device::irq_set( *machine.device("maincpu^"), "maincpu", data );
}
static void orionpro_bank_switch(running_machine &machine)
{
orion_state *state = machine.driver_data<orion_state>();
address_space *space = machine.device("maincpu")->memory().space(AS_PROGRAM);
int page = state->m_orionpro_page & 7; // we have only 8 pages
int is128 = (state->m_orionpro_dispatcher & 0x80) ? 1 : 0;
UINT8 *ram = ram_get_ptr(machine.device(RAM_TAG));
if (is128==1)
{
page = state->m_orionpro_128_page & 7;
}
space->install_write_bank(0x0000, 0x1fff, "bank1");
space->install_write_bank(0x2000, 0x3fff, "bank2");
space->install_write_bank(0x4000, 0x7fff, "bank3");
space->install_write_bank(0x8000, 0xbfff, "bank4");
space->install_write_bank(0xc000, 0xefff, "bank5");
space->install_write_bank(0xf000, 0xf3ff, "bank6");
space->install_write_bank(0xf400, 0xf7ff, "bank7");
space->install_write_bank(0xf800, 0xffff, "bank8");
if ((state->m_orionpro_dispatcher & 0x01)==0x00)
{ // RAM0 segment disabled
memory_set_bankptr(machine, "bank1", ram + 0x10000 * page);
memory_set_bankptr(machine, "bank2", ram + 0x10000 * page + 0x2000);
}
else
{
memory_set_bankptr(machine, "bank1", ram + (state->m_orionpro_ram0_segment & 31) * 0x4000);
memory_set_bankptr(machine, "bank2", ram + (state->m_orionpro_ram0_segment & 31) * 0x4000 + 0x2000);
}
if ((state->m_orionpro_dispatcher & 0x10)==0x10)
{ // ROM1 enabled
space->unmap_write(0x0000, 0x1fff);
memory_set_bankptr(machine, "bank1", machine.region("maincpu")->base() + 0x20000);
}
if ((state->m_orionpro_dispatcher & 0x08)==0x08)
{ // ROM2 enabled
space->unmap_write(0x2000, 0x3fff);
memory_set_bankptr(machine, "bank2", machine.region("maincpu")->base() + 0x22000 + (state->m_orionpro_rom2_segment & 7) * 0x2000);
}
if ((state->m_orionpro_dispatcher & 0x02)==0x00)
{ // RAM1 segment disabled
memory_set_bankptr(machine, "bank3", ram + 0x10000 * page + 0x4000);
}
else
{
memory_set_bankptr(machine, "bank3", ram + (state->m_orionpro_ram1_segment & 31) * 0x4000);
}
if ((state->m_orionpro_dispatcher & 0x04)==0x00)
{ // RAM2 segment disabled
memory_set_bankptr(machine, "bank4", ram + 0x10000 * page + 0x8000);
}
else
{
memory_set_bankptr(machine, "bank4", ram + (state->m_orionpro_ram2_segment & 31) * 0x4000);
}
memory_set_bankptr(machine, "bank5", ram + 0x10000 * page + 0xc000);
if (is128)
{
memory_set_bankptr(machine, "bank6", ram + 0x10000 * 0 + 0xf000);
space->install_legacy_write_handler(0xf400, 0xf4ff, FUNC(orion128_system_w));
space->install_legacy_write_handler(0xf500, 0xf5ff, FUNC(orion128_romdisk_w));
space->unmap_write(0xf600, 0xf6ff);
space->install_legacy_write_handler(0xf700, 0xf7ff, FUNC(orion128_floppy_w));
space->install_legacy_read_handler(0xf400, 0xf4ff, FUNC(orion128_system_r));
space->install_legacy_read_handler(0xf500, 0xf5ff, FUNC(orion128_romdisk_r));
space->unmap_read(0xf600, 0xf6ff);
space->install_legacy_read_handler(0xf700, 0xf7ff, FUNC(orion128_floppy_r));
space->install_legacy_write_handler(0xf800, 0xf8ff, FUNC(orion128_video_mode_w));
space->install_legacy_write_handler(0xf900, 0xf9ff, FUNC(orionpro_memory_page_w));
space->install_legacy_write_handler(0xfa00, 0xfaff, FUNC(orion128_video_page_w));
space->unmap_write(0xfb00, 0xfeff);
space->install_legacy_write_handler(0xff00, 0xffff, FUNC(orionz80_sound_w));
memory_set_bankptr(machine, "bank8", ram + 0x10000 * 0 + 0xf800);
}
else
{
if ((state->m_orionpro_dispatcher & 0x40)==0x40)
{ // FIX F000 enabled
memory_set_bankptr(machine, "bank6", ram + 0x10000 * 0 + 0xf000);
memory_set_bankptr(machine, "bank7", ram + 0x10000 * 0 + 0xf400);
memory_set_bankptr(machine, "bank8", ram + 0x10000 * 0 + 0xf800);
}
else
{
memory_set_bankptr(machine, "bank6", ram + 0x10000 * page + 0xf000);
memory_set_bankptr(machine, "bank7", ram + 0x10000 * page + 0xf400);
memory_set_bankptr(machine, "bank8", ram + 0x10000 * page + 0xf800);
}
}
}
