static void at91sam9260ek_macb_hw_init(void) { struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA; struct at91_rstc *rstc = (struct at91_rstc *)ATMEL_BASE_RSTC; unsigned long erstl; /* Enable EMAC clock */ writel(1 << ATMEL_ID_EMAC0, &pmc->pcer); /* * Disable pull-up on: * RXDV (PA17) => PHY normal mode (not Test mode) * ERX0 (PA14) => PHY ADDR0 * ERX1 (PA15) => PHY ADDR1 * ERX2 (PA25) => PHY ADDR2 * ERX3 (PA26) => PHY ADDR3 * ECRS (PA28) => PHY ADDR4 => PHYADDR = 0x0 * * PHY has internal pull-down */ writel(pin_to_mask(AT91_PIN_PA14) | pin_to_mask(AT91_PIN_PA15) | pin_to_mask(AT91_PIN_PA17) | pin_to_mask(AT91_PIN_PA25) | pin_to_mask(AT91_PIN_PA26) | pin_to_mask(AT91_PIN_PA28), &pioa->pudr); erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK; /* Need to reset PHY -> 500ms reset */ writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(13) | AT91_RSTC_MR_URSTEN, &rstc->mr); writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr); /* Wait for end hardware reset */ while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL)) ; /* Restore NRST value */ writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN, &rstc->mr); /* Re-enable pull-up */ writel(pin_to_mask(AT91_PIN_PA14) | pin_to_mask(AT91_PIN_PA15) | pin_to_mask(AT91_PIN_PA17) | pin_to_mask(AT91_PIN_PA25) | pin_to_mask(AT91_PIN_PA26) | pin_to_mask(AT91_PIN_PA28), &pioa->puer); /* Initialize EMAC=MACB hardware */ at91_macb_hw_init(); }
static void macb_hw_init(void) { struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA; struct at91_rstc *rstc = (struct at91_rstc *)ATMEL_BASE_RSTC; unsigned long erstl; /* Enable clock */ writel(1 << ATMEL_ID_EMAC0, &pmc->pcer); /* Disable pull-ups to prevent PHY going into test mode */ writel(pin_to_mask(AT91_PIN_PA14) | pin_to_mask(AT91_PIN_PA15) | pin_to_mask(AT91_PIN_PA18), &pioa->pudr); /* Power down ethernet */ pca953x_set_dir(0x28, IO_EXP_ETH_POWER, PCA953X_DIR_OUT); pca953x_set_val(0x28, IO_EXP_ETH_POWER, 1); /* Hold ethernet in reset */ pca953x_set_dir(0x28, IO_EXP_ETH_RESET, PCA953X_DIR_OUT); pca953x_set_val(0x28, IO_EXP_ETH_RESET, 0); /* Enable ethernet power */ pca953x_set_val(0x28, IO_EXP_ETH_POWER, 0); /* Need to reset PHY -> 500ms reset */ erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK; writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(13) | AT91_RSTC_MR_URSTEN, &rstc->mr); writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr); /* Wait for end hardware reset */ while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL)) ; /* Restore NRST value */ writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN, &rstc->mr); /* Bring the ethernet out of reset */ pca953x_set_val(0x28, IO_EXP_ETH_RESET, 1); /* The phy internal reset take 21ms */ udelay(21 * 1000); /* Re-enable pull-up */ writel(pin_to_mask(AT91_PIN_PA14) | pin_to_mask(AT91_PIN_PA15) | pin_to_mask(AT91_PIN_PA18), &pioa->puer); at91_macb_hw_init(); }
void at91_phy_reset(void) { unsigned long erstl; unsigned long start = get_timer(0); unsigned long const timeout = 1000; /* 1000ms */ at91_rstc_t *rstc = (at91_rstc_t *)ATMEL_BASE_RSTC; erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK; /* * Need to reset PHY -> 500ms reset * Reset PHY by pulling the NRST line for 500ms to low. To do so * disable user reset for low level on NRST pin and poll the NRST * level in reset status register. */ writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(0x0D) | AT91_RSTC_MR_URSTEN, &rstc->mr); writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr); /* Wait for end of hardware reset */ while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL)) { /* avoid shutdown by watchdog */ WATCHDOG_RESET(); mdelay(10); /* timeout for not getting stuck in an endless loop */ if (get_timer(start) >= timeout) { puts("*** ERROR: Timeout waiting for PHY reset!\n"); break; } }; /* Restore NRST value */ writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN, &rstc->mr); }
void at91_macb_hw_init(void) { at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; struct at91_rstc *rstc = (struct at91_rstc *)ATMEL_BASE_RSTC; unsigned long erstl; erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK; /* Need to reset PHY -> 500ms reset */ writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(13) | AT91_RSTC_MR_URSTEN, &rstc->mr); writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr); /* Wait for end hardware reset */ while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL)) ; /* Restore NRST value */ writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN, &rstc->mr); if (has_emac0()) { /* Enable EMAC0 clock */ writel(1 << ATMEL_ID_EMAC0, &pmc->pcer); /* EMAC0 pins setup */ at91_set_a_periph(AT91_PIO_PORTB, 4, 0); /* ETXCK */ at91_set_a_periph(AT91_PIO_PORTB, 3, 0); /* ERXDV */ at91_set_a_periph(AT91_PIO_PORTB, 0, 0); /* ERX0 */ at91_set_a_periph(AT91_PIO_PORTB, 1, 0); /* ERX1 */ at91_set_a_periph(AT91_PIO_PORTB, 2, 0); /* ERXER */ at91_set_a_periph(AT91_PIO_PORTB, 7, 0); /* ETXEN */ at91_set_a_periph(AT91_PIO_PORTB, 9, 0); /* ETX0 */ at91_set_a_periph(AT91_PIO_PORTB, 10, 0); /* ETX1 */ at91_set_a_periph(AT91_PIO_PORTB, 5, 0); /* EMDIO */ at91_set_a_periph(AT91_PIO_PORTB, 6, 0); /* EMDC */ } if (has_emac1()) { /* Enable EMAC1 clock */ writel(1 << ATMEL_ID_EMAC1, &pmc->pcer); /* EMAC1 pins setup */ at91_set_b_periph(AT91_PIO_PORTC, 29, 0); /* ETXCK */ at91_set_b_periph(AT91_PIO_PORTC, 28, 0); /* ECRSDV */ at91_set_b_periph(AT91_PIO_PORTC, 20, 0); /* ERXO */ at91_set_b_periph(AT91_PIO_PORTC, 21, 0); /* ERX1 */ at91_set_b_periph(AT91_PIO_PORTC, 16, 0); /* ERXER */ at91_set_b_periph(AT91_PIO_PORTC, 27, 0); /* ETXEN */ at91_set_b_periph(AT91_PIO_PORTC, 18, 0); /* ETX0 */ at91_set_b_periph(AT91_PIO_PORTC, 19, 0); /* ETX1 */ at91_set_b_periph(AT91_PIO_PORTC, 31, 0); /* EMDIO */ at91_set_b_periph(AT91_PIO_PORTC, 30, 0); /* EMDC */ } #ifndef CONFIG_RMII /* Only emac0 support MII */ if (has_emac0()) { at91_set_a_periph(AT91_PIO_PORTB, 16, 0); /* ECRS */ at91_set_a_periph(AT91_PIO_PORTB, 17, 0); /* ECOL */ at91_set_a_periph(AT91_PIO_PORTB, 13, 0); /* ERX2 */ at91_set_a_periph(AT91_PIO_PORTB, 14, 0); /* ERX3 */ at91_set_a_periph(AT91_PIO_PORTB, 15, 0); /* ERXCK */ at91_set_a_periph(AT91_PIO_PORTB, 11, 0); /* ETX2 */ at91_set_a_periph(AT91_PIO_PORTB, 12, 0); /* ETX3 */ at91_set_a_periph(AT91_PIO_PORTB, 8, 0); /* ETXER */ } #endif }
static void stamp9G20_macb_hw_init(void) { struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA; struct at91_rstc *rstc = (struct at91_rstc *)ATMEL_BASE_RSTC; unsigned long erstl; /* Enable the PHY Chip via PA26 on the Stamp 2 Adaptor */ at91_set_gpio_output(AT91_PIN_PA26, 0); /* * Disable pull-up on: * RXDV (PA17) => PHY normal mode (not Test mode) * ERX0 (PA14) => PHY ADDR0 * ERX1 (PA15) => PHY ADDR1 * ERX2 (PA25) => PHY ADDR2 * ERX3 (PA26) => PHY ADDR3 * ECRS (PA28) => PHY ADDR4 => PHYADDR = 0x0 * * PHY has internal pull-down */ writel(pin_to_mask(AT91_PIN_PA14) | pin_to_mask(AT91_PIN_PA15) | pin_to_mask(AT91_PIN_PA17) | pin_to_mask(AT91_PIN_PA18) | pin_to_mask(AT91_PIN_PA28), &pioa->pudr); erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK; /* Need to reset PHY -> 500ms reset */ writel(AT91_RSTC_KEY | (AT91_RSTC_MR_ERSTL(13) & ~AT91_RSTC_MR_URSTEN), &rstc->mr); writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr); /* Wait for end of hardware reset */ unsigned long start = get_timer(0); unsigned long timeout = 1000; /* 1000ms */ while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL)) { /* avoid shutdown by watchdog */ WATCHDOG_RESET(); mdelay(10); /* timeout for not getting stuck in an endless loop */ if (get_timer(start) >= timeout) { puts("*** ERROR: Timeout waiting for PHY reset!\n"); break; }; }; /* Restore NRST value */ writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN, &rstc->mr); /* Re-enable pull-up */ writel(pin_to_mask(AT91_PIN_PA14) | pin_to_mask(AT91_PIN_PA15) | pin_to_mask(AT91_PIN_PA17) | pin_to_mask(AT91_PIN_PA18) | pin_to_mask(AT91_PIN_PA28), &pioa->puer); /* Initialize EMAC=MACB hardware */ at91_macb_hw_init(); }